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Demo

helloworld

This a demo for llvm build and sim with verilator.

jtag

This is a demo of jtag simulation by openocd running on verilator.

install verilator

sudo apt install verilator

install openocd

git clone https://github.com/riscv/riscv-openocd.git
cd riscv-openocd
./bootstrap
./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
make
sudo make install

may be install sv2v

https://github.com/zachjs/sv2v

install ninja

sudo apt-get install -y ninja-build

Gen quasar core

git clone https://github.com/Lampro-Mellon/Quasar.git
cd tools
vim configs/quasar.config # to config the core
make clean
make conf
make sbt_
# Quasar/generated_rtl/quasar_wrapper.sv

install Bit-Vector

wget https://cpan.metacpan.org/authors/id/S/ST/STBEY/Bit-Vector-7.4.tar.gz
tar -xvf
cd 
perl Makefile.PL
make 
sudo make install

build and install riscv tools

Opetion1 :https://github.com/riscv-collab/riscv-gnu-toolchain.git

sudo make clean
./configure --prefix=/opt/riscv # build 64bit
sudo make -j12
sudo make clean
./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d
sudo make -j12

Opetion2 :

sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev
git clone https://github.com/chipsalliance/rocket-tools.git
git submodule update --init --recursive
# riscv-isa-sim and openocd may be checkout to main branch to avoid compile error
sudo su
export RISCV=/opt/riscv
export MAKEFLAGS="-j12"
./build-rv32ima.sh

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