40 lines
1.0 KiB
Markdown
40 lines
1.0 KiB
Markdown
# Demo
|
|
|
|
## helloworld
|
|
|
|
This a demo for llvm build and sim with verilator.
|
|
|
|
## jtag
|
|
|
|
This is a demo of jtag simulation by openocd running on verilator.
|
|
|
|
## install verilator
|
|
|
|
`sudo apt install verilator`
|
|
|
|
## install openocd
|
|
|
|
```shell
|
|
git clone https://github.com/riscv/riscv-openocd.git
|
|
cd riscv-openocd
|
|
./bootstrap
|
|
./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
|
|
make
|
|
sudo make install
|
|
```
|
|
|
|
## build and install riscv tools
|
|
|
|
* Opetion1 :https://github.com/riscv-collab/riscv-gnu-toolchain.git
|
|
* Opetion2 :
|
|
|
|
```bash
|
|
sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev
|
|
git clone https://github.com/chipsalliance/rocket-tools.git
|
|
git submodule update --init --recursive
|
|
# riscv-isa-sim and openocd may be checkout to main branch to avoid compile error
|
|
sudo su
|
|
export RISCV=/opt/riscv
|
|
export MAKEFLAGS="-j12"
|
|
./build-rv32ima.sh
|
|
``` |