50 lines
957 B
Verilog
50 lines
957 B
Verilog
module ram_single(dataout, addr, datain, we, clk);
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output[7:0] dataout;
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input [7:0] datain;
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input [10:0] addr;
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input we, clk;
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reg [7:0] mem [2048:0];
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always @(posedge clk) begin
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if (we)
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mem[addr] <= datain;
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dataout <= mem[addr];
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end
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endmodule
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module ram (
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input clk_i,
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output reg led_o
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);
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localparam MAX = 2_500_000_0;
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localparam WIDTH = $clog2(MAX);
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wire[7:0] dataout;
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reg[7:0] datain;
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reg[10:0] addr;
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reg we;
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ram_single mem(.dataout(dataout), .addr(addr), .datain(datain), .we(we), .clk(clk_i));
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wire clk_s;
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assign clk_s = clk_i;
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reg [WIDTH-1:0] cpt_s;
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wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
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wire end_s = cpt_s == MAX-1;
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wire nextAddr = addr + 1'b1;
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wire dataAdd = dataout + 1'b1;
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always @(posedge clk_s) begin
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cpt_s <= cpt_next_s;
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addr <= nextAddr;
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datain <= dataAdd;
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led_o <= dataout[0];
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// if (end_s)
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// led_o <= ~led_o;
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end
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endmodule
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