92 lines
2.1 KiB
Verilog
92 lines
2.1 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module px_had_sync(
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clk1,
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clk2,
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rst1_b,
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rst2_b,
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sync_in,
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sync_out
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);
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// &Ports; @22
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input clk1;
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input clk2;
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input rst1_b;
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input rst2_b;
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input sync_in;
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output sync_out;
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// &Regs; @23
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reg sync_ff1_clk1;
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reg sync_ff2_clk1;
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reg sync_ff3_clk1;
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reg sync_ff_clk2;
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// &Wires; @24
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wire clk1;
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wire clk2;
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wire rst1_b;
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wire rst2_b;
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wire sync_in;
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wire sync_out;
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//==============================================================================
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// sync logic from clk2 to clk1
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// step 1. flop once in clk2 domain
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// step 2. flop twice in clk1 domain
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// result: a pulse signal in clk1 domain
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// constraint: slow clock --> fast clock
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//==============================================================================
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always @(posedge clk2 or negedge rst2_b)
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begin
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if (!rst2_b)
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sync_ff_clk2 <= 1'b0;
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else
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sync_ff_clk2 <= sync_in;
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end
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always @(posedge clk1 or negedge rst1_b)
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begin
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if (!rst1_b) begin
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sync_ff1_clk1 <= 1'b0;
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sync_ff2_clk1 <= 1'b0;
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end
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else begin
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sync_ff1_clk1 <= sync_ff_clk2;
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sync_ff2_clk1 <= sync_ff1_clk1;
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end
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end
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// generates a pulse signal in clk1 domain
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always @(posedge clk1 or negedge rst1_b)
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begin
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if (!rst1_b)
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sync_ff3_clk1 <= 1'b0;
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else
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sync_ff3_clk1 <= sync_ff2_clk1;
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end
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assign sync_out = !sync_ff3_clk1 && sync_ff2_clk1;
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// &ModuleEnd; @66
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endmodule
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