137 lines
5.9 KiB
Markdown
137 lines
5.9 KiB
Markdown
# SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
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This repository contains the SweRV Core<sup>TM</sup> 1.5 design RTL. The previous version can be found in [branch 1.4.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.4)
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The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
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## License
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By contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).
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Files under the [tools](tools/) directory may be available under a different license. Please review individual file for details.
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## Directory Structure
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├── configs # Configurations Dir
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│ └── snapshots # Where generated configuration files are created
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├── design # Design root dir
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│ ├── dbg # Debugger
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│ ├── dec # Decode, Registers and Exceptions
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│ ├── dmi # DMI block
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│ ├── exu # EXU (ALU/MUL/DIV)
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│ ├── ifu # Fetch & Branch Prediction
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│ ├── include
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│ ├── lib
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│ └── lsu # Load/Store
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├── docs
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├── tools # Scripts/Makefiles
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└── testbench # (Very) simple testbench
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├── asm # Example assembly files
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└── hex # Canned demo hex files
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## Dependencies
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- Verilator **(3.926 or later)** must be installed on the system
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- If adding/removing instructions, espresso must be installed. Espresso is a logic minimization tool used in *tools/coredecode*.
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## Quickstart guide
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1. Clone the repository
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1. Setup RV_ROOT to point to the path in your local filesystem
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1. Determine your configuration {optional}
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1. Run make with tools/Makefile
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## Release Notes for this version
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Please see [release notes](release-notes.md) for changes and bug fixes in this version of SweRV
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### Configurations
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SweRV can be configured by running the `$RV_ROOT/configs/swerv.config` script:
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`% $RV_ROOT/configs/swerv.config -h` for detailed help options
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For example to build with a DCCM of size 64 :
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`% $RV_ROOT/configs/swerv.config -dccm_size=64`
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This will update the **default** snapshot in $RV_ROOT/configs/snapshots/default/ with parameters for a 64K DCCM.
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Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
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This script derives the following consistent set of include files :
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$RV_ROOT/configs/snapshots/default
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├── common_defines.vh # `defines for testbench or design
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├── defines.h # #defines for C/assembly headers
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├── pd_defines.vh # `defines for physical design
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├── perl_configs.pl # Perl %configs hash for scripting
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├── pic_ctrl_verilator_unroll.sv # Unrolled verilog based on PIC size
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├── pic_map_auto.h # PIC memory map based on configure size
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└── whisper.json # JSON file for swerv-iss
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### Building a model
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1. Set the RV_ROOT environment variable to the root of the SweRV directory structure
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`RV_ROOT = /path/to/swerv`
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`export RV_ROOT`
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1. Create your configuration
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*(Skip if default is sufficient)*
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*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the **default** snapshot)*
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`$RV_ROOT/configs/swerv.config [configuration options..] -snapshot=mybuild`
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Snapshots are placed in `$RV_ROOT/configs/snapshots/<snapshot name>/` directory
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1. Build with **verilator**:
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`make -f $RV_ROOT/tools/Makefile verilator [snapshot=name]`
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This will create and populate the verilator *obj_dir/* in the current work dir.
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**Other targets supported**:
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vcs (Synopsys)
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irun (Cadence)
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### Running a simple Hello World program (verilator)
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RV_ROOT = /path/to/swerv
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export RV_ROOT
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make -f $RV_ROOT/tools/Makefile verilator-run
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This will build a verilator model of SweRV with AHB-lite bus, and execute a short sequence of instructions that writes out "HELLO
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WORLD" to the bus.
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You can re-execute using
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./obj_dir/Vtb_top
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Start of sim
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------------------------------
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Hello World from SweRV @WDC !!
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------------------------------
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Finished : minstret = 389, mcycle = 1658
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End of sim
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A vcd file `sim.vcd` is created which can be browsed by gtkwave or similar waveform viewers. `trace_port.csv` contains a log of
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the trace port. `exec.log` contains a basic execution trace showing PC, opcode and GPR writes.
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The Makefile allows you to specify different assembly files from command line
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make -f $RV_ROOT/tools/Makefile verilator-run ASM_TEST=my_hellow_world.s ASM_TEST_DIR=/path/to/dir
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If you change only the assembly files, you do not need to rebuild verilator, just specify the target as `program.hex` :
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make -f $RV_ROOT/tools/Makefile program.hex ASM_TEST=my_hello_world.s ASM_TEST_DIR=/path/to/dir
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./obj_dir/Vtb_top
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### SweRV CoreMark Benchmarking
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We ran [CoreMark](https://www.eembc.org/coremark/) benchmark on Nexys4 board and achieved CoreMark score of **4.94**. Please see the [document](https://github.com/chipsalliance/Cores-SweRV/blob/master/docs/SweRV_CoreMark_Benchmarking.pdf) for details.
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----
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Western Digital, the Western Digital logo, G-Technology, SanDisk, Tegile, Upthere, WD, SweRV Core, SweRV ISS, and OmniXtend are registered trademarks or trademarks of Western Digital Corporation or its affiliates in the US and/or other countries. All other marks are the property of their respective owners.
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