139 lines
5.4 KiB
Markdown
139 lines
5.4 KiB
Markdown
# SweRV RISC-V Core<sup>TM</sup> 1.6 from Western Digital
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## Release Notes
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* Added internal timers support. Please see Chapter 4 of the RISC-V SweRV EH1<sup>TM</sup> Programmers Reference Manual.
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* Fixed an openOCD compliance case with abstract command error codes.
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# SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
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## Release Notes
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This is a bug-fix and performance-improvement release. No new functionality
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is added to the SweRV core.
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##### 1. Bug fixes:
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* Hart incorrectly cleared dmcontrol.dmactive on reset (reported by
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Codasip). *Note that a separate system power-on-reset signal `dbg_rst_l`
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was added to differentiate power-on-reset vs core reset.
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They can be tied together is there is a single reset on chip.*
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* Hart never asserted the dmstatus.allrunning signal on reset which
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caused a timeout in OpenOCD (reported by Codasip).
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* Debug module failed to auto-increment register on system-bus access
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of size 64-bit (reported by Codasip).
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* The core_rst_n signal was incorrectly connected (reported by Codasip).
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* Module/instance renamed for tool compatibility.
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* The program counter was getting corrupted when the load/store unit
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indicated both a single-bit and a double-bit error in the same
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cycle.
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* The MSTATUS register was not being updated as expected when both a
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non-maskable-interrupt and an MSTATUS-write happened in the same
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cycle.
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* Write to SBDATA0 was not starting a system-bus write access when
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sbreadonaddr/sbreadondata is set.
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* Minstret was incorrectly counting ecall/ebreak instructions.
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* The dec_tlu_mpc_halted_only signal was not set for MPC halt after
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reset.
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* The MEPC register was not being updated when a firmware-halt request
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was followed by a timer interrupt.
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* The MINSTRETH control register was being incremented when
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performance counters were disabled.
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* Bus driver contained combinational logic from multiple clock
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domains that sometimes caused a glitch.
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* System bus reads were always being made with 64-bit size for the
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AXI bus which is incorrect for IO access.
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* DCCM single-bit errors were counted for instructions that did not
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commit.
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* ICCM single bit errors were double-counted.
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* Load/store unit was not detecting access faults when DCCM and PIC
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memories are next to each other.
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* Single-bit ECC errors on data load were not always corrected in
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the DCCM.
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* Single-bit ECC errors were not always corrected in the DCCM for DMA
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accesses.
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* Single-bit errors detected while reading ICCM through DMA were not
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being corrected in memory.
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##### 2. Improvements:
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* Improved performance by removing redundant term in decode stall
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logic.
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* Reduced power used by the ICCM memory arrays.
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##### 3. Testbench Improvements:
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* AXI4 and AHB-Lite support.
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* Updated bus memory to be persistent and handle larger programs.
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* Makefile supports ability to run with source or pre-generated hex
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files.
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* Makefile supports targets for CoreMarks benchmark (issue #25).
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* Questa support in Makefile (Issue #19).
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# SweRV RISC-V Core<sup>TM</sup> 1.4 from Western Digital
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## Release Notes
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Move declarations to top of Verilog file to fix fpga compile issues.
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# SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital
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## Release Notes
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1. Make the FPGA optimization code work with the latest version of Verilator.[Pull request #13](https://github.com/chipsalliance/Cores-SweRV/pull/12)
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1. Move JTAG TAP to swerv_wrapper module. [Pull request #10](https://github.com/chipsalliance/Cores-SweRV/pull/10)
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# SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
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## Release Notes
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1. SWERV core RISCV compatibility improvements
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* The ebreak and ecall instructions are no longer counted in the MINSRET
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control and status register.
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* Write to SBDATA0 does not start SB write access when both
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sbreadonaddr/sbreadondata are zero. This fixes issue number
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5 on github.
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1. FPGA support: Add fpga_optimize option to swerv.config which
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eliminates over 90% of clock-gating enabling faster FPGA
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simulation.
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1. Usability: Untabified all the verilog files. This fixes issue number 3 on github.
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# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
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## Release Notes
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1. SWERV core RISCV compatibility improvements
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* Illegal instructions no longer increment minstret
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* Debug single-step command no longer executes multiple instructions
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* For instructions, MTVAL register holds the address that actually
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triggered an access fault
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* DICAD1 debug CSR ECC read size enhancements
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1. SWERV core performance enhancements
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* Improved instruction fetch unit external memory access performance
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* Instruction fetcher no longer stalls due to DMA ICCM requests
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* Improved performance of streaming stores
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* Improved performance of divide instruction
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* Improved I/O Timing
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* Non-idempotent Ld/St changed to non-posted in MFDC
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* DMA QoS Configurable in MFDC
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1. SWERV core miscellaneous changes
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* Non-word access to PIC memory generates access-error
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* Improved streaming performance with unified read/write buffer
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* Non-idempotent load enhancements
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* Debug, single-step, and trigger enhancements
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* DMA, IFU, and LSU interaction enhancements
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* Bus error handling improvements
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* DMA h-ready addition
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* DMA slave error response enhancements
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1. Added memory protection windows
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* Now able to define up to eight instruction fetch windows and up to eight
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data load/store windows. See the programmer reference manual for more
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details.
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