Go to file
colin.liang 5fb3787307 reset from top.v. 2023-01-06 21:19:54 +08:00
Cores-SweRV Reset Readme. 2023-01-04 22:40:08 +08:00
Cores-SweRV-EL2@e8224a4211 Update Cores-EL2 and Quasar. 2022-03-27 09:55:41 +00:00
Flow Delete rvdff by fpga. 2022-05-23 15:37:09 +00:00
Miner420T@21ffe6f37a Add Miner420T submodule 2022-03-22 23:14:02 +00:00
Quasar@5721e092bb Update Cores-EL2 and Quasar. 2022-03-27 09:55:41 +00:00
VexRiscv start to add ecp5 support,current donet support jlink 2022-02-28 03:34:59 +00:00
fpga Refine Readme of install openocd. 2022-02-28 03:33:08 +00:00
jtag add jtag to ESP32 2022-02-02 03:40:41 +00:00
opene906 Refine opene906 gdb sample. 2022-02-25 12:24:03 +00:00
uriscv reset from top.v. 2023-01-06 21:19:54 +08:00
xilinx Update xilinx Readme. 2022-03-11 05:08:19 +00:00
.gitignore Update .gitignore. 2022-03-22 23:24:30 +00:00
.gitmodules Add Miner420T submodule 2022-03-22 23:14:02 +00:00
Readme.md Reset Readme. 2023-01-04 22:40:08 +08:00

Readme.md

Weekend group

helloworld

This a demo for llvm build and sim with verilator.

jtag

This is a demo of jtag simulation by openocd running on verilator.

install verilator

sudo apt install verilator

install openocd

git clone https://github.com/riscv/riscv-openocd.git
cd riscv-openocd
./bootstrap
./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
make
sudo make install

may be install sv2v

https://github.com/zachjs/sv2v

install ninja

sudo apt-get install -y ninja-build

Gen quasar core

git clone https://github.com/Lampro-Mellon/Quasar.git
cd tools
vim configs/quasar.config # to config the core
make clean
make conf
make sbt_
# Quasar/generated_rtl/quasar_wrapper.sv

install Bit-Vector

wget https://cpan.metacpan.org/authors/id/S/ST/STBEY/Bit-Vector-7.4.tar.gz
tar -xvf
cd 
perl Makefile.PL
make 
sudo make install

build and install riscv tools

# build 64bit
sudo make clean
./configure --prefix=/opt/riscv 
sudo make -j12

# build 64bit and 32bit
sudo make clean
./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d --enable-multilib
sudo make -j12
  • Opetion2 :
sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev
git clone https://github.com/chipsalliance/rocket-tools.git
git submodule update --init --recursive
# riscv-isa-sim and openocd may be checkout to main branch to avoid compile error
sudo su
export RISCV=/opt/riscv
export MAKEFLAGS="-j12"
./build-rv32ima.sh

tips

  • jtag的reset引脚要设置正确 jtag_trst_n 低电平复位
  • 仿真的时候jtag的tclk不能太快要低于soc的clk
  • SweRV启动/复位后程序从reset_vec(0x80000000)开始遇到错误code=0就会跳到mtvec(中断向量表)指示的地址
  • 物理仿真的时候 adapter speed 不能太快
  • data段放到0x200太小GDB调试RISCV至少要4K的程序空间
  • soc的ram和rom直接接到了lsu和ifu和DCCM/ICCM无关
  • program.hex 用于 $readmemh 必须以空行结束

Todo

  • gdb怎么复位soc
  • gdb没有把程序加载到memifu还是用老代码
  • mem分bank后怎么加载用于仿真=>for循环分别加载
  • Quasar升级scala版本发现openocd运行不正常