start to add ecp5 support,current donet support jlink

Use FT2232H base jtag,and VexRiscv's openocd to support dbg.

VexRiscv/fpga/.gitignore

@@ -1 +1 @@
-gen
+gen/

VexRiscv/fpga/Colorlight_i5_v6.0-extboard.lpf

@@ -3,36 +3,36 @@ LOCATE COMP "io_mainClk" SITE "P3";
 IOBUF PORT "io_mainClk" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "io_mainClk" 25 MHZ;
 
-LOCATE COMP "io_asyncReset" SITE "N2";
+
+LOCATE COMP "io_asyncReset" SITE "D20";
 IOBUF PORT "io_asyncReset" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "io_asyncReset" 25 MHZ;
 
-LOCATE COMP "rst" SITE "N3";
+LOCATE COMP "rst" SITE "B19";
 IOBUF PORT "rst" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "rst" 25 MHZ;
 
-LOCATE COMP "io_jtag_tck" SITE "T2";
-IOBUF PORT "io_jtag_tck" IO_TYPE=LVCMOS33;
-FREQUENCY PORT "io_jtag_tck" 25 MHZ;
 
-LOCATE COMP "io_jtag_tms" SITE "T3";
-IOBUF PORT "io_jtag_tms" IO_TYPE=LVCMOS33;
-FREQUENCY PORT "io_jtag_tms" 25 MHZ;
 
-LOCATE COMP "io_jtag_tdi" SITE "N4";
+LOCATE COMP "io_jtag_tdi" SITE "E1";
 IOBUF PORT "io_jtag_tdi" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "io_jtag_tdi" 25 MHZ;
 
-LOCATE COMP "jtag_trst_n" SITE "M3";
-IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
-FREQUENCY PORT "jtag_trst_n" 25 MHZ;
-
-LOCATE COMP "io_jtag_tdo" SITE "M4";
+LOCATE COMP "io_jtag_tdo" SITE "E4";
 IOBUF PORT "io_jtag_tdo" IO_TYPE=LVCMOS33;
 
-LOCATE COMP "io_uart_rxd" SITE "P4";
+LOCATE COMP "io_jtag_tck" SITE "F3";
+IOBUF PORT "io_jtag_tck" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_jtag_tck" 25 MHZ;
+
+LOCATE COMP "io_jtag_tms" SITE "H3";
+IOBUF PORT "io_jtag_tms" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_jtag_tms" 25 MHZ;
+
+
+LOCATE COMP "io_uart_rxd" SITE "J5";
 IOBUF PORT "io_uart_rxd" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "io_uart_rxd" 25 MHZ;
 
-LOCATE COMP "io_uart_txd" SITE "N3";
+LOCATE COMP "io_uart_txd" SITE "U16";
 IOBUF PORT "io_uart_txd" IO_TYPE=LVCMOS33;

VexRiscv/fpga/Makefile

@@ -0,0 +1,25 @@
+TARGET=soc
+
+all: clean ${TARGET}.svf
+
+$(TARGET).cfg: 
+	./synth.sh
+
+$(TARGET).bit: $(TARGET).cfg
+	ecppack --svf gen/${TARGET}.svf gen/$< gen/$@
+
+${TARGET}.svf : ${TARGET}.bit
+
+prog: ${TARGET}.svf
+	./dapprog gen/${TARGET}.svf 
+
+clean:
+	rm -rf gen
+
+openocd:
+	openocd -f jlink.cfg -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg
+
+gdb:
+	/opt/riscv/bin/riscv64-unknown-elf-gdb -x gdbinit ./hello_world.elf
+
+.PHONY: prog clean

VexRiscv/fpga/cmsisdap.cfg

@@ -0,0 +1,28 @@
+#
+# Buspirate with OpenOCD support
+#
+# http://dangerousprototypes.com/bus-pirate-manual/
+#
+# http://www.fabienm.eu/flf/15-ecp5-board-kit/
+# https://github.com/Martoni/blp/tree/master/platforms/colorlight
+# https://github.com/HarmonInstruments/JTAG_SWD
+
+interface cmsis-dap
+transport select jtag
+
+adapter_khz 10000
+
+#jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
+
+#LFE5U-25F 0x41111043
+#LFE5U-45F 0x41112043
+jtag newtap ecp5 tap -irlen 8
+
+#init
+#scan_chain
+#
+#svf -tap ecp5.tap -quiet -progress blink.svf
+#exit
+
+# this depends on the cable, you are safe with this option
+#reset_config srst_only

VexRiscv/fpga/cpu0.yaml

@@ -0,0 +1 @@
+debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0}

VexRiscv/fpga/dapprog

@@ -0,0 +1,54 @@
+#!/bin/bash
+
+if [ ${#1} -eq 0 ]; then
+    echo "usage: dapprog xxx.bit or xxx.svf"
+    exit 0
+fi
+
+CURRENT_DIR=$(cd $(dirname $0); pwd)
+CONFIG=${CURRENT_DIR}/cmsisdap.cfg
+
+if [ "$1" == "--probe" ] || [ "$1" == "-p" ]; then
+    #probe add -d4 for detail log
+    sudo openocd -f ${CONFIG} -c \
+    "   init;
+        scan_chain;
+        exit;
+    "
+    exit $?
+
+else
+    # program 
+    IMAGE_FILE=$1
+    
+    EXT="${IMAGE_FILE##*.}"
+    echo EXT: $EXT
+    
+    #flash write_image erase xxx.hex;
+    #flash write_image erase xxx.bin 0x08000000;
+    
+    if [ "${EXT}" == "svf" ]; then
+        TARGET="$IMAGE_FILE"
+    elif [ "${EXT}" == "bit" ]; then
+        NAME="${IMAGE_FILE%%.bit}"
+        #/home/pi/oss/ulx3s/tools/ujprog/ujprog -j SRAM  ${IMAGE_FILE} > ${NAME}_sram.svf
+        ${CURRENT_DIR}/ujprog.bit2svf -j FLASH ${IMAGE_FILE} > ${NAME}_flash.svf
+        TARGET="${NAME}_flash.svf"
+    else
+        echo "illegal suffix [$EXT]"
+        exit 1
+    fi
+    
+    echo "TARGET: ${TARGET}"
+    
+    sudo openocd -f ${CONFIG} -c \
+    "   init;
+        scan_chain;
+        svf -tap ecp5.tap -quiet -progress ${TARGET};
+        exit;
+    "
+    
+    exit $?
+
+fi
+

VexRiscv/fpga/gdbinit

@@ -0,0 +1,4 @@
+target extended-remote :3333
+set remotetimeout 2000
+monitor reset halt
+load

VexRiscv/fpga/jlink.cfg

@@ -0,0 +1,17 @@
+#
+# SEGGER J-Link
+#
+# http://www.segger.com/jlink.html
+#
+
+adapter driver jlink
+adapter speed 500
+
+
+
+# The serial number can be used to select a specific device in case more than
+# one is connected to the host.
+#
+# Example: Select J-Link with serial number 123456789
+#
+# adapter serial 123456789

VexRiscv/fpga/murax.cfg

@@ -0,0 +1,30 @@
+transport select jtag
+
+set  _ENDIAN little
+set _TAP_TYPE 1234
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # set useful default
+   set _CPUTAPID 0x10001fff 
+}
+
+# adapter speed 800
+# adapter srst delay 260
+# jtag_ntrst_delay 250
+
+set _CHIPNAME fpga_spinal
+jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF 
+
+target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge -coreid 0 -dbgbase 0xF00F0000
+vexriscv readWaitCycles 12
+vexriscv cpuConfigFile $MURAX_CPU0_YAML
+
+poll_period 50
+
+init
+#echo "Halting processor"
+soft_reset_halt
+sleep 1000
+

VexRiscv/fpga/synth.sh

@@ -46,4 +46,4 @@ rm -rf gen/*
 
 yosys -v2 -l gen/synth.log gen/synth.ys
 
-nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 100  --json gen/soc.json
+nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg gen/soc.cfg --lpf Colorlight_i5_v6.0-extboard.lpf --freq 100  --json gen/soc.json