431 lines
18 KiB
Systemverilog
431 lines
18 KiB
Systemverilog
//********************************************************************************
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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//********************************************************************************
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// Function: Top level file for Icache, Fetch, Branch prediction & Aligner
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// BFF -> F1 -> F2 -> A
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//********************************************************************************
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module el2_ifu
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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) (
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input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
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input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
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input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
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input logic rst_l, // reset, active low
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input logic dec_i0_decode_d, // Valid instruction at D and not blocked
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input logic exu_flush_final, // flush, includes upper and lower
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input logic dec_tlu_i0_commit_cmt, // committed i0
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input logic dec_tlu_flush_err_wb, // flush due to parity error.
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input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
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input logic [31:1] exu_flush_path_final, // flush fetch address
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input logic [31:0] dec_tlu_mrac_ff, // Side_effect , cacheable for each region
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input logic dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
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input logic dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches
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input logic dec_tlu_bpred_disable, // disable all branch prediction
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input logic dec_tlu_core_ecc_disable, // disable ecc checking and flagging
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input logic dec_tlu_force_halt, // force halt
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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output logic ifu_axi_awvalid,
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output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
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output logic [ 31:0] ifu_axi_awaddr,
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output logic [ 3:0] ifu_axi_awregion,
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output logic [ 7:0] ifu_axi_awlen,
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output logic [ 2:0] ifu_axi_awsize,
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output logic [ 1:0] ifu_axi_awburst,
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output logic ifu_axi_awlock,
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output logic [ 3:0] ifu_axi_awcache,
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output logic [ 2:0] ifu_axi_awprot,
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output logic [ 3:0] ifu_axi_awqos,
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output logic ifu_axi_wvalid,
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output logic [63:0] ifu_axi_wdata,
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output logic [ 7:0] ifu_axi_wstrb,
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output logic ifu_axi_wlast,
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output logic ifu_axi_bready,
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// AXI Read Channels
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output logic ifu_axi_arvalid,
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input logic ifu_axi_arready,
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output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
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output logic [ 31:0] ifu_axi_araddr,
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output logic [ 3:0] ifu_axi_arregion,
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output logic [ 7:0] ifu_axi_arlen,
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output logic [ 2:0] ifu_axi_arsize,
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output logic [ 1:0] ifu_axi_arburst,
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output logic ifu_axi_arlock,
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output logic [ 3:0] ifu_axi_arcache,
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output logic [ 2:0] ifu_axi_arprot,
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output logic [ 3:0] ifu_axi_arqos,
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input logic ifu_axi_rvalid,
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output logic ifu_axi_rready,
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input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
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input logic [ 63:0] ifu_axi_rdata,
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input logic [ 1:0] ifu_axi_rresp,
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input logic ifu_bus_clk_en,
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input logic dma_iccm_req,
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input logic [31:0] dma_mem_addr,
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input logic [ 2:0] dma_mem_sz,
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input logic dma_mem_write,
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input logic [63:0] dma_mem_wdata,
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input logic [ 2:0] dma_mem_tag, // DMA Buffer entry number
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input logic dma_iccm_stall_any,
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output logic iccm_dma_ecc_error,
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output logic iccm_dma_rvalid,
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output logic [63:0] iccm_dma_rdata,
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output logic [ 2:0] iccm_dma_rtag, // Tag of the DMA req
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output logic iccm_ready,
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output logic ifu_pmu_instr_aligned,
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output logic ifu_pmu_fetch_stall,
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output logic ifu_ic_error_start, // has all of the I$ ecc/parity for data/tag
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// I$ & ITAG Ports
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output logic [31:1] ic_rw_addr, // Read/Write addresss to the Icache.
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output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, // Icache write enable, when filling the Icache.
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output logic ic_rd_en, // Icache read enable.
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output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
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input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [25:0] ictag_debug_rd_data, // Debug icache tag.
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output logic [70:0] ic_debug_wr_data, // Debug wr cache.
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output logic [70:0] ifu_ic_debug_rd_data,
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input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, //
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input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
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output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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output logic ic_sel_premux_data, // Select the premux data.
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output logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
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output logic ic_debug_rd_en, // Icache debug rd
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output logic ic_debug_wr_en, // Icache debug wr
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output logic ic_debug_tag_array, // Debug tag array
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output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
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output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid bits when accessing the Icache. One valid bit per way. F2 stage
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input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // Compare hits from Icache tags. Per way. F2 stage
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input logic ic_tag_perr, // Icache Tag parity error
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// ICCM ports
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output logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address.
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output logic iccm_wren, // ICCM write enable (through the DMA)
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output logic iccm_rden, // ICCM read enable.
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output logic [ 77:0] iccm_wr_data, // ICCM write data.
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output logic [ 2:0] iccm_wr_size, // ICCM write location within DW.
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input logic [63:0] iccm_rd_data, // Data read from ICCM.
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input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM.
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output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error.
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// Perf counter sigs
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output logic ifu_pmu_ic_miss, // ic miss
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output logic ifu_pmu_ic_hit, // ic hit
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output logic ifu_pmu_bus_error, // iside bus error
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output logic ifu_pmu_bus_busy, // iside bus busy
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output logic ifu_pmu_bus_trxn, // iside bus transactions
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output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode
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output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
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output logic ifu_i0_valid, // Instruction 0 valid. From Aligner to Decode
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output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst
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output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error
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output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access
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output logic [31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode
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output logic [31:1] ifu_i0_pc, // Instruction 0 pc. From Aligner to Decode
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output logic ifu_i0_pc4, // Instruction 0 is 4 byte. From Aligner to Decode
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output logic ifu_miss_state_idle, // There is no outstanding miss. Cache miss state is idle.
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output el2_br_pkt_t i0_brp, // Instruction 0 branch packet. From Aligner to Decode
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output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
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output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
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output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
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output logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
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input el2_predict_pkt_t exu_mp_pkt, // mispredict packet
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input logic [ pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
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input logic [ pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
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input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index
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input logic [ pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
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input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
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input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
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input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
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input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
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input dec_tlu_flush_lower_wb,
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output logic [15:0] ifu_i0_cinst,
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/// Icache debug
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input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt,
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output logic ifu_ic_debug_rd_data_valid,
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output logic iccm_buf_correct_ecc,
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output logic iccm_correction_state,
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input logic scan_mode
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);
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localparam TAGWIDTH = 2;
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localparam IDWIDTH = 2;
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logic ifu_fb_consume1, ifu_fb_consume2;
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logic [31:1] ifc_fetch_addr_f;
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logic [31:1] ifc_fetch_addr_bf;
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logic [ 1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
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logic [31:1] ifu_fetch_pc; // starting pc of fetch
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logic iccm_rd_ecc_single_err, ic_error_start;
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assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;
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assign ifu_ic_error_start = ic_error_start;
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logic ic_write_stall;
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logic ic_dma_active;
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logic ifc_dma_access_ok;
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logic [1:0] ic_access_fault_f;
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logic [1:0] ic_access_fault_type_f;
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logic ifu_ic_mb_empty;
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logic ic_hit_f;
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logic [1:0] ifu_bp_way_f; // way indication; right justified
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logic ifu_bp_hit_taken_f; // kill next fetch; taken target found
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logic [31:1] ifu_bp_btb_target_f; // predicted target PC
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logic ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
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logic [1:0] ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
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logic [1:0] ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
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logic [11:0] ifu_bp_poffset_f; // predicted target
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logic [1:0] ifu_bp_ret_f; // predicted ret ; right justified
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logic [1:0] ifu_bp_pc4_f; // pc4 indication; right justified
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logic [1:0] ifu_bp_valid_f; // branch valid, right justified
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logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
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logic [1:0][$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
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// fetch control
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el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*);
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// branch predictor
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if (pt.BTB_ENABLE == 1) begin : bpred
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el2_ifu_bp_ctl #(.pt(pt)) bp (.*);
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end else begin : bpred
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assign ifu_bp_hit_taken_f = '0;
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// verif wires
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logic btb_wr_en_way0, btb_wr_en_way1, dec_tlu_error_wb;
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logic [16+pt.BTB_BTAG_SIZE:0] btb_wr_data;
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assign btb_wr_en_way0 = '0;
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assign btb_wr_en_way1 = '0;
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assign btb_wr_data = '0;
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assign dec_tlu_error_wb = '0;
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assign ifu_bp_inst_mask_f = 1'b1;
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end
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logic [1:0] ic_fetch_val_f;
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logic [31:0] ic_data_f;
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logic [31:0] ifu_fetch_data_f;
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logic ifc_fetch_req_f;
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logic ifc_fetch_req_f_raw;
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logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error.
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logic ifu_async_error_start;
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assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];
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assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];
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assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
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logic ifc_fetch_uncacheable_bf; // The fetch request is uncacheable space. BF stage
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logic ifc_fetch_req_bf; // Fetch request. Comes with the address. BF stage
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logic ifc_fetch_req_bf_raw; // Fetch request without some qualifications. Used for clock-gating. BF stage
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logic ifc_iccm_access_bf; // This request is to the ICCM. Do not generate misses to the bus.
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logic ifc_region_acc_fault_bf; // Access fault. in ICCM region but offset is outside defined ICCM.
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// aligner
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el2_ifu_aln_ctl #(.pt(pt)) aln (.*);
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// icache
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el2_ifu_mem_ctl #(
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.pt(pt)
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) mem_ctl (
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.*,
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.ic_data_f(ic_data_f[31:0])
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);
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// Performance debug info
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//
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//
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`ifdef DUMP_BTB_ON
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logic exu_mp_valid; // conditional branch mispredict
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logic exu_mp_way; // conditional branch mispredict
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logic exu_mp_ataken; // direction is actual taken
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logic exu_mp_boffset; // branch offsett
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logic exu_mp_pc4; // branch is a 4B inst
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logic exu_mp_call; // branch is a call inst
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logic exu_mp_ret; // branch is a ret inst
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logic exu_mp_ja; // branch is a jump always
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logic [ 1:0] exu_mp_hist; // new history
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logic [ 11:0] exu_mp_tgt; // target offset
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logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
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assign exu_mp_valid = exu_mp_pkt.misp; // conditional branch mispredict
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assign exu_mp_ataken = exu_mp_pkt.ataken; // direction is actual taken
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assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset
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assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst
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assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst
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assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst
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assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always
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assign exu_mp_way = exu_mp_pkt.way; // branch is a jump always
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assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history
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assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0]; // target offset
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assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address
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logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_f;
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`define DEC top.rvtop.swerv.dec
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`define EXU top.rvtop.swerv.exu
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el2_btb_addr_hash f2hash (
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.pc (ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),
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.hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])
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);
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logic [31:0] mppc_ns, mppc;
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logic exu_flush_final_d1;
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assign mppc_ns[31:1] = `EXU.i0_flush_upper_x ? `EXU.exu_i0_pc_x : `EXU.dec_i0_pc_d;
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assign mppc_ns[0] = 1'b0;
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rvdff #(33) junk_ff (
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.*,
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.clk (active_clk),
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.din ({mppc_ns[31:0], exu_flush_final}),
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.dout({mppc[31:0], exu_flush_final_d1})
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);
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logic tmp_bnk;
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assign tmp_bnk = bpred.bp.btb_sel_f[1];
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always @(negedge clk) begin
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if (`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
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$display("BTB_CONFIG: %d", pt.BTB_SIZE);
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`ifndef BP_NOGSHARE
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$display("BHT_CONFIG: %d gshare: 1", pt.BHT_SIZE);
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`else
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$display("BHT_CONFIG: %d gshare: 0", pt.BHT_SIZE);
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`endif
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$display("RS_CONFIG: %d", pt.RET_STACK_SIZE);
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end
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if(exu_flush_final_d1 & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))
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$display(
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"%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h",
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`DEC.tlu.mcyclel[31:0] + 32'ha,
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exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
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1'b0,
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exu_mp_call,
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exu_mp_ret,
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exu_mp_ataken,
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exu_mp_hist[1:0],
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exu_mp_valid,
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exu_mp_btag[pt.BTB_BTAG_SIZE-1:0],
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{
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exu_flush_path_final[31:1], 1'b0
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},
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exu_mp_eghr[pt.BHT_GHR_SIZE-1:0],
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exu_mp_valid,
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bpred.bp.bht_wr_addr0,
|
|
mppc[31:0],
|
|
exu_mp_pkt.way
|
|
);
|
|
|
|
for (int i = 0; i < 8; i++) begin
|
|
if (ifu_bp_valid_f[i] & ifc_fetch_req_f)
|
|
$display(
|
|
"%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %0h ghr: %4b ghr_index: %h way: %h",
|
|
`DEC.tlu.mcyclel[31:0] + 32'ha,
|
|
btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
|
|
bpred.bp.btb_sel_f[1],
|
|
bpred.bp.btb_rd_call_f,
|
|
bpred.bp.btb_rd_ret_f,
|
|
ifu_bp_hist1_f[tmp_bnk],
|
|
ifu_bp_hist0_f[tmp_bnk],
|
|
bpred.bp.fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0],
|
|
{
|
|
ifu_bp_btb_target_f[31:1], 1'b0
|
|
},
|
|
bpred.bp.fghr[pt.BHT_GHR_SIZE-1:0],
|
|
bpred.bp.bht_rd_addr_f,
|
|
ifu_bp_way_f[tmp_bnk]
|
|
);
|
|
end
|
|
if (dec_tlu_br0_r_pkt.valid & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error))
|
|
$display(
|
|
"%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h",
|
|
`DEC.tlu.mcyclel[31:0] + 32'ha,
|
|
bpred.bp.br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO],
|
|
{
|
|
dec_tlu_br0_r_pkt.middle
|
|
},
|
|
dec_tlu_br0_r_pkt.hist,
|
|
dec_tlu_br0_r_pkt.way
|
|
);
|
|
|
|
if (dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error)
|
|
$display(
|
|
"%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h",
|
|
`DEC.tlu.mcyclel[31:0] + 32'ha,
|
|
exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
|
|
1'b0,
|
|
dec_tlu_br0_r_pkt.br_start_error,
|
|
{
|
|
exu_flush_path_final[31:1], 1'b0
|
|
},
|
|
dec_tlu_br0_r_pkt.way
|
|
);
|
|
end // always @ (negedge clk)
|
|
function [1:0] encode4_2;
|
|
input [3:0] in;
|
|
|
|
encode4_2[1] = in[3] | in[2];
|
|
encode4_2[0] = in[3] | in[1];
|
|
|
|
endfunction
|
|
`endif
|
|
endmodule // el2_ifu
|