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abstractaccelerator/testbench/hex
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Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 		2019-08-07 17:04:48 -07:00
..
data.hex Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00
program.hex Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 2019-08-07 17:04:48 -07:00