58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
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`timescale 1ns/1ps
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module soc (
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input wire io_asyncReset,
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input wire io_mainClk,
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input wire [31:0] io_gpioA_read,
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output wire [31:0] io_gpioA_write,
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output wire [31:0] io_gpioA_writeEnable,
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output wire io_uart_txd,
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input wire io_uart_rxd
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);
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_tdo;
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bit [31:0] cycleCnt;
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always @(posedge io_mainClk) begin
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cycleCnt <= cycleCnt + 1;
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end
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wire clk;
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assign clk = cycleCnt[2];
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logic rst_l;
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assign rst_l = cycleCnt > 100;
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Murax murax(
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.io_asyncReset(io_asyncReset),
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.io_mainClk(io_mainClk),
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.io_jtag_tms(jtag_tms),
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.io_jtag_tdi(jtag_tdi),
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.io_jtag_tdo(jtag_tdo),
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.io_jtag_tck(jtag_tck),
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.io_gpioA_read(io_gpioA_read),
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.io_gpioA_write(io_gpioA_write),
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.io_gpioA_writeEnable(io_gpioA_writeEnable),
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.io_uart_txd(io_uart_txd),
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.io_uart_rxd(io_uart_rxd)
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);
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jtagdpi jtagdpi (
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.clk_i (io_mainClk),
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.rst_ni(rst_l),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo(jtag_tdo),
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.jtag_trst_n(),
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.jtag_srst_n()
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);
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endmodule |