444 lines
15 KiB
Systemverilog
444 lines
15 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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`ifdef VERILATOR
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module soc_top ( input bit core_clk);
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`else
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module soc_top;
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bit core_clk;
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`endif
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logic rst_l;
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logic porst_l;
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logic nmi_int;
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logic [31:0] reset_vector;
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logic [31:0] nmi_vector;
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logic [31:1] jtag_id;
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logic [31:0] ic_haddr;
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logic [2:0] ic_hburst;
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logic ic_hmastlock;
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logic [3:0] ic_hprot;
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logic [2:0] ic_hsize;
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logic [1:0] ic_htrans;
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logic ic_hwrite;
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logic [63:0] ic_hrdata;
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logic ic_hready;
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logic ic_hresp;
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logic [31:0] lsu_haddr;
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logic [2:0] lsu_hburst;
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logic lsu_hmastlock;
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logic [3:0] lsu_hprot;
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logic [2:0] lsu_hsize;
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logic [1:0] lsu_htrans;
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logic lsu_hwrite;
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logic [63:0] lsu_hrdata;
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logic [63:0] lsu_hwdata;
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logic lsu_hready;
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logic lsu_hresp;
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logic [31:0] sb_haddr;
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logic [2:0] sb_hburst;
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logic sb_hmastlock;
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logic [3:0] sb_hprot;
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logic [2:0] sb_hsize;
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logic [1:0] sb_htrans;
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logic sb_hwrite;
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logic [63:0] sb_hrdata;
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logic [63:0] sb_hwdata;
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logic sb_hready;
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logic sb_hresp;
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logic [63:0] trace_rv_i_insn_ip;
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logic [63:0] trace_rv_i_address_ip;
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logic [2:0] trace_rv_i_valid_ip;
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logic [2:0] trace_rv_i_exception_ip;
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logic [4:0] trace_rv_i_ecause_ip;
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logic [2:0] trace_rv_i_interrupt_ip;
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logic [31:0] trace_rv_i_tval_ip;
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logic o_debug_mode_status;
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logic [1:0] dec_tlu_perfcnt0;
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logic [1:0] dec_tlu_perfcnt1;
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logic [1:0] dec_tlu_perfcnt2;
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logic [1:0] dec_tlu_perfcnt3;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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logic o_cpu_run_ack;
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logic mailbox_write;
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logic [63:0] dma_hrdata;
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logic [63:0] dma_hwdata;
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logic dma_hready;
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logic dma_hresp;
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logic mpc_debug_halt_req;
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logic mpc_debug_run_req;
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logic mpc_reset_run_req;
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logic mpc_debug_halt_ack;
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logic mpc_debug_run_ack;
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logic debug_brkpt_status;
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bit [31:0] cycleCnt;
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logic mailbox_data_val;
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wire dma_hready_out;
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int commit_count;
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logic wb_valid[1:0];
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logic [4:0] wb_dest[1:0];
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logic [31:0] wb_data[1:0];
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wire[63:0] WriteData;
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string abi_reg[32]; // ABI register names
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`define DEC rvtop.swerv.dec
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assign mailbox_write = lmem.mailbox_write;
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assign WriteData = lmem.WriteData;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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parameter MAX_CYCLES = 10_000_000_0;
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integer fd, tp, el;
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always @(negedge core_clk) begin
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cycleCnt <= cycleCnt+1;
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// Test timeout monitor
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if(cycleCnt == MAX_CYCLES) begin
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$display ("Hit max cycle count (%0d) .. stopping",cycleCnt);
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$finish;
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end
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// cansol Monitor
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if( mailbox_data_val & mailbox_write) begin
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$fwrite(fd,"%c", WriteData[7:0]);
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$write("%c", WriteData[7:0]);
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end
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// End Of test monitor
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if(mailbox_write && WriteData[7:0] == 8'hff) begin
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$display("\nFinished : minstret = %0d, mcycle = %0d", `DEC.tlu.minstretl[31:0],`DEC.tlu.mcyclel[31:0]);
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$display("See \"exec.log\" for execution trace with register updates..\n");
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$display("TEST_PASSED");
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$finish;
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end
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else if(mailbox_write && WriteData[7:0] == 8'h1) begin
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$display("TEST_FAILED");
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$finish;
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end
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end
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// trace monitor
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always @(posedge core_clk) begin
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wb_valid[1:0] <= '{`DEC.dec_i1_wen_wb, `DEC.dec_i0_wen_wb};
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wb_dest[1:0] <= '{`DEC.dec_i1_waddr_wb, `DEC.dec_i0_waddr_wb};
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wb_data[1:0] <= '{`DEC.dec_i1_wdata_wb, `DEC.dec_i0_wdata_wb};
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if (trace_rv_i_valid_ip !== 0) begin
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$fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", trace_rv_i_valid_ip, trace_rv_i_address_ip[63:32], trace_rv_i_address_ip[31:0],
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trace_rv_i_insn_ip[63:32], trace_rv_i_insn_ip[31:0],trace_rv_i_exception_ip,trace_rv_i_ecause_ip,
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trace_rv_i_tval_ip,trace_rv_i_interrupt_ip);
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// Basic trace - no exception register updates
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// #1 0 ee000000 b0201073 c 0b02 00000000
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for (int i=0; i<2; i++)
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if (trace_rv_i_valid_ip[i]==1) begin
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commit_count++;
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$fwrite (el, "%10d : %8s %0d %h %h%13s ; %s\n",cycleCnt, $sformatf("#%0d",commit_count), 0,
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trace_rv_i_address_ip[31+i*32 -:32], trace_rv_i_insn_ip[31+i*32-:32],
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(wb_dest[i] !=0 && wb_valid[i]) ? $sformatf("%s=%h", abi_reg[wb_dest[i]], wb_data[i]) : " ",
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dasm(trace_rv_i_insn_ip[31+i*32 -:32], trace_rv_i_address_ip[31+i*32-:32], wb_dest[i] & {5{wb_valid[i]}}, wb_data[i])
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);
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end
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end
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if(`DEC.dec_nonblock_load_wen) begin
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$fwrite (el, "%10d : %10d%22s=%h ; nbL\n", cycleCnt, 0, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
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soc_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
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end
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end
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initial begin
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abi_reg[0] = "zero";
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abi_reg[1] = "ra";
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abi_reg[2] = "sp";
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abi_reg[3] = "gp";
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abi_reg[4] = "tp";
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abi_reg[5] = "t0";
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abi_reg[6] = "t1";
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abi_reg[7] = "t2";
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abi_reg[8] = "s0";
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abi_reg[9] = "s1";
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abi_reg[10] = "a0";
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abi_reg[11] = "a1";
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abi_reg[12] = "a2";
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abi_reg[13] = "a3";
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abi_reg[14] = "a4";
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abi_reg[15] = "a5";
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abi_reg[16] = "a6";
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abi_reg[17] = "a7";
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abi_reg[18] = "s2";
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abi_reg[19] = "s3";
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abi_reg[20] = "s4";
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abi_reg[21] = "s5";
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abi_reg[22] = "s6";
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abi_reg[23] = "s7";
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abi_reg[24] = "s8";
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abi_reg[25] = "s9";
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abi_reg[26] = "s10";
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abi_reg[27] = "s11";
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abi_reg[28] = "t3";
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abi_reg[29] = "t4";
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abi_reg[30] = "t5";
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abi_reg[31] = "t6";
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// tie offs
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jtag_id[31:28] = 4'b1;
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jtag_id[27:12] = '0;
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jtag_id[11:1] = 11'h45;
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reset_vector = 32'h0;
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nmi_vector = 32'hee000000;
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nmi_int = 0;
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$readmemh("program.hex", lmem.mem);
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$readmemh("program.hex", imem.mem);
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tp = $fopen("trace_port.csv","w");
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el = $fopen("exec.log","w");
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$fwrite (el, "// Cycle : #inst hart pc opcode reg=value ; mnemonic\n");
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$fwrite (el, "//---------------------------------------------------------------\n");
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fd = $fopen("console.log","w");
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commit_count = 0;
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`ifndef VERILATOR
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if($test$plusargs("dumpon")) $dumpvars;
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forever core_clk = #5 ~core_clk;
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`endif
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end
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assign rst_l = cycleCnt > 5;
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assign porst_l = cycleCnt >2;
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//=========================================================================-
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// RTL instance
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//=========================================================================-
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jtagdpi jtagdpi(
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.clk_i(core_clk),
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.rst_ni(rst_l),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo(jtag_tdo),
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.jtag_trst_n(jtag_trst_n),
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.jtag_srst_n()
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);
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swerv_wrapper rvtop (
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.rst_l ( rst_l ),
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.dbg_rst_l ( porst_l ),
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.clk ( core_clk ),
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.rst_vec ( reset_vector[31:1]),
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.nmi_int ( nmi_int ),
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.nmi_vec ( nmi_vector[31:1]),
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.jtag_id ( jtag_id[31:1]),
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`ifdef RV_BUILD_AHB_LITE
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.haddr ( ic_haddr ),
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.hburst ( ic_hburst ),
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.hmastlock ( ic_hmastlock ),
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.hprot ( ic_hprot ),
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.hsize ( ic_hsize ),
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.htrans ( ic_htrans ),
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.hwrite ( ic_hwrite ),
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.hrdata ( ic_hrdata[63:0]),
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.hready ( ic_hready ),
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.hresp ( ic_hresp ),
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//---------------------------------------------------------------
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// Debug AHB Master
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//---------------------------------------------------------------
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.sb_haddr ( sb_haddr ),
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.sb_hburst ( sb_hburst ),
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.sb_hmastlock ( sb_hmastlock ),
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.sb_hprot ( sb_hprot ),
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.sb_hsize ( sb_hsize ),
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.sb_htrans ( sb_htrans ),
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.sb_hwrite ( sb_hwrite ),
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.sb_hwdata ( sb_hwdata ),
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.sb_hrdata ( sb_hrdata ),
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.sb_hready ( sb_hready ),
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.sb_hresp ( sb_hresp ),
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//---------------------------------------------------------------
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// LSU AHB Master
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//---------------------------------------------------------------
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.lsu_haddr ( lsu_haddr ),
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.lsu_hburst ( lsu_hburst ),
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.lsu_hmastlock ( lsu_hmastlock ),
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.lsu_hprot ( lsu_hprot ),
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.lsu_hsize ( lsu_hsize ),
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.lsu_htrans ( lsu_htrans ),
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.lsu_hwrite ( lsu_hwrite ),
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.lsu_hwdata ( lsu_hwdata ),
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.lsu_hrdata ( lsu_hrdata[63:0]),
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.lsu_hready ( lsu_hready ),
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.lsu_hresp ( lsu_hresp ),
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//---------------------------------------------------------------
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// DMA Slave
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//---------------------------------------------------------------
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.dma_haddr ( '0 ),
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.dma_hburst ( '0 ),
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.dma_hmastlock ( '0 ),
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.dma_hprot ( '0 ),
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.dma_hsize ( '0 ),
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.dma_htrans ( '0 ),
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.dma_hwrite ( '0 ),
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.dma_hwdata ( '0 ),
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.dma_hrdata ( dma_hrdata ),
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.dma_hresp ( dma_hresp ),
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.dma_hsel ( 1'b1 ),
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.dma_hreadyin ( dma_hready_out ),
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.dma_hreadyout ( dma_hready_out ),
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`endif
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.timer_int ( 1'b0 ),
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.extintsrc_req ( '0 ),
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.lsu_bus_clk_en ( 1'b1 ),
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.ifu_bus_clk_en ( 1'b1 ),
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.dbg_bus_clk_en ( 1'b1 ),
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.dma_bus_clk_en ( 1'b1 ),
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.trace_rv_i_insn_ip (trace_rv_i_insn_ip),
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.trace_rv_i_address_ip (trace_rv_i_address_ip),
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.trace_rv_i_valid_ip (trace_rv_i_valid_ip),
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.trace_rv_i_exception_ip(trace_rv_i_exception_ip),
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.trace_rv_i_ecause_ip (trace_rv_i_ecause_ip),
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.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
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.trace_rv_i_tval_ip (trace_rv_i_tval_ip),
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.jtag_tck ( jtag_tck ),
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.jtag_tms ( jtag_tms ),
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.jtag_tdi ( jtag_tdi ),
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.jtag_trst_n ( jtag_trst_n ),
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.jtag_tdo ( jtag_tdo ),
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.mpc_debug_halt_ack ( mpc_debug_halt_ack),
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.mpc_debug_halt_req ( 1'b0),
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.mpc_debug_run_ack ( mpc_debug_run_ack),
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.mpc_debug_run_req ( 1'b1),
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.mpc_reset_run_req ( 1'b1),
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.debug_brkpt_status (debug_brkpt_status),
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.i_cpu_halt_req ( 1'b0 ),
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.o_cpu_halt_ack ( o_cpu_halt_ack ),
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.o_cpu_halt_status ( o_cpu_halt_status ),
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.i_cpu_run_req ( 1'b0 ),
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.o_debug_mode_status (o_debug_mode_status),
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.o_cpu_run_ack ( o_cpu_run_ack ),
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.dec_tlu_perfcnt0 (dec_tlu_perfcnt0),
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.dec_tlu_perfcnt1 (dec_tlu_perfcnt1),
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.dec_tlu_perfcnt2 (dec_tlu_perfcnt2),
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.dec_tlu_perfcnt3 (dec_tlu_perfcnt3),
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.scan_mode ( 1'b0 ),
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.mbist_mode ( 1'b0 )
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);
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//=========================================================================-
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// AHB I$ instance
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//=========================================================================-
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`ifdef RV_BUILD_AHB_LITE
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ahb_sif imem (
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// Inputs
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.HWDATA(64'h0),
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.HCLK(core_clk),
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.HSEL(1'b1),
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.HPROT(ic_hprot),
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.HWRITE(ic_hwrite),
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.HTRANS(ic_htrans),
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.HSIZE(ic_hsize),
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.HREADY(ic_hready),
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.HRESETn(rst_l),
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.HADDR(ic_haddr),
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.HBURST(ic_hburst),
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// Outputs
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.HREADYOUT(ic_hready),
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.HRESP(ic_hresp),
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.HRDATA(ic_hrdata[63:0])
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);
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ahb_sif lmem (
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// Inputs
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.HWDATA(lsu_hwdata),
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.HCLK(core_clk),
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.HSEL(1'b1),
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.HPROT(lsu_hprot),
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.HWRITE(lsu_hwrite),
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.HTRANS(lsu_htrans),
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.HSIZE(lsu_hsize),
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.HREADY(lsu_hready),
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.HRESETn(rst_l),
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.HADDR(lsu_haddr),
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.HBURST(lsu_hburst),
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// Outputs
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.HREADYOUT(lsu_hready),
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.HRESP(lsu_hresp),
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.HRDATA(lsu_hrdata[63:0])
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);
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`endif
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`define DRAM(bank) \
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rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
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`define ICCM_PATH `RV_TOP.mem.iccm
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`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
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`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
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`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
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`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
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/* verilator lint_off WIDTH */
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/* verilator lint_off CASEINCOMPLETE */
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`include "dasm.svi"
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/* verilator lint_on CASEINCOMPLETE */
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/* verilator lint_on WIDTH */
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endmodule
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