32 lines
688 B
Makefile
32 lines
688 B
Makefile
TARGET=top
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OBJS+=top.sv
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OBJS+=bram.sv
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all: ${TARGET}.bit
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$(TARGET).json: $(OBJS)
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yosys -p "read_verilog -sv $(OBJS); synth_ecp5 -top ${TARGET} -json $@"
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$(TARGET).config: $(TARGET).json
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nextpnr-ecp5 --25k --package CABGA381 --speed 6 --json $< --textcfg $@ --lpf $(TARGET).lpf --freq 65
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$(TARGET).bit: $(TARGET).config
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ecppack --svf ${TARGET}.svf $< $@
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${TARGET}.svf : ${TARGET}.bit
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prog: ${TARGET}.svf
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# openFPGALoader -c digilent_hs2 $(TARGET).bit
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./dapprog ${TARGET}.svf
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clean:
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rm -rf *.svf *.bit *.config *.ys *.json obj_dir logs
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verilator:
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rm -rf obj_dir logs
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verilator -Wall --cc --exe --build --trace sim_main.cpp $(OBJS)
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obj_dir/Vtop +trace
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.PHONY: prog clean
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