abstractaccelerator/Cores-SweRV/demo/fpga/Readmd.md

237 B

jtag simulation

start openocd

openocd -d -f swerv.cfg

start gdb

/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"

quick start

At demo/jtag/

  1. make all
  2. make openocd
  3. make gdb