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170 Commits 1 Branch 0 Tags 68 MiB
Verilog 56.8%
SystemVerilog 30.2%
Perl 5.4%
C 5.1%
Assembly 1.1%
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colin e513374a7e Add submodule of sweRV EL2. 2022-03-09 11:17:07 +00:00
Cores-SweRV add quasar fpga. 2022-03-09 11:16:13 +00:00
Cores-SweRV-EL2@9950499ac5 Add submodule of sweRV EL2. 2022-03-09 11:17:07 +00:00
VexRiscv start to add ecp5 support,current donet support jlink 2022-02-28 03:34:59 +00:00
fpga Refine Readme of install openocd. 2022-02-28 03:33:08 +00:00
jtag add jtag to ESP32 2022-02-02 03:40:41 +00:00
opene906 Refine opene906 gdb sample. 2022-02-25 12:24:03 +00:00
xilinx Add xilinx readme. 2022-02-21 07:53:02 +00:00
.gitignore Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00
.gitmodules Add submodule of sweRV EL2. 2022-03-09 11:17:07 +00:00
Readme.md Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00

Readme.md

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