0dacc978da
not start an SB write access when sbreadonaddr/dbreadondata is set. Add fpga_optimize option to swerv.config; eliminates over 90% of clock-gating to support faster FPGA simulation. |
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|---|---|---|
| .. | ||
| dmi_jtag_to_core_sync.v | ||
| dmi_wrapper.v | ||
| rvjtag_tap.sv | ||