cores-swerv-el2/swerv_el2.core

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CAPI=2:
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name : chipsalliance.org:cores:SweRV_EL2:1.2
filesets:
rtl:
files:
- design/include/el2_def.sv
- design/lib/el2_lib.sv
- design/lib/beh_lib.sv
- design/el2_mem.sv
- design/el2_pic_ctrl.sv
- design/el2_dma_ctrl.sv
- design/ifu/el2_ifu_aln_ctl.sv
- design/ifu/el2_ifu_compress_ctl.sv
- design/ifu/el2_ifu_ifc_ctl.sv
- design/ifu/el2_ifu_bp_ctl.sv
- design/ifu/el2_ifu_ic_mem.sv
- design/ifu/el2_ifu_mem_ctl.sv
- design/ifu/el2_ifu_iccm_mem.sv
- design/ifu/el2_ifu.sv
- design/dec/el2_dec_decode_ctl.sv
- design/dec/el2_dec_gpr_ctl.sv
- design/dec/el2_dec_ib_ctl.sv
- design/dec/el2_dec_tlu_ctl.sv
- design/dec/el2_dec_trigger.sv
- design/dec/el2_dec.sv
- design/exu/el2_exu_alu_ctl.sv
- design/exu/el2_exu_mul_ctl.sv
- design/exu/el2_exu_div_ctl.sv
- design/exu/el2_exu.sv
- design/lsu/el2_lsu.sv
- design/lsu/el2_lsu_bus_buffer.sv
- design/lsu/el2_lsu_clkdomain.sv
- design/lsu/el2_lsu_addrcheck.sv
- design/lsu/el2_lsu_lsc_ctl.sv
- design/lsu/el2_lsu_stbuf.sv
- design/lsu/el2_lsu_bus_intf.sv
- design/lsu/el2_lsu_ecc.sv
- design/lsu/el2_lsu_dccm_mem.sv
- design/lsu/el2_lsu_dccm_ctl.sv
- design/lsu/el2_lsu_trigger.sv
- design/dbg/el2_dbg.sv
- design/dmi/dmi_wrapper.v
- design/dmi/dmi_jtag_to_core_sync.v
- design/dmi/rvjtag_tap.v
- design/lib/mem_lib.sv
- design/el2_swerv.sv
- design/el2_swerv_wrapper.sv
file_type : systemVerilogSource
vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]}
targets:
default:
filesets :
- rtl
- "tool_vivado ? (vivado_tcl)"
lint:
default_tool: verilator
filesets : [rtl]
generate : [swerv_default_config]
tools:
verilator :
mode : lint-only
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toplevel : el2_swerv_wrapper
synth:
default_tool : vivado
filesets : [rtl, vivado_tcl]
generate : [swerv_default_config]
parameters : [RV_FPGA_OPTIMIZE]
tools:
vivado:
part : xc7a100tcsg324-1
pnr : none
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toplevel : el2_swerv_wrapper
generate:
swerv_default_config:
generator: swerv_el2_config
position : first
parameters:
args : [-unset=assert_on]
generators:
swerv_el2_config:
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interpreter: python3
command: configs/swerv_config_gen.py
description : Create a SweRV EL2 configuration. Note! Only supports the default config
parameters:
RV_FPGA_OPTIMIZE:
datatype : bool
default : true
description : Minimize clock gating to map better to FPGAs
paramtype : vlogdefine