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Fix non-blocking assignment in mem_lib.sv 

A typo in mem_lib.sv caused suboptimal mapping which led to high
resource usage on FPGA targets.
This commit is contained in:
Olof Kindgren 2020-09-24 16:16:03 +02:00
parent 4c5674ca35
commit 025a720e35
1 changed files with 1 additions and 1 deletions
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2
design/lib/mem_lib.sv
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@ -28,7 +28,7 @@ module ram_``depth``x``width( \
reg [(width-1):0] ram_core [(depth-1):0]; \ reg [(width-1):0] ram_core [(depth-1):0]; \
\ \
always @(posedge CLK) begin \ always @(posedge CLK) begin \
if (ME && WE) ram_core[ADR] = D; \ if (ME && WE) ram_core[ADR] <= D; \
if (ME && ~WE) Q <= ram_core[ADR]; \ if (ME && ~WE) Q <= ram_core[ADR]; \
end \ end \
\ \