Fix non-blocking assignment in mem_lib.sv

A typo in mem_lib.sv caused suboptimal mapping which led to high resource usage on FPGA targets.
2020-09-24 16:16:03 +02:00 · 2020-09-24 16:16:03 +02:00 · 025a720e35
parent 4c5674ca35
commit 025a720e35
1 changed files with 1 additions and 1 deletions
--- a/design/lib/mem_lib.sv
+++ b/design/lib/mem_lib.sv
@ -28,7 +28,7 @@ module ram_``depth``x``width(               \
 reg [(width-1):0] ram_core [(depth-1):0];   \
                                            \
 always @(posedge CLK) begin              \
-   if (ME && WE) ram_core[ADR] = D;        \
+   if (ME && WE) ram_core[ADR] <= D;        \
   if (ME && ~WE) Q <= ram_core[ADR];       \
 end                                         \
                                            \