Splite ram and rom to bank=8.
This commit is contained in:
colin
parent
dc1509b921
commit
94c3d5f8ad
188
soc/ahb_sif.sv
188
soc/ahb_sif.sv
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@ -53,58 +53,186 @@ module axi_slv #(
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output reg [TAGW-1:0] bid
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);
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15
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parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15
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bit [7:0] mem[(1<<MEM_DEPTH)-1:0];
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bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
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bit [63:0] memdata;
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wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];
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wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH-1:0];
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wire [MEM_DEPTH-4:0] saraddr0 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h0 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr1 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h1 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr2 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h2 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr3 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h3 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr4 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h4 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr5 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h5 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr6 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h6 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr7 = araddr[MEM_DEPTH - 1:3];
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wire [7:0] rm0 = mem0[saraddr0];
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wire [7:0] rm1 = mem1[saraddr1];
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wire [7:0] rm2 = mem2[saraddr2];
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wire [7:0] rm3 = mem3[saraddr3];
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wire [7:0] rm4 = mem4[saraddr4];
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wire [7:0] rm5 = mem5[saraddr5];
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wire [7:0] rm6 = mem6[saraddr6];
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wire [7:0] rm7 = mem7[saraddr7];
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wire [MEM_DEPTH-4:0] sawaddr0 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 0 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr1 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 1 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr2 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 2 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr3 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 3 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr4 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 4 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr5 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 5 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr6 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 6 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr7 = awaddr[MEM_DEPTH - 1:3];
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initial begin
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mem0[0] = 8'h63;
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mem1[0] = 8'h0;
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mem2[0] = 8'h0;
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mem3[0] = 8'h0;
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end
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always @(posedge aclk or negedge rst_l) begin
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if (!rst_l) begin
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rvalid <= 0;
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bvalid <= 0;
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end else begin
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bid <= awid;
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rid <= arid;
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bid <= awid;
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rid <= arid;
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rvalid <= arvalid;
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bvalid <= awvalid;
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rdata <= memdata;
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rdata <= memdata;
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end
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end
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always @(negedge aclk) begin
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if (arvalid)
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memdata <= {
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mem[saraddr+7],
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mem[saraddr+6],
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mem[saraddr+5],
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mem[saraddr+4],
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mem[saraddr+3],
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mem[saraddr+2],
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mem[saraddr+1],
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mem[saraddr]
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};
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case (araddr[2:0])
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3'h0: begin
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memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
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end
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3'h1: begin
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memdata <= {rm0, rm7, rm6, rm5, rm4, rm3, rm2, rm1};
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end
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3'h2: begin
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memdata <= {rm1, rm0, rm7, rm6, rm5, rm4, rm3, rm2};
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end
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3'h3: begin
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memdata <= {rm2, rm1, rm0, rm7, rm6, rm5, rm4, rm3};
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end
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3'h4: begin
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memdata <= {rm3, rm2, rm1, rm0, rm7, rm6, rm5, rm4};
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end
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3'h5: begin
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memdata <= {rm4, rm3, rm2, rm1, rm0, rm7, rm6, rm5};
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end
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3'h6: begin
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memdata <= {rm5, rm4, rm3, rm2, rm1, rm0, rm7, rm6};
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end
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3'h7: begin
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memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
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end
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endcase
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if (awvalid) begin
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if (wstrb[7]) mem[sawaddr+7] = wdata[63:56];
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if (wstrb[6]) mem[sawaddr+6] = wdata[55:48];
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if (wstrb[5]) mem[sawaddr+5] = wdata[47:40];
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if (wstrb[4]) mem[sawaddr+4] = wdata[39:32];
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if (wstrb[3]) mem[sawaddr+3] = wdata[31:24];
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if (wstrb[2]) mem[sawaddr+2] = wdata[23:16];
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if (wstrb[1]) mem[sawaddr+1] = wdata[15:08];
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if (wstrb[0]) mem[sawaddr+0] = wdata[07:00];
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case (awaddr[2:0])
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3'h0: begin
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if (wstrb[7]) mem7[sawaddr7] = wdata[63:56];
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if (wstrb[6]) mem6[sawaddr6] = wdata[55:48];
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if (wstrb[5]) mem5[sawaddr5] = wdata[47:40];
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if (wstrb[4]) mem4[sawaddr4] = wdata[39:32];
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if (wstrb[3]) mem3[sawaddr3] = wdata[31:24];
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if (wstrb[2]) mem2[sawaddr2] = wdata[23:16];
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if (wstrb[1]) mem1[sawaddr1] = wdata[15:08];
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if (wstrb[0]) mem0[sawaddr0] = wdata[07:00];
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end
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3'h1: begin
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if (wstrb[7]) mem0[sawaddr0] = wdata[63:56];
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if (wstrb[6]) mem7[sawaddr7] = wdata[55:48];
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if (wstrb[5]) mem6[sawaddr6] = wdata[47:40];
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if (wstrb[4]) mem5[sawaddr5] = wdata[39:32];
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if (wstrb[3]) mem4[sawaddr4] = wdata[31:24];
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if (wstrb[2]) mem3[sawaddr3] = wdata[23:16];
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if (wstrb[1]) mem2[sawaddr2] = wdata[15:08];
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if (wstrb[0]) mem1[sawaddr1] = wdata[07:00];
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end
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3'h2: begin
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if (wstrb[7]) mem1[sawaddr1] = wdata[63:56];
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if (wstrb[6]) mem0[sawaddr0] = wdata[55:48];
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if (wstrb[5]) mem7[sawaddr7] = wdata[47:40];
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if (wstrb[4]) mem6[sawaddr6] = wdata[39:32];
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if (wstrb[3]) mem5[sawaddr5] = wdata[31:24];
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if (wstrb[2]) mem4[sawaddr4] = wdata[23:16];
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if (wstrb[1]) mem3[sawaddr3] = wdata[15:08];
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if (wstrb[0]) mem2[sawaddr2] = wdata[07:00];
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end
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3'h3: begin
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if (wstrb[7]) mem2[sawaddr2] = wdata[63:56];
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if (wstrb[6]) mem1[sawaddr1] = wdata[55:48];
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if (wstrb[5]) mem0[sawaddr0] = wdata[47:40];
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if (wstrb[4]) mem7[sawaddr7] = wdata[39:32];
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if (wstrb[3]) mem6[sawaddr6] = wdata[31:24];
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if (wstrb[2]) mem5[sawaddr5] = wdata[23:16];
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if (wstrb[1]) mem4[sawaddr4] = wdata[15:08];
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if (wstrb[0]) mem3[sawaddr3] = wdata[07:00];
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end
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3'h4: begin
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if (wstrb[7]) mem3[sawaddr3] = wdata[63:56];
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if (wstrb[6]) mem2[sawaddr2] = wdata[55:48];
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if (wstrb[5]) mem1[sawaddr1] = wdata[47:40];
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if (wstrb[4]) mem0[sawaddr0] = wdata[39:32];
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if (wstrb[3]) mem7[sawaddr7] = wdata[31:24];
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if (wstrb[2]) mem6[sawaddr6] = wdata[23:16];
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if (wstrb[1]) mem5[sawaddr5] = wdata[15:08];
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if (wstrb[0]) mem4[sawaddr4] = wdata[07:00];
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end
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3'h5: begin
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if (wstrb[7]) mem4[sawaddr4] = wdata[63:56];
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if (wstrb[6]) mem3[sawaddr3] = wdata[55:48];
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if (wstrb[5]) mem2[sawaddr2] = wdata[47:40];
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if (wstrb[4]) mem1[sawaddr1] = wdata[39:32];
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if (wstrb[3]) mem0[sawaddr0] = wdata[31:24];
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if (wstrb[2]) mem7[sawaddr7] = wdata[23:16];
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if (wstrb[1]) mem6[sawaddr6] = wdata[15:08];
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if (wstrb[0]) mem5[sawaddr5] = wdata[07:00];
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end
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3'h6: begin
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if (wstrb[7]) mem5[sawaddr5] = wdata[63:56];
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if (wstrb[6]) mem4[sawaddr4] = wdata[55:48];
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if (wstrb[5]) mem3[sawaddr3] = wdata[47:40];
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if (wstrb[4]) mem2[sawaddr2] = wdata[39:32];
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if (wstrb[3]) mem1[sawaddr1] = wdata[31:24];
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if (wstrb[2]) mem0[sawaddr0] = wdata[23:16];
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if (wstrb[1]) mem7[sawaddr7] = wdata[15:08];
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if (wstrb[0]) mem6[sawaddr6] = wdata[07:00];
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end
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3'h7: begin
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if (wstrb[7]) mem6[sawaddr6] = wdata[63:56];
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if (wstrb[6]) mem5[sawaddr5] = wdata[55:48];
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if (wstrb[5]) mem4[sawaddr4] = wdata[47:40];
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if (wstrb[4]) mem3[sawaddr3] = wdata[39:32];
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if (wstrb[3]) mem2[sawaddr2] = wdata[31:24];
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if (wstrb[2]) mem1[sawaddr1] = wdata[23:16];
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if (wstrb[1]) mem0[sawaddr0] = wdata[15:08];
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if (wstrb[0]) mem7[sawaddr7] = wdata[07:00];
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end
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endcase
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end
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end
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assign arready = 1'b1;
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assign awready = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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endmodule
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@ -18,25 +18,25 @@ module soc_sim (
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input bit core_clk
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);
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logic rst_l;
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logic dbg_rst_l;
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logic rst_l;
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logic dbg_rst_l;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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bit [31:0] cycleCnt;
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logic mailbox_data_val;
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int commit_count;
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bit [31:0] cycleCnt;
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logic mailbox_data_val;
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int commit_count;
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logic wb_valid;
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logic [ 4:0] wb_dest;
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logic [31:0] wb_data;
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logic wb_valid;
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logic [4:0] wb_dest;
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logic [31:0] wb_data;
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wire [63:0] WriteData;
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string abi_reg [32]; // ABI register names
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wire [63:0] WriteData;
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string abi_reg[32]; // ABI register names
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assign WriteData = rvsoc.lsu_axi_wdata;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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@ -130,6 +130,8 @@ module soc_sim (
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end
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end
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reg [7:0] hex[(1<<rvsoc.imem.MEM_DEPTH)-1:0];
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initial begin
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abi_reg[0] = "zero";
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abi_reg[1] = "ra";
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@ -170,22 +172,45 @@ module soc_sim (
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fd = $fopen("console.log", "w");
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commit_count = 0;
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$readmemh("program.hex", rvsoc.lmem.mem);
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$readmemh("program.hex", rvsoc.imem.mem);
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$readmemh("program.hex", hex);
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for (
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reg [rvsoc.imem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.imem.MEM_DEPTH - 3)); i++
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) begin
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rvsoc.imem.mem0[i] = hex[(i << 3) + 0];
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rvsoc.imem.mem1[i] = hex[(i << 3) + 1];
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rvsoc.imem.mem2[i] = hex[(i << 3) + 2];
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rvsoc.imem.mem3[i] = hex[(i << 3) + 3];
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rvsoc.imem.mem4[i] = hex[(i << 3) + 4];
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rvsoc.imem.mem5[i] = hex[(i << 3) + 5];
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rvsoc.imem.mem6[i] = hex[(i << 3) + 6];
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rvsoc.imem.mem7[i] = hex[(i << 3) + 7];
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end
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for (
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reg [rvsoc.lmem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.lmem.MEM_DEPTH - 3)); i++
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) begin
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rvsoc.lmem.mem0[i] = hex[(i << 3) + 0];
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rvsoc.lmem.mem1[i] = hex[(i << 3) + 1];
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rvsoc.lmem.mem2[i] = hex[(i << 3) + 2];
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rvsoc.lmem.mem3[i] = hex[(i << 3) + 3];
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rvsoc.lmem.mem4[i] = hex[(i << 3) + 4];
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rvsoc.lmem.mem5[i] = hex[(i << 3) + 5];
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rvsoc.lmem.mem6[i] = hex[(i << 3) + 6];
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rvsoc.lmem.mem7[i] = hex[(i << 3) + 7];
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end
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end
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assign rst_l = cycleCnt > 20;
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assign dbg_rst_l = cycleCnt > 10;
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soc_top rvsoc (
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.clk(core_clk),
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.rst(rst_l),
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.clk (core_clk),
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.rst (rst_l),
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.dbg_rst(dbg_rst_l),
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.jtag_tdo(jtag_tdo),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo (jtag_tdo),
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.jtag_tck (jtag_tck),
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.jtag_tms (jtag_tms),
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.jtag_tdi (jtag_tdi),
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.jtag_trst_n(jtag_trst_n)
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);
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@ -193,10 +218,10 @@ module soc_sim (
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.clk_i (core_clk),
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.rst_ni(rst_l),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo(jtag_tdo),
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.jtag_tck (jtag_tck),
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.jtag_tms (jtag_tms),
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.jtag_tdi (jtag_tdi),
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.jtag_tdo (jtag_tdo),
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.jtag_trst_n(jtag_trst_n),
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.jtag_srst_n()
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);
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