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Fixes in riviera support pushed into 1.3

This commit is contained in:
Daniel Mlynek 2020-11-20 16:38:02 +01:00
parent ebfb8abf88
commit 9755d8f94a
2 changed files with 2 additions and 4 deletions
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2
design/dec/el2_dec_decode_ctl.sv
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@ -602,7 +602,6 @@ end // else: !if(pt.BTB_ENABLE==1)
always_comb begin always_comb begin
found = 0; found = 0;
cam_wen[NBLOAD_SIZE_MSB:0] = '0;
for (int i=0; i<NBLOAD_SIZE; i++) begin for (int i=0; i<NBLOAD_SIZE; i++) begin
if (~found) begin if (~found) begin
if (~cam[i].valid) begin if (~cam[i].valid) begin
@ -618,7 +617,6 @@ end // else: !if(pt.BTB_ENABLE==1)
end end
end end
assign cam_write = lsu_nonblock_load_valid_m; assign cam_write = lsu_nonblock_load_valid_m;
assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0]; assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0];

4
tools/Makefile
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@ -34,7 +34,7 @@ IRUN = xrun
VCS = vcs VCS = vcs
VLOG = qverilog VLOG = qverilog
VERILATOR = verilator VERILATOR = verilator
RIVEIRA = riviera RIVIERA = riviera
GCC_PREFIX = riscv64-unknown-elf GCC_PREFIX = riscv64-unknown-elf
BUILD_DIR = snapshots/${snapshot} BUILD_DIR = snapshots/${snapshot}
TBDIR = ${RV_ROOT}/testbench TBDIR = ${RV_ROOT}/testbench
@ -103,7 +103,7 @@ all: clean verilator
clean: clean:
rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* snapshots swerv* \ rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* snapshots swerv* \
verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work\ verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work\
work dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb