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Add jtag

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colin 2022-03-07 13:08:10 +00:00
parent 7045b803ca
commit ddf80fde8d
37 changed files with 10062 additions and 0 deletions
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build/
obj_dir/
gen/

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export RV_ROOT = ${PWD}/../..
GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
ABI = -mabi=ilp32 -march=rv32imc
DEMODIR = ${PWD}
BUILD_DIR = ${DEMODIR}/build
RV_SOC = ${RV_ROOT}/soc
TEST = jtag
ifdef debug
DEBUG_PLUS = +dumpon
VERILATOR_DEBUG = --trace
endif
LINK = $(DEMODIR)/link.ld
# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
CFLAGS += "-std=c++11"
# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
# -O2 for faster runtime (slower compiles), or -O for balance.
VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
# Targets
all: clean verilator
clean:
rm -rf build obj_dir
swerv_define :
BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set build_axi4
##################### Verilog Builds #####################################
verilator-build: swerv_define
echo '`undef RV_ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
verilator --cc -CFLAGS ${CFLAGS} \
$(BUILD_DIR)/common_defines.vh \
$(BUILD_DIR)/el2_pdef.vh \
-I${BUILD_DIR} \
-Wno-WIDTH \
-Wno-UNOPTFLAT \
-F ${RV_SOC}/soc_top.mk \
-F ${RV_SOC}/soc_sim.mk \
$(RV_SOC)/soc_sim.sv \
--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
cp ${DEMODIR}/test_soc_sim.cpp obj_dir
$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
##################### Simulation Runs #####################################
verilator: program.hex verilator-build
cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
sim:
cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
##################### Test hex Build #####################################
program.hex: $(TEST).o $(LINK)
@echo Building $(TEST)
$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
@echo Completed building $(TEST)
%.o : %.s swerv_define
$(GCC_PREFIX)-cpp -g -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
##################### openocd #####################################
openocd:
openocd -f swerv.cfg
gdb:
$(GDB_PREFIX) -x gdbinit
help:
@echo Possible targets: verilator help clean all verilator-build program.hex
.PHONY: help clean verilator

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# jtag simulation
## start openocd
`openocd -d -f swerv.cfg`
## start gdb
`/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"`
## quick start
At demo/jtag/
1. `make all`
2. `make openocd`
3. `make gdb`

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set debug remote 1
target extended-remote :3333
set remotetimeout 5000

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Assembly code for Hello World
// Not using only ALU ops for creating the string
#include "defines.h"
#define STDOUT 0xd0580000
// Code to execute
.section .text
.global _start
_start:
// Clear minstret
csrw minstret, zero
csrw minstreth, zero
// Set up MTVEC - not expecting to use it though
li x1, RV_ICCM_SADR
csrw mtvec, x1
// Enable Caches in MRAC
li x1, 0x5f555555
csrw 0x7c0, x1
// Load string from hw_data
// and write to stdout address
li x3, STDOUT
la x4, hw_data
loop:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
bnez x5, loop
li x3, STDOUT
la x4, hw_data
loop2:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
bnez x5, loop2
loop3:
beq x0, x0, loop3
// Write 0xff to STDOUT for TB to terminate test.
_finish:
li x3, STDOUT
addi x5, x0, 0xff
sb x5, 0(x3)
beq x0, x0, _finish
.rept 100
nop
.endr
.global hw_data
.data
hw_data:
.ascii "----------------------------------\n"
.ascii "Hello World Colin.liang EL2@WDC !!\n"
.ascii "----------------------------------\n"
.byte 0

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0;
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0x4000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }
}

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LOCATE COMP "clk" SITE "P3";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 25 MHZ;
LOCATE COMP "dbg_rst" SITE "N2";
IOBUF PORT "dbg_rst" IO_TYPE=LVCMOS33;
FREQUENCY PORT "dbg_rst" 25 MHZ;
LOCATE COMP "rst" SITE "N3";
IOBUF PORT "rst" IO_TYPE=LVCMOS33;
FREQUENCY PORT "rst" 25 MHZ;
LOCATE COMP "jtag_tck" SITE "T2";
IOBUF PORT "jtag_tck" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tck" 25 MHZ;
LOCATE COMP "jtag_tms" SITE "T3";
IOBUF PORT "jtag_tms" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tms" 25 MHZ;
LOCATE COMP "jtag_tdi" SITE "N4";
IOBUF PORT "jtag_tdi" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tdi" 25 MHZ;
LOCATE COMP "jtag_trst_n" SITE "M3";
IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_trst_n" 25 MHZ;
LOCATE COMP "jtag_tdo" SITE "M4";
IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;

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# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
# speaking the remote_bitbang protocol. The adapter is implemented as
# SystemVerilog DPI module.
adapter driver remote_bitbang
remote_bitbang host localhost
remote_bitbang port 44853
# Target configuration for the riscv chip
set _CHIPNAME riscv
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x1000008b
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
# Configure work area in on-chip SRAM
# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
riscv expose_csrs 1988
# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Increase timeouts in simulation
riscv set_command_timeout_sec 4200
# Conclude OpenOCD configuration
init
# Halt the target
halt

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#!/bin/bash
# if [ $# -ne 1 -o ! -d "$1" ]; then
# echo "Usage: $0 <design>" >&2
# exit 1
# fi
set -ex
PWD=$(pwd)
SOC=$PWD/../../soc
design=${1%/}
YOSYS_COARSE=true
YOSYS_GLOBRST=false
YOSYS_SPLITNETS=false
TOP="soc_top"
RTL=$(cat ../../soc/soc_top.mk)
rtl_files=""
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
# # rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
for src in $RTL; do
rtl_files="$rtl_files $SOC/$src"
done
mkdir -p gen
rm -rf gen/*
mkdir gen/design
filelist=""
for file in $rtl_files; do
filelist="$filelist $file"
done
sv2v -Ibuild $filelist > gen/soc_top.v
{
# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
# for file in $rtl_files; do
# echo "read_verilog -sv -I../../design/include $file"
# done
echo "read_verilog gen/soc_top.v"
if test -n "$TOP"; then
echo "hierarchy -check -top $TOP"
else
echo "hierarchy -check"
fi
if $YOSYS_GLOBRST; then
# insertation of global reset (e.g. for FPGA cores)
echo "add -global_input globrst 1"
echo "proc -global_arst globrst"
fi
echo "synth -run coarse; opt -fine"
# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
if ! $YOSYS_COARSE; then
echo "memory_map; techmap; opt; abc -dff; clean"
fi
if $YOSYS_SPLITNETS; then
# icarus verilog has a performance problems when there are
# dependencies between the bits of a long vector
echo "splitnets; clean"
fi
if $YOSYS_COARSE; then
echo "write_verilog -noexpr -noattr gen/synth.v"
else
echo "select -assert-none t:\$[!_]"
echo "write_verilog -noattr gen/synth.v"
fi
echo "synth_ecp5 -top $TOP -json gen/soc.json"
# echo "synth_xilinx -top $TOP"
} > gen/synth.ys
yosys -v2 -l gen/synth.log gen/synth.ys
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#include <stdlib.h>
#include <iostream>
#include <utility>
#include <string>
#include "Vsoc_sim.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
vluint64_t main_time = 0;
double sc_time_stamp () {
return main_time;
}
int main(int argc, char** argv) {
std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
Verilated::commandArgs(argc, argv);
Vsoc_sim* soc = new Vsoc_sim;
// init trace dump
VerilatedVcdC* tfp = NULL;
#if VM_TRACE
Verilated::traceEverOn(true);
tfp = new VerilatedVcdC;
soc->trace (tfp, 24);
tfp->open ("sim.vcd");
#endif
// Simulate
while(!Verilated::gotFinish()){
#if VM_TRACE
tfp->dump (main_time);
#endif
main_time += 5;
soc->core_clk = !soc->core_clk;
soc->eval();
}
#if VM_TRACE
tfp->close();
#endif
std::cout << "\nVerilatorTB: End of sim" << std::endl;
exit(EXIT_SUCCESS);
}

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
module axi_slv #(
TAGW = 1
) (
input aclk,
input rst_l,
input arvalid,
output reg arready,
input [ 31:0] araddr,
input [TAGW-1:0] arid,
input [ 7:0] arlen,
input [ 1:0] arburst,
input [ 2:0] arsize,
output reg rvalid,
input rready,
output reg [ 63:0] rdata,
output reg [ 1:0] rresp,
output reg [TAGW-1:0] rid,
output rlast,
input awvalid,
output awready,
input [ 31:0] awaddr,
input [TAGW-1:0] awid,
input [ 7:0] awlen,
input [ 1:0] awburst,
input [ 2:0] awsize,
input [63:0] wdata,
input [ 7:0] wstrb,
input wvalid,
output wready,
output reg bvalid,
input bready,
output reg [ 1:0] bresp,
output reg [TAGW-1:0] bid
);
parameter MEM_DEPTH = 17; // memory size = 0x8000 = 32k
bit [7:0] mem[(1<<MEM_DEPTH)-1:0];
bit [63:0] memdata;
wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];
wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH-1:0];
always @(posedge aclk or negedge rst_l) begin
if (!rst_l) begin
rvalid <= 0;
bvalid <= 0;
end else begin
bid <= awid;
rid <= arid;
rvalid <= arvalid;
bvalid <= awvalid;
rdata <= memdata;
end
end
always @(negedge aclk) begin
if (arvalid)
memdata <= {
mem[saraddr+7],
mem[saraddr+6],
mem[saraddr+5],
mem[saraddr+4],
mem[saraddr+3],
mem[saraddr+2],
mem[saraddr+1],
mem[saraddr]
};
if (awvalid) begin
if (wstrb[7]) mem[sawaddr+7] = wdata[63:56];
if (wstrb[6]) mem[sawaddr+6] = wdata[55:48];
if (wstrb[5]) mem[sawaddr+5] = wdata[47:40];
if (wstrb[4]) mem[sawaddr+4] = wdata[39:32];
if (wstrb[3]) mem[sawaddr+3] = wdata[31:24];
if (wstrb[2]) mem[sawaddr+2] = wdata[23:16];
if (wstrb[1]) mem[sawaddr+1] = wdata[15:08];
if (wstrb[0]) mem[sawaddr+0] = wdata[07:00];
end
end
assign arready = 1'b1;
assign awready = 1'b1;
assign wready = 1'b1;
assign rresp = 2'b0;
assign bresp = 2'b0;
assign rlast = 1'b1;
endmodule

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// connects LSI master to external AXI slave and DMA slave
module axi_lsu_dma_bridge #(
parameter M_ID_WIDTH = 8,
parameter S0_ID_WIDTH = 8
) (
input clk,
input reset_l,
// master read bus
input m_arvalid,
input [M_ID_WIDTH-1:0] m_arid,
input [ 31:0] m_araddr,
output m_arready,
output m_rvalid,
input m_rready,
output [ 63:0] m_rdata,
output [M_ID_WIDTH-1:0] m_rid,
output [ 1:0] m_rresp,
output m_rlast,
// master write bus
input m_awvalid,
input [M_ID_WIDTH-1:0] m_awid,
input [ 31:0] m_awaddr,
output m_awready,
input m_wvalid,
output m_wready,
output [ 1:0] m_bresp,
output m_bvalid,
output [M_ID_WIDTH-1:0] m_bid,
input m_bready,
// slave 0 if general ext memory
output s0_arvalid,
input s0_arready,
input s0_rvalid,
input [S0_ID_WIDTH-1:0] s0_rid,
input [ 1:0] s0_rresp,
input [ 63:0] s0_rdata,
input s0_rlast,
output s0_rready,
output s0_awvalid,
input s0_awready,
output s0_wvalid,
input s0_wready,
input [ 1:0] s0_bresp,
input s0_bvalid,
input [S0_ID_WIDTH-1:0] s0_bid,
output s0_bready,
// slave 1 if DMA port
output s1_arvalid,
input s1_arready,
input s1_rvalid,
input [ 1:0] s1_rresp,
input [63:0] s1_rdata,
input s1_rlast,
output s1_rready,
output s1_awvalid,
input s1_awready,
output s1_wvalid,
input s1_wready,
input [1:0] s1_bresp,
input s1_bvalid,
output s1_bready
);
parameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs
localparam IDFIFOSZ = $clog2(`RV_DMA_BUF_DEPTH);
bit [31:0] iccm_real_base_addr = `RV_ICCM_SADR;
wire ar_slave_select;
wire aw_slave_select;
wire w_slave_select;
wire rresp_select;
wire bresp_select;
wire ar_iccm_select;
wire aw_iccm_select;
reg [1:0] wsel_iptr, wsel_optr;
reg [2:0] wsel_count;
reg [3:0] wsel;
reg [M_ID_WIDTH-1:0] arid[1<<IDFIFOSZ];
reg [M_ID_WIDTH-1:0] awid[1<<IDFIFOSZ];
reg [IDFIFOSZ-1:0] arid_cnt;
reg [IDFIFOSZ-1:0] awid_cnt;
reg [IDFIFOSZ-1:0] rid_cnt;
reg [IDFIFOSZ-1:0] bid_cnt;
// 1 select slave 1; 0 - slave 0
assign ar_slave_select = ar_iccm_select;
assign aw_slave_select = aw_iccm_select;
assign ar_iccm_select = m_araddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
assign aw_iccm_select = m_awaddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
assign s0_arvalid = m_arvalid & ~ar_slave_select;
assign s1_arvalid = m_arvalid & ar_slave_select;
assign m_arready = ar_slave_select ? s1_arready : s0_arready;
assign s0_awvalid = m_awvalid & ~aw_slave_select;
assign s1_awvalid = m_awvalid & aw_slave_select;
assign m_awready = aw_slave_select ? s1_awready : s0_awready;
assign s0_wvalid = m_wvalid & ~w_slave_select;
assign s1_wvalid = m_wvalid & w_slave_select;
assign m_wready = w_slave_select ? s1_wready : s0_wready;
assign w_slave_select = (wsel_count == 0 || wsel_count[2]) ? aw_slave_select : wsel[wsel_optr];
assign m_rvalid = s0_rvalid | s1_rvalid;
assign s0_rready = m_rready & ~rresp_select;
assign s1_rready = m_rready & rresp_select;
assign m_rdata = rresp_select ? s1_rdata : s0_rdata;
assign m_rresp = rresp_select ? s1_rresp : s0_rresp;
assign m_rid = rresp_select ? arid[rid_cnt] : s0_rid;
assign m_rlast = rresp_select ? s1_rlast : s0_rlast;
assign rresp_select = s1_rvalid & ~s0_rvalid;
assign m_bvalid = s0_bvalid | s1_bvalid;
assign s0_bready = m_bready & ~bresp_select;
assign s1_bready = m_bready & bresp_select;
assign m_bid = bresp_select ? awid[bid_cnt] : s0_bid;
assign m_bresp = bresp_select ? s1_bresp : s0_bresp;
assign bresp_select = s1_bvalid & ~s0_bvalid;
// W-channel select fifo
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
wsel_count <= '0;
wsel_iptr <= '0;
wsel_optr <= '0;
end else begin
if (m_awvalid & m_awready) begin
wsel[wsel_iptr] <= aw_slave_select;
if (!(m_wready & m_wvalid)) wsel_count <= wsel_count + 1;
wsel_iptr <= wsel_iptr + 1;
end
if (m_wvalid & m_wready) begin
if (!(m_awready & m_awvalid)) wsel_count <= wsel_count - 1;
wsel_optr <= wsel_optr + 1;
end
end
// id replacement for narrow ID slave
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
arid_cnt <= '0;
rid_cnt <= '0;
end else begin
if (ar_slave_select & m_arready & m_arvalid) begin
arid[arid_cnt] <= m_arid;
arid_cnt <= arid_cnt + 1;
end
if (rresp_select & m_rready & m_rvalid) begin
rid_cnt <= rid_cnt + 1;
end
end
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
awid_cnt <= '0;
bid_cnt <= '0;
end else begin
if (aw_slave_select & m_awready & m_awvalid) begin
awid[awid_cnt] <= m_awid;
awid_cnt <= awid_cnt + 1;
end
if (bresp_select & m_bready & m_bvalid) begin
bid_cnt <= bid_cnt + 1;
end
end
endmodule

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Run time disassembler functions
// supports RISCV extentions I, C, M, A
`ifndef RV_NUM_THREADS
`define RV_NUM_THREADS 1
`endif
bit[31:0] [31:0] gpr[`RV_NUM_THREADS];
// main DASM function
function string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv, input tid=0);
dasm = (opcode[1:0] == 2'b11) ? dasm32(opcode, pc, tid) : dasm16(opcode, pc, tid);
if(regn) gpr[tid][regn] = regv;
endfunction
///////////////// 16 bits instructions ///////////////////////
function string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
case(opcode[1:0])
0: return dasm16_0(opcode, tid);
1: return dasm16_1(opcode, pc);
2: return dasm16_2(opcode);
endcase
return $sformatf(".short 0x%h", opcode[15:0]);
endfunction
function string dasm16_0( input[31:0] opcode, tid);
case(opcode[15:13])
3'b000: return dasm16_ciw(opcode);
3'b001: return {"c.fld ", dasm16_cl(opcode, tid)};
3'b010: return {"c.lw ", dasm16_cl(opcode, tid)};
3'b011: return {"c.flw ", dasm16_cl(opcode, tid)};
3'b101: return {"c.fsd ", dasm16_cl(opcode, tid)};
3'b110: return {"c.sw ", dasm16_cl(opcode, tid)};
3'b111: return {"c.fsw ", dasm16_cl(opcode, tid)};
endcase
return $sformatf(".short 0x%h", opcode[15:0]);
endfunction
function string dasm16_ciw( input[31:0] opcode);
int imm;
imm=0;
if(opcode[15:0] == 0) return ".short 0";
{imm[5:4],imm[9:6],imm[2],imm[3]} = opcode[12:5];
return $sformatf("c.addi4spn %s,0x%0h", abi_reg[opcode[4:2]+8], imm);
endfunction
function string dasm16_cl( input[31:0] opcode, input tid=0);
int imm;
imm=0;
imm[5:3] = opcode[12:10];
imm[7:6] = opcode[6:5];
return $sformatf(" %s,%0d(%s) [%h]", abi_reg[opcode[4:2]+8], imm, abi_reg[opcode[9:7]+8], gpr[tid][opcode[9:7]+8]+imm);
endfunction
function string dasm16_1( input[31:0] opcode, input[31:0] pc);
case(opcode[15:13])
3'b000: return opcode[11:7]==0 ? "c.nop" : {"c.addi ",dasm16_ci(opcode)};
3'b001: return {"c.jal ", dasm16_cj(opcode, pc)};
3'b010: return {"c.li ", dasm16_ci(opcode)};
3'b011: return dasm16_1_3(opcode);
3'b100: return dasm16_cr(opcode);
3'b101: return {"c.j ", dasm16_cj(opcode, pc)};
3'b110: return {"c.beqz ", dasm16_cb(opcode, pc)};
3'b111: return {"c.bnez ", dasm16_cb(opcode, pc)};
endcase
endfunction
function string dasm16_ci( input[31:0] opcode);
int imm;
imm=0;
imm[4:0] = opcode[6:2];
if(opcode[12]) imm [31:5] = '1;
return $sformatf("%s,%0d", abi_reg[opcode[11:7]], imm);
endfunction
function string dasm16_cj( input[31:0] opcode, input[31:0] pc);
bit[31:0] imm;
imm=0;
{imm[11],imm[4],imm[9:8],imm[10],imm[6], imm[7],imm[3:1], imm[5]} = opcode[12:2];
if(opcode[12]) imm [31:12] = '1;
return $sformatf("0x%0h", imm+pc);
endfunction
function string dasm16_cb( input[31:0] opcode, input[31:0] pc);
bit[31:0] imm;
imm=0;
{imm[8],imm[4:3]} = opcode[12:10];
{imm[7:6],imm[2:1], imm[5]} = opcode[6:2];
if(opcode[12]) imm [31:9] = '1;
return $sformatf("%s,0x%0h",abi_reg[opcode[9:7]+8], imm+pc);
endfunction
function string dasm16_cr( input[31:0] opcode);
bit[31:0] imm;
imm = 0;
imm[4:0] = opcode[6:2];
if(opcode[5]) imm [31:5] = '1;
case(opcode[11:10])
0: return $sformatf("c.srli %s,%0d", abi_reg[opcode[9:7]+8], imm[5:0]);
1: return $sformatf("c.srai %s,%0d", abi_reg[opcode[9:7]+8], imm[5:0]);
2: return $sformatf("c.andi %s,0x%0h", abi_reg[opcode[9:7]+8], imm);
endcase
case(opcode[6:5])
0: return $sformatf("c.sub %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
1: return $sformatf("c.xor %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
2: return $sformatf("c.or %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
3: return $sformatf("c.and %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
endcase
endfunction
function string dasm16_1_3( input[31:0] opcode);
int imm;
imm=0;
if(opcode[11:7] == 2) begin
{imm[4], imm[6],imm[8:7], imm[5]} = opcode[6:2];
if(opcode[12]) imm [31:9] = '1;
return $sformatf("c.addi16sp %0d", imm);
end
else begin
imm[16:12] = opcode[6:2];
if(opcode[12]) imm [31:17] = '1;
return $sformatf("c.lui %s,0x%0h", abi_reg[opcode[11:7]], imm);
end
endfunction
function string dasm16_2( input[31:0] opcode, input tid=0);
case(opcode[15:13])
3'b000: return {"c.slli ", dasm16_ci(opcode)};
3'b001: return {"c.fldsp ", dasm16_cls(opcode,1,tid)};
3'b010: return {"c.lwsp ", dasm16_cls(opcode,0,tid)};
3'b011: return {"c.flwsp ", dasm16_cls(opcode,0,tid)};
3'b101: return {"c.fsdsp ", dasm16_css(opcode,1,tid)};
3'b110: return {"c.swsp ", dasm16_css(opcode,0,tid)};
3'b111: return {"c.fswsp ", dasm16_css(opcode,0,tid)};
endcase
if(opcode[12]) begin
if(opcode[12:2] == 0) return "c.ebreak";
else if(opcode[6:2] == 0) return $sformatf("c.jalr %s", abi_reg[opcode[11:7]]);
else return $sformatf("c.add %s,%s", abi_reg[opcode[11:7]], abi_reg[opcode[6:2]]);
end
else begin
if(opcode[6:2] == 0) return $sformatf("c.jr %s", abi_reg[opcode[11:7]]);
else return $sformatf("c.mv %s,%s", abi_reg[opcode[11:7]], abi_reg[opcode[6:2]]);
end
endfunction
function string dasm16_cls( input[31:0] opcode, input sh1=0, tid=0);
bit[31:0] imm;
imm=0;
if(sh1) {imm[4:3],imm[8:6]} = opcode[6:2];
else {imm[4:2],imm[7:6]} = opcode[6:2];
imm[5] = opcode[12];
return $sformatf("%s,0x%0h [%h]", abi_reg[opcode[11:7]], imm, gpr[tid][2]+imm);
endfunction
function string dasm16_css( input[31:0] opcode, input sh1=0, tid=0);
bit[31:0] imm;
imm=0;
if(sh1) {imm[5:3],imm[8:6]} = opcode[12:7];
else {imm[5:2],imm[7:6]} = opcode[12:7];
return $sformatf("%s,0x%0h [%h]", abi_reg[opcode[6:2]], imm, gpr[tid][2]+imm);
endfunction
///////////////// 32 bit instructions ///////////////////////
function string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
case(opcode[6:0])
7'b0110111: return {"lui ", dasm32_u(opcode)};
7'b0010111: return {"auipc ", dasm32_u(opcode)};
7'b1101111: return {"jal ", dasm32_j(opcode,pc)};
7'b1100111: return {"jalr ", dasm32_jr(opcode,pc)};
7'b1100011: return dasm32_b(opcode,pc);
7'b0000011: return dasm32_l(opcode,tid);
7'b0100011: return dasm32_s(opcode,tid);
7'b0010011: return dasm32_ai(opcode);
7'b0110011: return dasm32_ar(opcode);
7'b0001111: return {"fence", dasm32_fence(opcode)};
7'b1110011: return dasm32_e(opcode);
7'b0101111: return dasm32_a(opcode,tid);
endcase
return $sformatf(".long 0x%h", opcode);
endfunction
function string dasm32_u( input[31:0] opcode);
bit[31:0] imm;
imm=0;
imm[31:12] = opcode[31:12];
return $sformatf("%s,0x%0h", abi_reg[opcode[11:7]], imm);
endfunction
function string dasm32_j( input[31:0] opcode, input[31:0] pc);
int imm;
imm=0;
{imm[20], imm[10:1], imm[11], imm[19:12]} = opcode[31:12];
if(opcode[31]) imm[31:20] = '1;
return $sformatf("%s,0x%0h",abi_reg[opcode[11:7]], imm+pc);
endfunction
function string dasm32_jr( input[31:0] opcode, input[31:0] pc);
int imm;
imm=0;
imm[11:1] = opcode[31:19];
if(opcode[31]) imm[31:12] = '1;
return $sformatf("%s,%s,0x%0h",abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm+pc);
endfunction
function string dasm32_b( input[31:0] opcode, input[31:0] pc);
int imm;
string mn;
imm=0;
{imm[12],imm[10:5]} = opcode[31:25];
{imm[4:1],imm[11]} = opcode[11:7];
if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12])
0: mn = "beq ";
1: mn = "bne ";
2,3 : return $sformatf(".long 0x%h", opcode);
4: mn = "blt ";
5: mn = "bge ";
6: mn = "bltu ";
7: mn = "bgeu ";
endcase
return $sformatf("%s%s,%s,0x%0h", mn, abi_reg[opcode[19:15]], abi_reg[opcode[24:20]], imm+pc);
endfunction
function string dasm32_l( input[31:0] opcode, input tid=0);
int imm;
string mn;
imm=0;
imm[11:0] = opcode[31:20];
if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12])
0: mn = "lb ";
1: mn = "lh ";
2: mn = "lw ";
4: mn = "lbu ";
5: mn = "lhu ";
default : return $sformatf(".long 0x%h", opcode);
endcase
return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[11:7]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
endfunction
function string dasm32_s( input[31:0] opcode, input tid=0);
int imm;
string mn;
imm=0;
imm[11:5] = opcode[31:25];
imm[4:0] = opcode[11:7];
if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12])
0: mn = "sb ";
1: mn = "sh ";
2: mn = "sw ";
default : return $sformatf(".long 0x%h", opcode);
endcase
return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[24:20]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
endfunction
function string dasm32_ai( input[31:0] opcode);
int imm;
string mn;
imm=0;
imm[11:0] = opcode[31:20];
if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12])
0: mn = "addi ";
2: mn = "slti ";
3: mn = "sltiu ";
4: mn = "xori ";
6: mn = "ori ";
7: mn = "andi ";
default: return dasm32_si(opcode);
endcase
return $sformatf("%s%s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
endfunction
function string dasm32_si( input[31:0] opcode);
int imm;
string mn;
imm = opcode[24:20];
case(opcode[14:12])
1: mn = "slli";
5: mn = opcode[30] ? "srli": "srai";
endcase
return $sformatf("%s %s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
endfunction
function string dasm32_ar( input[31:0] opcode);
string mn;
if(opcode[25])
case(opcode[14:12])
0: mn = "mul ";
1: mn = "mulh ";
2: mn = "mulhsu ";
3: mn = "mulhu ";
4: mn = "div ";
5: mn = "divu ";
6: mn = "rem ";
7: mn = "remu ";
endcase
else
case(opcode[14:12])
0: mn = opcode[30]? "sub ":"add ";
1: mn = "sll ";
2: mn = "slt ";
3: mn = "sltu ";
4: mn = "xor ";
5: mn = opcode[30]? "sra ":"srl ";
6: mn = "or ";
7: mn = "and ";
endcase
return $sformatf("%s%s,%s,%s", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], abi_reg[opcode[24:20]]);
endfunction
function string dasm32_fence( input[31:0] opcode);
return opcode[12] ? ".i" : "";
endfunction
function string dasm32_e(input[31:0] opcode);
if(opcode[31:7] == 0) return "ecall";
else if({opcode[31:21],opcode [19:7]} == 0) return "ebreak";
else
case(opcode[14:12])
1: return {"csrrw ", dasm32_csr(opcode)};
2: return {"csrrs ", dasm32_csr(opcode)};
3: return {"csrrc ", dasm32_csr(opcode)};
5: return {"csrrwi ", dasm32_csr(opcode, 1)};
6: return {"csrrsi ", dasm32_csr(opcode, 1)};
7: return {"csrrci ", dasm32_csr(opcode, 1)};
endcase
endfunction
function string dasm32_csr(input[31:0] opcode, input im=0);
bit[11:0] csr;
csr = opcode[31:20];
if(im) begin
return $sformatf("%s,csr_%0h,0x%h", abi_reg[opcode[11:7]], csr, opcode[19:15]);
end
else begin
return $sformatf("%s,csr_%0h,%s", abi_reg[opcode[11:7]], csr, abi_reg[opcode[19:15]]);
end
endfunction
//atomics
function string dasm32_a(input[31:0] opcode, input tid=0);
case(opcode[31:27])
'b00010: return $sformatf("lr.w %s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
'b00011: return $sformatf("sc.w %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
'b00001: return {"amoswap.w", dasm32_amo(opcode, tid)};
'b00000: return {"amoadd.w", dasm32_amo(opcode, tid)};
'b00100: return {"amoxor.w", dasm32_amo(opcode, tid)};
'b01100: return {"amoand.w", dasm32_amo(opcode, tid)};
'b01000: return {"amoor.w", dasm32_amo(opcode, tid)};
'b10000: return {"amomin.w", dasm32_amo(opcode, tid)};
'b10100: return {"amomax.w", dasm32_amo(opcode, tid)};
'b11000: return {"amominu.w", dasm32_amo(opcode, tid)};
'b11100: return {"amomaxu.w", dasm32_amo(opcode, tid)};
endcase
return $sformatf(".long 0x%h", opcode);
endfunction
function string dasm32_amo( input[31:0] opcode, input tid=0);
return $sformatf(" %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
endfunction

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soc/dpi/common/tcp_server.c Normal file
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "tcp_server.h"
#include <assert.h>
#include <errno.h>
#include <fcntl.h>
#include <netinet/in.h>
#include <netinet/tcp.h>
#include <pthread.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <sys/time.h>
#include <sys/types.h>
#include <unistd.h>
/**
* Simple buffer for passing data between TCP sockets and DPI modules
*/
const int BUFSIZE_BYTE = 25600;
struct tcp_buf {
unsigned int rptr;
unsigned int wptr;
char buf[BUFSIZE_BYTE];
};
/**
* TCP Server thread context structure
*/
struct tcp_server_ctx {
// Writeable by the host thread
char *display_name;
uint16_t listen_port;
volatile bool socket_run;
// Writeable by the server thread
tcp_buf *buf_in;
tcp_buf *buf_out;
int sfd; // socket fd
int cfd; // client fd
pthread_t sock_thread;
};
static bool tcp_buffer_is_full(struct tcp_buf *buf) {
if (buf->wptr >= buf->rptr) {
return (buf->wptr - buf->rptr) == (BUFSIZE_BYTE - 1);
} else {
return (buf->rptr - buf->wptr) == 1;
}
}
static bool tcp_buffer_is_empty(struct tcp_buf *buf) {
return (buf->wptr == buf->rptr);
}
static void tcp_buffer_put_byte(struct tcp_buf *buf, char dat) {
bool done = false;
while (!done) {
if (!tcp_buffer_is_full(buf)) {
buf->buf[buf->wptr++] = dat;
buf->wptr %= BUFSIZE_BYTE;
done = true;
}
}
}
static bool tcp_buffer_get_byte(struct tcp_buf *buf, char *dat) {
if (tcp_buffer_is_empty(buf)) {
return false;
}
*dat = buf->buf[buf->rptr++];
buf->rptr %= BUFSIZE_BYTE;
return true;
}
static struct tcp_buf *tcp_buffer_new(void) {
struct tcp_buf *buf_new;
buf_new = (struct tcp_buf *)malloc(sizeof(struct tcp_buf));
buf_new->rptr = 0;
buf_new->wptr = 0;
return buf_new;
}
static void tcp_buffer_free(struct tcp_buf **buf) {
free(*buf);
*buf = NULL;
}
/**
* Start a TCP server
*
* This function creates attempts to create a new TCP socket instance. The
* socket is a non-blocking stream socket, with buffering disabled.
*
* @param ctx context object
* @return 0 on success, -1 in case of an error
*/
static int start(struct tcp_server_ctx *ctx) {
int rv;
assert(ctx->sfd == 0 && "Server already started.");
// create socket
int sfd = socket(AF_INET, SOCK_STREAM, 0);
if (sfd == -1) {
fprintf(stderr, "%s: Unable to create socket: %s (%d)\n", ctx->display_name,
strerror(errno), errno);
return -1;
}
rv = fcntl(sfd, F_SETFL, O_NONBLOCK);
if (rv != 0) {
fprintf(stderr, "%s: Unable to make socket non-blocking: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
return -1;
}
// reuse existing socket (if existing)
int reuse_socket = 1;
rv = setsockopt(sfd, SOL_SOCKET, SO_REUSEADDR, &reuse_socket, sizeof(int));
if (rv != 0) {
fprintf(stderr, "%s: Unable to set socket options: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
return -1;
}
// stop tcp socket from buffering (buffering prevents timely responses to
// OpenOCD which severly limits debugging performance)
int tcp_nodelay = 1;
rv = setsockopt(sfd, IPPROTO_TCP, TCP_NODELAY, &tcp_nodelay, sizeof(int));
if (rv != 0) {
fprintf(stderr, "%s: Unable to set socket nodelay: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
return -1;
}
// bind server
struct sockaddr_in addr;
memset(&addr, 0, sizeof(addr));
addr.sin_family = AF_INET;
addr.sin_addr.s_addr = htonl(INADDR_ANY);
addr.sin_port = htons(ctx->listen_port);
rv = bind(sfd, (struct sockaddr *)&addr, sizeof(addr));
if (rv != 0) {
fprintf(stderr, "%s: Failed to bind socket: %s (%d)\n", ctx->display_name,
strerror(errno), errno);
return -1;
}
// listen for incoming connections
rv = listen(sfd, 1);
if (rv != 0) {
fprintf(stderr, "%s: Failed to listen on socket: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
return -1;
}
ctx->sfd = sfd;
assert(ctx->sfd > 0);
return 0;
}
/**
* Accept an incoming connection from a client (nonblocking)
*
* The resulting client fd is made non-blocking.
*
* @param ctx context object
* @return 0 on success, any other value indicates an error
*/
static int client_tryaccept(struct tcp_server_ctx *ctx) {
int rv;
assert(ctx->sfd > 0);
assert(ctx->cfd == 0);
int cfd = accept(ctx->sfd, NULL, NULL);
if (cfd == -1 && errno == EAGAIN) {
return -EAGAIN;
}
if (cfd == -1) {
fprintf(stderr, "%s: Unable to accept incoming connection: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
return -1;
}
rv = fcntl(cfd, F_SETFL, O_NONBLOCK);
if (rv != 0) {
fprintf(stderr, "%s: Unable to make client socket non-blocking: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
return -1;
}
ctx->cfd = cfd;
assert(ctx->cfd > 0);
printf("%s: Accepted client connection\n", ctx->display_name);
return 0;
}
/**
* Stop the TCP server
*
* @param ctx context object
*/
static void stop(struct tcp_server_ctx *ctx) {
assert(ctx);
if (!ctx->sfd) {
return;
}
close(ctx->sfd);
ctx->sfd = 0;
}
/**
* Receive a byte from a connected client
*
* @param ctx context object
* @param cmd byte received
* @return true if a byte was read
*/
static bool get_byte(struct tcp_server_ctx *ctx, char *cmd) {
assert(ctx);
ssize_t num_read = read(ctx->cfd, cmd, 1);
if (num_read == 0) {
return false;
}
if (num_read == -1) {
if (errno == EAGAIN || errno == EWOULDBLOCK) {
return false;
} else if (errno == EBADF) {
// Possibly client went away? Accept a new connection.
fprintf(stderr, "%s: Client disappeared.\n", ctx->display_name);
tcp_server_client_close(ctx);
return false;
} else {
fprintf(stderr, "%s: Error while reading from client: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
assert(0 && "Error reading from client");
}
}
assert(num_read == 1);
return true;
}
/**
* Send a byte to a connected client
*
* @param ctx context object
* @param cmd byte to send
*/
static void put_byte(struct tcp_server_ctx *ctx, char cmd) {
while (1) {
ssize_t num_written = send(ctx->cfd, &cmd, sizeof(cmd), MSG_NOSIGNAL);
if (num_written == -1) {
if (errno == EAGAIN || errno == EWOULDBLOCK) {
continue;
} else if (errno == EPIPE) {
printf("%s: Remote disconnected.\n", ctx->display_name);
tcp_server_client_close(ctx);
break;
} else {
fprintf(stderr, "%s: Error while writing to client: %s (%d)\n",
ctx->display_name, strerror(errno), errno);
assert(0 && "Error writing to client.");
}
}
if (num_written >= 1) {
break;
}
}
}
/**
* Cleanup server context
*
* @param ctx context object
*/
static void ctx_free(struct tcp_server_ctx *ctx) {
// Free the buffers
tcp_buffer_free(&ctx->buf_in);
tcp_buffer_free(&ctx->buf_out);
// Free the display name
free(ctx->display_name);
// Free the ctx
free(ctx);
ctx = NULL;
}
/**
* Thread function to create a new server instance
*
* @param ctx_void context object
* @return Always returns NULL
*/
static void *server_create(void *ctx_void) {
// Cast to a server struct
struct tcp_server_ctx *ctx = (struct tcp_server_ctx *)ctx_void;
struct timeval timeout;
// Start the server
int rv = start(ctx);
if (rv != 0) {
fprintf(stderr, "%s: Unable to create TCP server on port %d\n",
ctx->display_name, ctx->listen_port);
goto err_cleanup_return;
}
// Initialise timeout
timeout.tv_sec = 0;
// Initialise fd_set
// Start waiting for connection / data
char xfer_data;
while (ctx->socket_run) {
// Initialise structure of fds
fd_set read_fds;
FD_ZERO(&read_fds);
if (ctx->sfd) {
FD_SET(ctx->sfd, &read_fds);
}
if (ctx->cfd) {
FD_SET(ctx->cfd, &read_fds);
}
// max fd num
int mfd = (ctx->cfd > ctx->sfd) ? ctx->cfd : ctx->sfd;
// Set timeout - 50us gives good performance
timeout.tv_usec = 50;
// Wait for socket activity or timeout
rv = select(mfd + 1, &read_fds, NULL, NULL, &timeout);
if (rv < 0) {
printf("%s: Socket read failed, port: %d\n", ctx->display_name,
ctx->listen_port);
tcp_server_client_close(ctx);
}
// New connection
if (FD_ISSET(ctx->sfd, &read_fds)) {
client_tryaccept(ctx);
}
// New client data
if (FD_ISSET(ctx->cfd, &read_fds)) {
while (get_byte(ctx, &xfer_data)) {
tcp_buffer_put_byte(ctx->buf_in, xfer_data);
}
}
if (ctx->cfd != 0) {
while (tcp_buffer_get_byte(ctx->buf_out, &xfer_data)) {
put_byte(ctx, xfer_data);
}
}
}
err_cleanup_return:
// Simulation done - clean up
tcp_server_client_close(ctx);
stop(ctx);
return NULL;
}
// Abstract interface functions
tcp_server_ctx *tcp_server_create(const char *display_name, int listen_port) {
struct tcp_server_ctx *ctx =
(struct tcp_server_ctx *)calloc(1, sizeof(struct tcp_server_ctx));
assert(ctx);
// Create the buffers
struct tcp_buf *buf_in = tcp_buffer_new();
struct tcp_buf *buf_out = tcp_buffer_new();
assert(buf_in);
assert(buf_out);
// Populate the struct with buffer pointers
ctx->buf_in = buf_in;
ctx->buf_out = buf_out;
// Set up socket details
ctx->socket_run = true;
ctx->listen_port = listen_port;
ctx->display_name = strdup(display_name);
assert(ctx->display_name);
if (pthread_create(&ctx->sock_thread, NULL, server_create, (void *)ctx) !=
0) {
fprintf(stderr, "%s: Unable to create TCP socket thread\n",
ctx->display_name);
ctx_free(ctx);
free(ctx);
return NULL;
}
return ctx;
}
bool tcp_server_read(struct tcp_server_ctx *ctx, char *dat) {
return tcp_buffer_get_byte(ctx->buf_in, dat);
}
void tcp_server_write(struct tcp_server_ctx *ctx, char dat) {
tcp_buffer_put_byte(ctx->buf_out, dat);
}
void tcp_server_close(struct tcp_server_ctx *ctx) {
// Shut down the socket thread
ctx->socket_run = false;
pthread_join(ctx->sock_thread, NULL);
ctx_free(ctx);
}
void tcp_server_client_close(struct tcp_server_ctx *ctx) {
assert(ctx);
if (!ctx->cfd) {
return;
}
close(ctx->cfd);
ctx->cfd = 0;
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
/**
* Functions to create and interact with a threaded TCP server
*
* This is intended to be used by simulation add-on DPI modules to provide
* basic TCP socket communication between a host and simulated peripherals.
*/
#ifndef TCP_SERVER_H_
#define TCP_SERVER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
struct tcp_server_ctx;
/**
* Non-blocking read of a byte from a connected client
*
* @param ctx tcp server context object
* @param dat byte received
* @return true if a byte was read
*/
bool tcp_server_read(struct tcp_server_ctx *ctx, char *dat);
/**
* Write a byte to a connected client
*
* The write is internally buffered and so does not block if the client is not
* ready to accept data, but does block if the buffer is full.
*
* @param ctx tcp server context object
* @param dat byte to send
*/
void tcp_server_write(struct tcp_server_ctx *ctx, char dat);
/**
* Create a new TCP server instance
*
* @param display_name C string description of server
* @param listen_port On which port the server should listen
* @return A pointer to the created context struct
*/
tcp_server_ctx *tcp_server_create(const char *display_name, int listen_port);
/**
* Shut down the server and free all reserved memory
*
* @param ctx tcp server context object
*/
void tcp_server_close(struct tcp_server_ctx *ctx);
/**
* Instruct the server to disconnect a client
*
* @param ctx tcp server context object
*/
void tcp_server_client_close(struct tcp_server_ctx *ctx);
#ifdef __cplusplus
} // extern "C"
#endif
#endif // TCP_SERVER_H_

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "jtagdpi.h"
#include <assert.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../common/tcp_server.h"
struct jtagdpi_ctx {
// Server context
struct tcp_server_ctx *sock;
// Signals
uint8_t tck;
uint8_t tms;
uint8_t tdi;
uint8_t tdo;
uint8_t trst_n;
uint8_t srst_n;
};
/**
* Reset the JTAG signals to a "dongle unplugged" state
*/
static void reset_jtag_signals(struct jtagdpi_ctx *ctx) {
assert(ctx);
ctx->tck = 0;
ctx->tms = 0;
ctx->tdi = 0;
// trst_n is pulled down (reset active) by default
ctx->trst_n = 0;
// srst_n is pulled up (reset not active) by default
ctx->srst_n = 1;
}
/**
* Update the JTAG signals in the context structure
*/
static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
assert(ctx);
/*
* Documentation pointer:
* The remote_bitbang protocol implemented below is documented in the OpenOCD
* source tree at doc/manual/jtag/drivers/remote_bitbang.txt, or online at
* https://repo.or.cz/openocd.git/blob/HEAD:/doc/manual/jtag/drivers/remote_bitbang.txt
*/
// read a command byte
char cmd;
if (!tcp_server_read(ctx->sock, &cmd)) {
return;
}
bool act_send_resp = false;
bool act_quit = false;
// parse received command byte
if (cmd >= '0' && cmd <= '7') {
// JTAG write
char cmd_bit = cmd - '0';
ctx->tdi = (cmd_bit >> 0) & 0x1;
ctx->tms = (cmd_bit >> 1) & 0x1;
ctx->tck = (cmd_bit >> 2) & 0x1;
} else if (cmd >= 'r' && cmd <= 'u') {
// JTAG reset (active high from OpenOCD)
char cmd_bit = cmd - 'r';
ctx->srst_n = !((cmd_bit >> 0) & 0x1);
ctx->trst_n = !((cmd_bit >> 1) & 0x1);
} else if (cmd == 'R') {
// JTAG read
act_send_resp = true;
} else if (cmd == 'B') {
// printf("%s: BLINK ON!\n", ctx->display_name);
} else if (cmd == 'b') {
// printf("%s: BLINK OFF!\n", ctx->display_name);
} else if (cmd == 'Q') {
// quit (client disconnect)
act_quit = true;
} else {
fprintf(stderr,
"JTAG DPI Protocol violation detected: unsupported command %c\n",
cmd);
exit(1);
}
// send tdo as response
if (act_send_resp) {
char tdo_ascii = ctx->tdo + '0';
tcp_server_write(ctx->sock, tdo_ascii);
}
if (act_quit) {
printf("JTAG DPI: Remote disconnected.\n");
tcp_server_client_close(ctx->sock);
}
}
void *jtagdpi_create(const char *display_name, int listen_port) {
struct jtagdpi_ctx *ctx =
(struct jtagdpi_ctx *)calloc(1, sizeof(struct jtagdpi_ctx));
assert(ctx);
// Create socket
ctx->sock = tcp_server_create(display_name, listen_port);
reset_jtag_signals(ctx);
printf(
"\n"
"JTAG: Virtual JTAG interface %s is listening on port %d. Use\n"
"OpenOCD and the following configuration to connect:\n"
" interface remote_bitbang\n"
" remote_bitbang_host localhost\n"
" remote_bitbang_port %d\n",
display_name, listen_port, listen_port);
return (void *)ctx;
}
void jtagdpi_close(void *ctx_void) {
struct jtagdpi_ctx *ctx = (struct jtagdpi_ctx *)ctx_void;
if (!ctx) {
return;
}
tcp_server_close(ctx->sock);
free(ctx);
}
void jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,
svBit *trst_n, svBit *srst_n, const svBit tdo) {
struct jtagdpi_ctx *ctx = (struct jtagdpi_ctx *)ctx_void;
ctx->tdo = tdo;
// TODO: Evaluate moving this functionality into a separate thread
if (ctx) {
update_jtag_signals(ctx);
}
*tdi = ctx->tdi;
*tms = ctx->tms;
*tck = ctx->tck;
*srst_n = ctx->srst_n;
*trst_n = ctx->trst_n;
}

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef JTAGDPI_H_
#define JTAGDPI_H_
#include <svdpi.h>
#ifdef __cplusplus
extern "C" {
#endif
struct jtagdpi_ctx;
/**
* Constructor: Create and initialize jtagdpi context object
*
* Call from a initial block.
*
* @param display_name Name of the JTAG interface (for display purposes only)
* @param listen_port Port to listen on
* @return an initialized struct jtagdpi_ctx context object
*/
void *jtagdpi_create(const char *display_name, int listen_port);
/**
* Destructor: Close all connections and free all resources
*
* Call from a finish block.
*
* @param ctx_void a struct jtagdpi_ctx context object
*/
void jtagdpi_close(void *ctx_void);
/**
* Drive JTAG signals
*
* Call this function from the simulation at every clock tick to read/write
* from/to the JTAG signals.
*
* @param ctx_void a struct jtagdpi_ctx context object
* @param tck JTAG test clock signal
* @param tms JTAG test mode select signal
* @param tdi JTAG test data input signal
* @param trst_n JTAG test reset signal (active low)
* @param srst_n JTAG system reset signal (active low)
* @param tdo JTAG test data out
*/
void jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,
svBit *trst_n, svBit *srst_n, const svBit tdo);
#ifdef __cplusplus
} // extern "C"
#endif
#endif // JTAGDPI_H_

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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module jtagdpi #(
parameter string Name = "jtag0", // name of the JTAG interface (display only)
parameter int ListenPort = 44853 // TCP port to listen on
) (
input logic clk_i,
input logic rst_ni,
output logic jtag_tck,
output logic jtag_tms,
output logic jtag_tdi,
input logic jtag_tdo,
output logic jtag_trst_n,
output logic jtag_srst_n
);
import "DPI-C" function chandle jtagdpi_create(
input string name,
input int listen_port
);
import "DPI-C" function void jtagdpi_tick(
input chandle ctx,
output bit tck,
output bit tms,
output bit tdi,
output bit trst_n,
output bit srst_n,
input bit tdo
);
import "DPI-C" function void jtagdpi_close(input chandle ctx);
chandle ctx;
initial begin
ctx = jtagdpi_create(Name, ListenPort);
end
final begin
jtagdpi_close(ctx);
ctx = 0;
end
reg [1:0] plit;
always_ff @(posedge clk_i) plit <= plit + 1'b1;
always_ff @(posedge plit[1], negedge rst_ni) begin
jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
jtag_tdo);
end
endmodule

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-I../design/include
-I./
-CFLAGS -lpthread
-LDFLAGS -lpthread
./dpi/common/tcp_server.c
./dpi/jtagdpi/jtagdpi.sv
./dpi/jtagdpi/jtagdpi.c

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
module soc_sim (
input bit core_clk
);
logic rst_l;
logic dbg_rst_l;
wire jtag_tdo;
wire jtag_tck;
wire jtag_tms;
wire jtag_tdi;
wire jtag_trst_n;
bit [31:0] cycleCnt;
logic mailbox_data_val;
int commit_count;
logic wb_valid;
logic [ 4:0] wb_dest;
logic [31:0] wb_data;
wire [63:0] WriteData;
string abi_reg [32]; // ABI register names
assign WriteData = rvsoc.lsu_axi_wdata;
assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
parameter MAILBOX_ADDR = 32'hD0580000;
logic write;
logic [31:0] laddr;
wire mailbox_write = rvsoc.lmem_axi_awvalid && rvsoc.lsu_axi_awaddr == MAILBOX_ADDR && rst_l;
always @(posedge core_clk or negedge rst_l) begin
if (~rst_l) begin
laddr <= 32'b0;
write <= 1'b0;
end else begin
if (rvsoc.lsu_hready) begin
laddr <= rvsoc.lsu_haddr;
write <= rvsoc.lsu_hwrite & |rvsoc.lsu_htrans;
end
end
end
parameter MAX_CYCLES = 10_000_000_0;
integer fd, tp, el;
/* verilator lint_off WIDTH */
/* verilator lint_off CASEINCOMPLETE */
`include "dasm.svi"
/* verilator lint_on CASEINCOMPLETE */
/* verilator lint_on WIDTH */
always @(posedge core_clk) begin
cycleCnt <= cycleCnt + 1;
if (cycleCnt == MAX_CYCLES) begin
$display("Hit max cycle count (%0d) .. stopping", cycleCnt);
$finish;
end
if (mailbox_data_val & mailbox_write) begin
$fwrite(fd, "%c", WriteData[7:0]);
$write("%c", WriteData[7:0]);
end
if (mailbox_write && WriteData[7:0] == 8'hff) begin
$display("\nFinished : minstret = %0d, mcycle = %0d",
rvsoc.rvtop.swerv.dec.tlu.minstretl[31:0],
rvsoc.rvtop.swerv.dec.tlu.mcyclel[31:0]);
$display(
"See \"exec.log\" for execution trace with register updates..\n");
$display("TEST_PASSED");
$finish;
end else if (mailbox_write && WriteData[7:0] == 8'h1) begin
$display("TEST_FAILED");
$finish;
end
end
// trace monitor
always @(posedge core_clk) begin
wb_valid <= rvsoc.rvtop.swerv.dec.dec_i0_wen_r;
wb_dest <= rvsoc.rvtop.swerv.dec.dec_i0_waddr_r;
wb_data <= rvsoc.rvtop.swerv.dec.dec_i0_wdata_r;
if (rvsoc.trace_rv_i_valid_ip) begin
$fwrite(tp, "%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvsoc.trace_rv_i_valid_ip,
0, rvsoc.trace_rv_i_address_ip, 0, rvsoc.trace_rv_i_insn_ip,
rvsoc.trace_rv_i_exception_ip, rvsoc.trace_rv_i_ecause_ip,
rvsoc.trace_rv_i_tval_ip, rvsoc.trace_rv_i_interrupt_ip);
// Basic trace - no exception register updates
// #1 0 ee000000 b0201073 c 0b02 00000000
commit_count++;
$fwrite(el, "%10d : %8s 0 %h %h%13s ; %s\n", cycleCnt, $sformatf(
"#%0d", commit_count), rvsoc.trace_rv_i_address_ip,
rvsoc.trace_rv_i_insn_ip, (wb_dest != 0 && wb_valid) ? $sformatf(
"%s=%h", abi_reg[wb_dest], wb_data) : " ", dasm(
rvsoc.trace_rv_i_insn_ip,
rvsoc.trace_rv_i_address_ip,
wb_dest & {5{wb_valid}},
wb_data
));
end
if (rvsoc.rvtop.swerv.dec.dec_nonblock_load_wen) begin
$fwrite(el, "%10d : %32s=%h ; nbL\n", cycleCnt,
abi_reg[rvsoc.rvtop.swerv.dec.dec_nonblock_load_waddr],
rvsoc.rvtop.swerv.dec.lsu_nonblock_load_data);
soc_sim.gpr[0][rvsoc.rvtop.swerv.dec.dec_nonblock_load_waddr] = rvsoc.rvtop.swerv.dec.lsu_nonblock_load_data;
end
if (rvsoc.rvtop.swerv.dec.exu_div_wren) begin
$fwrite(el, "%10d : %32s=%h ; nbD\n", cycleCnt,
abi_reg[rvsoc.rvtop.swerv.dec.div_waddr_wb],
rvsoc.rvtop.swerv.dec.exu_div_result);
soc_sim.gpr[0][rvsoc.rvtop.swerv.dec.div_waddr_wb] = rvsoc.rvtop.swerv.dec.exu_div_result;
end
end
initial begin
abi_reg[0] = "zero";
abi_reg[1] = "ra";
abi_reg[2] = "sp";
abi_reg[3] = "gp";
abi_reg[4] = "tp";
abi_reg[5] = "t0";
abi_reg[6] = "t1";
abi_reg[7] = "t2";
abi_reg[8] = "s0";
abi_reg[9] = "s1";
abi_reg[10] = "a0";
abi_reg[11] = "a1";
abi_reg[12] = "a2";
abi_reg[13] = "a3";
abi_reg[14] = "a4";
abi_reg[15] = "a5";
abi_reg[16] = "a6";
abi_reg[17] = "a7";
abi_reg[18] = "s2";
abi_reg[19] = "s3";
abi_reg[20] = "s4";
abi_reg[21] = "s5";
abi_reg[22] = "s6";
abi_reg[23] = "s7";
abi_reg[24] = "s8";
abi_reg[25] = "s9";
abi_reg[26] = "s10";
abi_reg[27] = "s11";
abi_reg[28] = "t3";
abi_reg[29] = "t4";
abi_reg[30] = "t5";
abi_reg[31] = "t6";
tp = $fopen("trace_port.csv", "w");
el = $fopen("exec.log", "w");
$fwrite(el, "//Cycle : #inst 0 pc opcode reg regnum value\n");
fd = $fopen("console.log", "w");
commit_count = 0;
end
assign rst_l = cycleCnt > 20;
assign dbg_rst_l = cycleCnt > 10;
soc_top rvsoc (
.clk(core_clk),
.rst(rst_l),
.dbg_rst(dbg_rst_l),
.jtag_tdo(jtag_tdo),
.jtag_tck(jtag_tck),
.jtag_tms(jtag_tms),
.jtag_tdi(jtag_tdi),
.jtag_trst_n(jtag_trst_n)
);
jtagdpi jtagdpi (
.clk_i (core_clk),
.rst_ni(rst_l),
.jtag_tck(jtag_tck),
.jtag_tms(jtag_tms),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
.jtag_trst_n(jtag_trst_n),
.jtag_srst_n()
);
`define DRAM(bank) \
rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
`define ICCM_PATH `RV_TOP.mem.iccm
`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
endmodule

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../design/include/el2_def.sv
../design/el2_swerv_wrapper.sv
../design/el2_mem.sv
../design/el2_pic_ctrl.sv
../design/el2_swerv.sv
../design/el2_dma_ctrl.sv
../design/ifu/el2_ifu_aln_ctl.sv
../design/ifu/el2_ifu_compress_ctl.sv
../design/ifu/el2_ifu_ifc_ctl.sv
../design/ifu/el2_ifu_bp_ctl.sv
../design/ifu/el2_ifu_ic_mem.sv
../design/ifu/el2_ifu_mem_ctl.sv
../design/ifu/el2_ifu_iccm_mem.sv
../design/ifu/el2_ifu.sv
../design/dec/el2_dec_decode_ctl.sv
../design/dec/el2_dec_gpr_ctl.sv
../design/dec/el2_dec_ib_ctl.sv
../design/dec/el2_dec_tlu_ctl.sv
../design/dec/el2_dec_trigger.sv
../design/dec/el2_dec.sv
../design/exu/el2_exu_alu_ctl.sv
../design/exu/el2_exu_mul_ctl.sv
../design/exu/el2_exu_div_ctl.sv
../design/exu/el2_exu.sv
../design/lsu/el2_lsu.sv
../design/lsu/el2_lsu_clkdomain.sv
../design/lsu/el2_lsu_addrcheck.sv
../design/lsu/el2_lsu_lsc_ctl.sv
../design/lsu/el2_lsu_stbuf.sv
../design/lsu/el2_lsu_bus_buffer.sv
../design/lsu/el2_lsu_bus_intf.sv
../design/lsu/el2_lsu_ecc.sv
../design/lsu/el2_lsu_dccm_mem.sv
../design/lsu/el2_lsu_dccm_ctl.sv
../design/lsu/el2_lsu_trigger.sv
../design/dbg/el2_dbg.sv
../design/dmi/dmi_wrapper.v
../design/dmi/dmi_jtag_to_core_sync.v
../design/dmi/rvjtag_tap.v
../design/lib/el2_lib.sv
../design/lib/beh_lib.sv
../design/lib/mem_lib.sv
../design/lib/ahb_to_axi4.sv
../design/lib/axi4_to_ahb.sv
./ahb_sif.sv
./axi_lsu_dma_bridge.sv
./soc_top.sv

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soc/soc_top.sv Normal file
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module soc_top (
input clk,
input dbg_rst,
input rst,
output jtag_tdo,
input jtag_tck,
input jtag_tms,
input jtag_tdi,
input jtag_trst_n
);
logic nmi_int;
logic [ 31:0] reset_vector;
logic [ 31:0] nmi_vector;
logic [ 31:1] jtag_id;
logic [ 31:0] ic_haddr;
logic [ 2:0] ic_hburst;
logic ic_hmastlock;
logic [ 3:0] ic_hprot;
logic [ 2:0] ic_hsize;
logic [ 1:0] ic_htrans;
logic ic_hwrite;
logic [ 63:0] ic_hrdata;
logic ic_hready;
logic ic_hresp;
logic [ 31:0] lsu_haddr;
logic [ 2:0] lsu_hburst;
logic lsu_hmastlock;
logic [ 3:0] lsu_hprot;
logic [ 2:0] lsu_hsize;
logic [ 1:0] lsu_htrans;
logic lsu_hwrite;
logic [ 63:0] lsu_hrdata;
logic [ 63:0] lsu_hwdata;
logic lsu_hready;
logic lsu_hresp;
logic [ 31:0] sb_haddr;
logic [ 2:0] sb_hburst;
logic sb_hmastlock;
logic [ 3:0] sb_hprot;
logic [ 2:0] sb_hsize;
logic [ 1:0] sb_htrans;
logic sb_hwrite;
logic [ 63:0] sb_hrdata;
logic [ 63:0] sb_hwdata;
logic sb_hready;
logic sb_hresp;
logic [ 63:0] trace_rv_i_insn_ip;
logic [ 63:0] trace_rv_i_address_ip;
logic [ 2:0] trace_rv_i_valid_ip;
logic [ 2:0] trace_rv_i_exception_ip;
logic [ 4:0] trace_rv_i_ecause_ip;
logic [ 2:0] trace_rv_i_interrupt_ip;
logic [ 31:0] trace_rv_i_tval_ip;
logic o_debug_mode_status;
logic [ 1:0] dec_tlu_perfcnt0;
logic [ 1:0] dec_tlu_perfcnt1;
logic [ 1:0] dec_tlu_perfcnt2;
logic [ 1:0] dec_tlu_perfcnt3;
logic o_cpu_halt_ack;
logic o_cpu_halt_status;
logic o_cpu_run_ack;
logic mailbox_write;
logic [ 63:0] dma_hrdata;
logic [ 63:0] dma_hwdata;
logic dma_hready;
logic dma_hresp;
logic mpc_debug_halt_req;
logic mpc_debug_run_req;
logic mpc_reset_run_req;
logic mpc_debug_halt_ack;
logic mpc_debug_run_ack;
logic debug_brkpt_status;
wire dma_hready_out;
//-------------------------- LSU AXI signals--------------------------
// AXI Write Channels
wire lsu_axi_awvalid;
wire lsu_axi_awready;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;
wire [ 31:0] lsu_axi_awaddr;
wire [ 3:0] lsu_axi_awregion;
wire [ 7:0] lsu_axi_awlen;
wire [ 2:0] lsu_axi_awsize;
wire [ 1:0] lsu_axi_awburst;
wire lsu_axi_awlock;
wire [ 3:0] lsu_axi_awcache;
wire [ 2:0] lsu_axi_awprot;
wire [ 3:0] lsu_axi_awqos;
wire lsu_axi_wvalid;
wire lsu_axi_wready;
wire [ 63:0] lsu_axi_wdata;
wire [ 7:0] lsu_axi_wstrb;
wire lsu_axi_wlast;
wire lsu_axi_bvalid;
wire lsu_axi_bready;
wire [ 1:0] lsu_axi_bresp;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;
// AXI Read Channels
wire lsu_axi_arvalid;
wire lsu_axi_arready;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;
wire [ 31:0] lsu_axi_araddr;
wire [ 3:0] lsu_axi_arregion;
wire [ 7:0] lsu_axi_arlen;
wire [ 2:0] lsu_axi_arsize;
wire [ 1:0] lsu_axi_arburst;
wire lsu_axi_arlock;
wire [ 3:0] lsu_axi_arcache;
wire [ 2:0] lsu_axi_arprot;
wire [ 3:0] lsu_axi_arqos;
wire lsu_axi_rvalid;
wire lsu_axi_rready;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;
wire [ 63:0] lsu_axi_rdata;
wire [ 1:0] lsu_axi_rresp;
wire lsu_axi_rlast;
//-------------------------- IFU AXI signals--------------------------
// AXI Write Channels
wire ifu_axi_awvalid;
wire ifu_axi_awready;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;
wire [ 31:0] ifu_axi_awaddr;
wire [ 3:0] ifu_axi_awregion;
wire [ 7:0] ifu_axi_awlen;
wire [ 2:0] ifu_axi_awsize;
wire [ 1:0] ifu_axi_awburst;
wire ifu_axi_awlock;
wire [ 3:0] ifu_axi_awcache;
wire [ 2:0] ifu_axi_awprot;
wire [ 3:0] ifu_axi_awqos;
wire ifu_axi_wvalid;
wire ifu_axi_wready;
wire [ 63:0] ifu_axi_wdata;
wire [ 7:0] ifu_axi_wstrb;
wire ifu_axi_wlast;
wire ifu_axi_bvalid;
wire ifu_axi_bready;
wire [ 1:0] ifu_axi_bresp;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;
// AXI Read Channels
wire ifu_axi_arvalid;
wire ifu_axi_arready;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;
wire [ 31:0] ifu_axi_araddr;
wire [ 3:0] ifu_axi_arregion;
wire [ 7:0] ifu_axi_arlen;
wire [ 2:0] ifu_axi_arsize;
wire [ 1:0] ifu_axi_arburst;
wire ifu_axi_arlock;
wire [ 3:0] ifu_axi_arcache;
wire [ 2:0] ifu_axi_arprot;
wire [ 3:0] ifu_axi_arqos;
wire ifu_axi_rvalid;
wire ifu_axi_rready;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;
wire [ 63:0] ifu_axi_rdata;
wire [ 1:0] ifu_axi_rresp;
wire ifu_axi_rlast;
//-------------------------- SB AXI signals--------------------------
// AXI Write Channels
wire sb_axi_awvalid;
wire sb_axi_awready;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_awid;
wire [ 31:0] sb_axi_awaddr;
wire [ 3:0] sb_axi_awregion;
wire [ 7:0] sb_axi_awlen;
wire [ 2:0] sb_axi_awsize;
wire [ 1:0] sb_axi_awburst;
wire sb_axi_awlock;
wire [ 3:0] sb_axi_awcache;
wire [ 2:0] sb_axi_awprot;
wire [ 3:0] sb_axi_awqos;
wire sb_axi_wvalid;
wire sb_axi_wready;
wire [ 63:0] sb_axi_wdata;
wire [ 7:0] sb_axi_wstrb;
wire sb_axi_wlast;
wire sb_axi_bvalid;
wire sb_axi_bready;
wire [ 1:0] sb_axi_bresp;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_bid;
// AXI Read Channels
wire sb_axi_arvalid;
wire sb_axi_arready;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_arid;
wire [ 31:0] sb_axi_araddr;
wire [ 3:0] sb_axi_arregion;
wire [ 7:0] sb_axi_arlen;
wire [ 2:0] sb_axi_arsize;
wire [ 1:0] sb_axi_arburst;
wire sb_axi_arlock;
wire [ 3:0] sb_axi_arcache;
wire [ 2:0] sb_axi_arprot;
wire [ 3:0] sb_axi_arqos;
wire sb_axi_rvalid;
wire sb_axi_rready;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_rid;
wire [ 63:0] sb_axi_rdata;
wire [ 1:0] sb_axi_rresp;
wire sb_axi_rlast;
//-------------------------- DMA AXI signals--------------------------
// AXI Write Channels
wire dma_axi_awvalid;
wire dma_axi_awready;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;
wire [ 31:0] dma_axi_awaddr;
wire [ 2:0] dma_axi_awsize;
wire [ 2:0] dma_axi_awprot;
wire [ 7:0] dma_axi_awlen;
wire [ 1:0] dma_axi_awburst;
wire dma_axi_wvalid;
wire dma_axi_wready;
wire [ 63:0] dma_axi_wdata;
wire [ 7:0] dma_axi_wstrb;
wire dma_axi_wlast;
wire dma_axi_bvalid;
wire dma_axi_bready;
wire [ 1:0] dma_axi_bresp;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;
// AXI Read Channels
wire dma_axi_arvalid;
wire dma_axi_arready;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;
wire [ 31:0] dma_axi_araddr;
wire [ 2:0] dma_axi_arsize;
wire [ 2:0] dma_axi_arprot;
wire [ 7:0] dma_axi_arlen;
wire [ 1:0] dma_axi_arburst;
wire dma_axi_rvalid;
wire dma_axi_rready;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;
wire [ 63:0] dma_axi_rdata;
wire [ 1:0] dma_axi_rresp;
wire dma_axi_rlast;
wire lmem_axi_arvalid;
wire lmem_axi_arready;
wire lmem_axi_rvalid;
wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_rid;
wire [ 1:0] lmem_axi_rresp;
wire [ 63:0] lmem_axi_rdata;
wire lmem_axi_rlast;
wire lmem_axi_rready;
wire lmem_axi_awvalid;
wire lmem_axi_awready;
wire lmem_axi_wvalid;
wire lmem_axi_wready;
wire [ 1:0] lmem_axi_bresp;
wire lmem_axi_bvalid;
wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_bid;
wire lmem_axi_bready;
initial begin
jtag_id[31:28] = 4'b1;
jtag_id[27:12] = '0;
jtag_id[11:1] = 11'h45;
reset_vector = `RV_RESET_VEC;
nmi_vector = 32'hee000000;
nmi_int = 0;
$readmemh("program.hex", lmem.mem);
$readmemh("program.hex", imem.mem);
end
el2_swerv_wrapper rvtop (
.rst_l (rst),
.dbg_rst_l(dbg_rst),
.clk (clk),
.rst_vec (reset_vector[31:1]),
.nmi_int (nmi_int),
.nmi_vec (nmi_vector[31:1]),
.jtag_id (jtag_id[31:1]),
//-------------------------- LSU AXI signals--------------------------
// AXI Write Channels
.lsu_axi_awvalid (lsu_axi_awvalid),
.lsu_axi_awready (lsu_axi_awready),
.lsu_axi_awid (lsu_axi_awid),
.lsu_axi_awaddr (lsu_axi_awaddr),
.lsu_axi_awregion(lsu_axi_awregion),
.lsu_axi_awlen (lsu_axi_awlen),
.lsu_axi_awsize (lsu_axi_awsize),
.lsu_axi_awburst (lsu_axi_awburst),
.lsu_axi_awlock (lsu_axi_awlock),
.lsu_axi_awcache (lsu_axi_awcache),
.lsu_axi_awprot (lsu_axi_awprot),
.lsu_axi_awqos (lsu_axi_awqos),
.lsu_axi_wvalid(lsu_axi_wvalid),
.lsu_axi_wready(lsu_axi_wready),
.lsu_axi_wdata (lsu_axi_wdata),
.lsu_axi_wstrb (lsu_axi_wstrb),
.lsu_axi_wlast (lsu_axi_wlast),
.lsu_axi_bvalid(lsu_axi_bvalid),
.lsu_axi_bready(lsu_axi_bready),
.lsu_axi_bresp (lsu_axi_bresp),
.lsu_axi_bid (lsu_axi_bid),
.lsu_axi_arvalid (lsu_axi_arvalid),
.lsu_axi_arready (lsu_axi_arready),
.lsu_axi_arid (lsu_axi_arid),
.lsu_axi_araddr (lsu_axi_araddr),
.lsu_axi_arregion(lsu_axi_arregion),
.lsu_axi_arlen (lsu_axi_arlen),
.lsu_axi_arsize (lsu_axi_arsize),
.lsu_axi_arburst (lsu_axi_arburst),
.lsu_axi_arlock (lsu_axi_arlock),
.lsu_axi_arcache (lsu_axi_arcache),
.lsu_axi_arprot (lsu_axi_arprot),
.lsu_axi_arqos (lsu_axi_arqos),
.lsu_axi_rvalid(lsu_axi_rvalid),
.lsu_axi_rready(lsu_axi_rready),
.lsu_axi_rid (lsu_axi_rid),
.lsu_axi_rdata (lsu_axi_rdata),
.lsu_axi_rresp (lsu_axi_rresp),
.lsu_axi_rlast (lsu_axi_rlast),
//-------------------------- IFU AXI signals--------------------------
// AXI Write Channels
.ifu_axi_awvalid (ifu_axi_awvalid),
.ifu_axi_awready (ifu_axi_awready),
.ifu_axi_awid (ifu_axi_awid),
.ifu_axi_awaddr (ifu_axi_awaddr),
.ifu_axi_awregion(ifu_axi_awregion),
.ifu_axi_awlen (ifu_axi_awlen),
.ifu_axi_awsize (ifu_axi_awsize),
.ifu_axi_awburst (ifu_axi_awburst),
.ifu_axi_awlock (ifu_axi_awlock),
.ifu_axi_awcache (ifu_axi_awcache),
.ifu_axi_awprot (ifu_axi_awprot),
.ifu_axi_awqos (ifu_axi_awqos),
.ifu_axi_wvalid(ifu_axi_wvalid),
.ifu_axi_wready(ifu_axi_wready),
.ifu_axi_wdata (ifu_axi_wdata),
.ifu_axi_wstrb (ifu_axi_wstrb),
.ifu_axi_wlast (ifu_axi_wlast),
.ifu_axi_bvalid(ifu_axi_bvalid),
.ifu_axi_bready(ifu_axi_bready),
.ifu_axi_bresp (ifu_axi_bresp),
.ifu_axi_bid (ifu_axi_bid),
.ifu_axi_arvalid (ifu_axi_arvalid),
.ifu_axi_arready (ifu_axi_arready),
.ifu_axi_arid (ifu_axi_arid),
.ifu_axi_araddr (ifu_axi_araddr),
.ifu_axi_arregion(ifu_axi_arregion),
.ifu_axi_arlen (ifu_axi_arlen),
.ifu_axi_arsize (ifu_axi_arsize),
.ifu_axi_arburst (ifu_axi_arburst),
.ifu_axi_arlock (ifu_axi_arlock),
.ifu_axi_arcache (ifu_axi_arcache),
.ifu_axi_arprot (ifu_axi_arprot),
.ifu_axi_arqos (ifu_axi_arqos),
.ifu_axi_rvalid(ifu_axi_rvalid),
.ifu_axi_rready(ifu_axi_rready),
.ifu_axi_rid (ifu_axi_rid),
.ifu_axi_rdata (ifu_axi_rdata),
.ifu_axi_rresp (ifu_axi_rresp),
.ifu_axi_rlast (ifu_axi_rlast),
//-------------------------- SB AXI signals--------------------------
// AXI Write Channels
.sb_axi_awvalid (sb_axi_awvalid),
.sb_axi_awready (sb_axi_awready),
.sb_axi_awid (sb_axi_awid),
.sb_axi_awaddr (sb_axi_awaddr),
.sb_axi_awregion(sb_axi_awregion),
.sb_axi_awlen (sb_axi_awlen),
.sb_axi_awsize (sb_axi_awsize),
.sb_axi_awburst (sb_axi_awburst),
.sb_axi_awlock (sb_axi_awlock),
.sb_axi_awcache (sb_axi_awcache),
.sb_axi_awprot (sb_axi_awprot),
.sb_axi_awqos (sb_axi_awqos),
.sb_axi_wvalid(sb_axi_wvalid),
.sb_axi_wready(sb_axi_wready),
.sb_axi_wdata (sb_axi_wdata),
.sb_axi_wstrb (sb_axi_wstrb),
.sb_axi_wlast (sb_axi_wlast),
.sb_axi_bvalid(sb_axi_bvalid),
.sb_axi_bready(sb_axi_bready),
.sb_axi_bresp (sb_axi_bresp),
.sb_axi_bid (sb_axi_bid),
.sb_axi_arvalid (sb_axi_arvalid),
.sb_axi_arready (sb_axi_arready),
.sb_axi_arid (sb_axi_arid),
.sb_axi_araddr (sb_axi_araddr),
.sb_axi_arregion(sb_axi_arregion),
.sb_axi_arlen (sb_axi_arlen),
.sb_axi_arsize (sb_axi_arsize),
.sb_axi_arburst (sb_axi_arburst),
.sb_axi_arlock (sb_axi_arlock),
.sb_axi_arcache (sb_axi_arcache),
.sb_axi_arprot (sb_axi_arprot),
.sb_axi_arqos (sb_axi_arqos),
.sb_axi_rvalid(sb_axi_rvalid),
.sb_axi_rready(sb_axi_rready),
.sb_axi_rid (sb_axi_rid),
.sb_axi_rdata (sb_axi_rdata),
.sb_axi_rresp (sb_axi_rresp),
.sb_axi_rlast (sb_axi_rlast),
//-------------------------- DMA AXI signals--------------------------
// AXI Write Channels
.dma_axi_awvalid(dma_axi_awvalid),
.dma_axi_awready(dma_axi_awready),
.dma_axi_awid ('0), // ids are not used on DMA since it always responses in order
.dma_axi_awaddr(lsu_axi_awaddr),
.dma_axi_awsize(lsu_axi_awsize),
.dma_axi_awprot('0),
.dma_axi_awlen('0),
.dma_axi_awburst('0),
.dma_axi_wvalid(dma_axi_wvalid),
.dma_axi_wready(dma_axi_wready),
.dma_axi_wdata (lsu_axi_wdata),
.dma_axi_wstrb (lsu_axi_wstrb),
.dma_axi_wlast (1'b1),
.dma_axi_bvalid(dma_axi_bvalid),
.dma_axi_bready(dma_axi_bready),
.dma_axi_bresp (dma_axi_bresp),
.dma_axi_bid (),
.dma_axi_arvalid(dma_axi_arvalid),
.dma_axi_arready(dma_axi_arready),
.dma_axi_arid ('0),
.dma_axi_araddr (lsu_axi_araddr),
.dma_axi_arsize (lsu_axi_arsize),
.dma_axi_arprot ('0),
.dma_axi_arlen ('0),
.dma_axi_arburst('0),
.dma_axi_rvalid(dma_axi_rvalid),
.dma_axi_rready(dma_axi_rready),
.dma_axi_rid (),
.dma_axi_rdata (dma_axi_rdata),
.dma_axi_rresp (dma_axi_rresp),
.dma_axi_rlast (dma_axi_rlast),
.timer_int (1'b0),
.extintsrc_req('0),
.lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
.ifu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
.dbg_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB Debug master interface
.dma_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB slave interface
.trace_rv_i_insn_ip (trace_rv_i_insn_ip),
.trace_rv_i_address_ip (trace_rv_i_address_ip),
.trace_rv_i_valid_ip (trace_rv_i_valid_ip),
.trace_rv_i_exception_ip(trace_rv_i_exception_ip),
.trace_rv_i_ecause_ip (trace_rv_i_ecause_ip),
.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
.trace_rv_i_tval_ip (trace_rv_i_tval_ip),
.jtag_tck (jtag_tck),
.jtag_tms (jtag_tms),
.jtag_tdi (jtag_tdi),
.jtag_trst_n(jtag_trst_n),
.jtag_tdo (jtag_tdo),
.mpc_debug_halt_ack(mpc_debug_halt_ack),
.mpc_debug_halt_req(1'b0),
.mpc_debug_run_ack (mpc_debug_run_ack),
.mpc_debug_run_req (1'b1),
.mpc_reset_run_req (1'b1), // Start running after reset
.debug_brkpt_status(debug_brkpt_status),
.i_cpu_halt_req(1'b0), // Async halt req to CPU
.o_cpu_halt_ack(o_cpu_halt_ack), // core response to halt
.o_cpu_halt_status(o_cpu_halt_status), // 1'b1 indicates core is halted
.i_cpu_run_req(1'b0), // Async restart req to CPU
.o_debug_mode_status(o_debug_mode_status),
.o_cpu_run_ack(o_cpu_run_ack), // Core response to run req
.dec_tlu_perfcnt0(),
.dec_tlu_perfcnt1(),
.dec_tlu_perfcnt2(),
.dec_tlu_perfcnt3(),
// remove mems DFT pins for opensource
.dccm_ext_in_pkt ('0),
.iccm_ext_in_pkt ('0),
.ic_data_ext_in_pkt('0),
.ic_tag_ext_in_pkt ('0),
.soft_int ('0),
.core_id ('0),
.scan_mode (1'b0), // To enable scan mode
.mbist_mode(1'b0) // to enable mbist
);
axi_slv #(
.TAGW(`RV_IFU_BUS_TAG)
) imem (
.aclk(clk),
.rst_l(rst),
.arvalid(ifu_axi_arvalid),
.arready(ifu_axi_arready),
.araddr(ifu_axi_araddr),
.arid(ifu_axi_arid),
.arlen(ifu_axi_arlen),
.arburst(ifu_axi_arburst),
.arsize(ifu_axi_arsize),
.rvalid(ifu_axi_rvalid),
.rready(ifu_axi_rready),
.rdata(ifu_axi_rdata),
.rresp(ifu_axi_rresp),
.rid(ifu_axi_rid),
.rlast(ifu_axi_rlast),
.awvalid(1'b0),
.awready(),
.awaddr('0),
.awid('0),
.awlen('0),
.awburst('0),
.awsize('0),
.wdata ('0),
.wstrb ('0),
.wvalid(1'b0),
.wready(),
.bvalid(),
.bready(1'b0),
.bresp(),
.bid()
);
defparam lmem.TAGW = `RV_LSU_BUS_TAG;
//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(
axi_slv lmem (
.aclk(clk),
.rst_l(rst),
.arvalid(lmem_axi_arvalid),
.arready(lmem_axi_arready),
.araddr(lsu_axi_araddr),
.arid(lsu_axi_arid),
.arlen(lsu_axi_arlen),
.arburst(lsu_axi_arburst),
.arsize(lsu_axi_arsize),
.rvalid(lmem_axi_rvalid),
.rready(lmem_axi_rready),
.rdata(lmem_axi_rdata),
.rresp(lmem_axi_rresp),
.rid(lmem_axi_rid),
.rlast(lmem_axi_rlast),
.awvalid(lmem_axi_awvalid),
.awready(lmem_axi_awready),
.awaddr(lsu_axi_awaddr),
.awid(lsu_axi_awid),
.awlen(lsu_axi_awlen),
.awburst(lsu_axi_awburst),
.awsize(lsu_axi_awsize),
.wdata (lsu_axi_wdata),
.wstrb (lsu_axi_wstrb),
.wvalid(lmem_axi_wvalid),
.wready(lmem_axi_wready),
.bvalid(lmem_axi_bvalid),
.bready(lmem_axi_bready),
.bresp(lmem_axi_bresp),
.bid(lmem_axi_bid)
);
axi_lsu_dma_bridge #(`RV_LSU_BUS_TAG, `RV_LSU_BUS_TAG) bridge (
.clk(clk),
.reset_l(rst),
.m_arvalid(lsu_axi_arvalid),
.m_arid(lsu_axi_arid),
.m_araddr(lsu_axi_araddr),
.m_arready(lsu_axi_arready),
.m_rvalid(lsu_axi_rvalid),
.m_rready(lsu_axi_rready),
.m_rdata(lsu_axi_rdata),
.m_rid(lsu_axi_rid),
.m_rresp(lsu_axi_rresp),
.m_rlast(lsu_axi_rlast),
.m_awvalid(lsu_axi_awvalid),
.m_awid(lsu_axi_awid),
.m_awaddr(lsu_axi_awaddr),
.m_awready(lsu_axi_awready),
.m_wvalid(lsu_axi_wvalid),
.m_wready(lsu_axi_wready),
.m_bresp(lsu_axi_bresp),
.m_bvalid(lsu_axi_bvalid),
.m_bid(lsu_axi_bid),
.m_bready(lsu_axi_bready),
.s0_arvalid(lmem_axi_arvalid),
.s0_arready(lmem_axi_arready),
.s0_rvalid(lmem_axi_rvalid),
.s0_rid(lmem_axi_rid),
.s0_rresp(lmem_axi_rresp),
.s0_rdata(lmem_axi_rdata),
.s0_rlast(lmem_axi_rlast),
.s0_rready(lmem_axi_rready),
.s0_awvalid(lmem_axi_awvalid),
.s0_awready(lmem_axi_awready),
.s0_wvalid(lmem_axi_wvalid),
.s0_wready(lmem_axi_wready),
.s0_bresp(lmem_axi_bresp),
.s0_bvalid(lmem_axi_bvalid),
.s0_bid(lmem_axi_bid),
.s0_bready(lmem_axi_bready),
.s1_arvalid(dma_axi_arvalid),
.s1_arready(dma_axi_arready),
.s1_rvalid(dma_axi_rvalid),
.s1_rresp (dma_axi_rresp),
.s1_rdata (dma_axi_rdata),
.s1_rlast (dma_axi_rlast),
.s1_rready(dma_axi_rready),
.s1_awvalid(dma_axi_awvalid),
.s1_awready(dma_axi_awready),
.s1_wvalid(dma_axi_wvalid),
.s1_wready(dma_axi_wready),
.s1_bresp (dma_axi_bresp),
.s1_bvalid(dma_axi_bvalid),
.s1_bready(dma_axi_bready)
);
endmodule

2609
soc/swerv.config Executable file
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41
soc/swerv_config_gen.py Normal file
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@ -0,0 +1,41 @@
#!/usr/bin/env python3
from fusesoc.capi2.generator import Generator
import os
import subprocess
import sys
class SwervConfigGenerator(Generator):
def run(self):
script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
files = [
{"common_defines.vh" : {
"copyto" : "config/common_defines.vh",
"file_type" : "systemVerilogSource"}},
{"el2_pdef.vh" : {
"copyto" : "config/el2_pdef.vh",
"file_type" : "systemVerilogSource"}},
{"el2_param.vh" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}},
{"pic_map_auto.h" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}}]
env = os.environ.copy()
env['RV_ROOT'] = script_root
env['BUILD_PATH'] = os.getcwd()
args = ['configs/swerv.config'] + self.config.get('args', [])
rc = subprocess.call(args, cwd=script_root, env=env, stdout=subprocess.DEVNULL)
if rc:
exit(1)
filenames = []
for f in files:
for k in f:
filenames.append(k)
self.add_files(files)
g = SwervConfigGenerator()
g.run()
g.write()

26
tools/program.hex Executable file
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@80000000
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
17 02 00 00 13 02 E2 0E 83 02 02 00 23 80 51 00
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
51 00 E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00
@8000010E
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 66
72 6F 6D 20 53 77 65 52 56 20 45 4C 32 20 40 57
44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 2D 2D 2D 2D 2D 2D 0A 00

247
tools/snapshots/default/common_defines.vh Normal file
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
//
// cmd: swerv -target=default -set build_axi4
//
`define RV_ROOT "/home/colin/develop/Cores-SweRV-EL2"
`define RV_NMI_VEC 'h11110000
`define RV_NUMIREGS 32
`define RV_BHT_GHR_RANGE 7:0
`define RV_BHT_HASH_STRING {hashin[8+1:2]^ghr[8-1:0]}// cf2
`define RV_BHT_ADDR_HI 9
`define RV_BHT_GHR_SIZE 8
`define RV_BHT_ARRAY_DEPTH 256
`define RV_BHT_GHR_HASH_1
`define RV_BHT_SIZE 512
`define RV_BHT_ADDR_LO 2
`define RV_RET_STACK_SIZE 8
`define RV_CONFIG_KEY 32'hdeadbeef
`define RV_TARGET default
`define RV_DCCM_OFFSET 28'h40000
`define RV_DCCM_REGION 4'hf
`define RV_DCCM_EADR 32'hf004ffff
`define RV_DCCM_SIZE 64
`define RV_DCCM_SADR 32'hf0040000
`define RV_DCCM_FDATA_WIDTH 39
`define RV_DCCM_BANK_BITS 2
`define RV_DCCM_NUM_BANKS_4
`define RV_DCCM_ROWS 4096
`define RV_DCCM_ENABLE 1
`define RV_DCCM_INDEX_BITS 12
`define RV_DCCM_BITS 16
`define RV_DCCM_NUM_BANKS 4
`define RV_LSU_SB_BITS 16
`define RV_DCCM_DATA_WIDTH 32
`define RV_DCCM_DATA_CELL ram_4096x39
`define RV_DCCM_RESERVED 'h1400
`define RV_DCCM_SIZE_64
`define RV_DCCM_ECC_WIDTH 7
`define RV_DCCM_WIDTH_BITS 2
`define RV_DCCM_BYTE_WIDTH 4
`define REGWIDTH 32
`define RV_RESET_VEC 'h80000000
`define RV_LSU_STBUF_DEPTH 4
`define RV_BITMANIP_ZBR 0
`define RV_BITMANIP_ZBS 1
`define RV_BITMANIP_ZBF 0
`define RV_FPGA_OPTIMIZE 1
`define RV_DMA_BUF_DEPTH 5
`define RV_BITMANIP_ZBC 1
`define RV_BITMANIP_ZBE 0
`define RV_ICCM_ICACHE 1
`define RV_FAST_INTERRUPT_REDIRECT 1
`define RV_LSU_NUM_NBLOAD 4
`define RV_BITMANIP_ZBA 1
`define RV_BITMANIP_ZBP 0
`define RV_LSU2DMA 0
`define RV_LSU_NUM_NBLOAD_WIDTH 2
`define RV_DIV_BIT 4
`define RV_BITMANIP_ZBB 1
`define RV_TIMER_LEGAL_EN 1
`define RV_DIV_NEW 1
`define RV_SERIALIO 'hd0580000
`define RV_EXTERNAL_DATA 'hc0580000
`define RV_UNUSED_REGION5 'h30000000
`define RV_UNUSED_REGION4 'h40000000
`define RV_UNUSED_REGION1 'h70000000
`define RV_UNUSED_REGION8 'h00000000
`define RV_UNUSED_REGION2 'h60000000
`define RV_UNUSED_REGION7 'h10000000
`define RV_DEBUG_SB_MEM 'ha0580000
`define RV_UNUSED_REGION6 'h20000000
`define RV_UNUSED_REGION3 'h50000000
`define RV_EXTERNAL_DATA_1 'hb0000000
`define RV_UNUSED_REGION0 'h90000000
`define RV_ICCM_NUM_BANKS 4
`define RV_ICCM_BITS 16
`define RV_ICCM_INDEX_BITS 12
`define RV_ICCM_ENABLE 1
`define RV_ICCM_SIZE_64
`define RV_ICCM_DATA_CELL ram_4096x39
`define RV_ICCM_RESERVED 'h1000
`define RV_ICCM_BANK_INDEX_LO 4
`define RV_ICCM_SADR 32'hee000000
`define RV_ICCM_EADR 32'hee00ffff
`define RV_ICCM_OFFSET 10'he000000
`define RV_ICCM_REGION 4'he
`define RV_ICCM_SIZE 64
`define RV_ICCM_NUM_BANKS_4
`define RV_ICCM_ROWS 4096
`define RV_ICCM_BANK_HI 3
`define RV_ICCM_BANK_BITS 2
`define RV_PIC_MEIPL_MASK 'hf
`define RV_PIC_MEIPL_COUNT 31
`define RV_PIC_MEIE_COUNT 31
`define RV_PIC_MEIP_MASK 'h0
`define RV_PIC_MEIPT_OFFSET 'h3004
`define RV_PIC_REGION 4'hf
`define RV_PIC_TOTAL_INT 31
`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
`define RV_PIC_MEIP_COUNT 1
`define RV_PIC_MEIE_MASK 'h1
`define RV_PIC_MPICCFG_OFFSET 'h3000
`define RV_PIC_MEIGWCLR_MASK 'h0
`define RV_PIC_MEIGWCLR_COUNT 31
`define RV_PIC_INT_WORDS 1
`define RV_PIC_OFFSET 10'hc0000
`define RV_PIC_MEIP_OFFSET 'h1000
`define RV_PIC_BITS 15
`define RV_PIC_MPICCFG_COUNT 1
`define RV_PIC_MEIGWCLR_OFFSET 'h5000
`define RV_PIC_SIZE 32
`define RV_PIC_MPICCFG_MASK 'h1
`define RV_PIC_TOTAL_INT_PLUS1 32
`define RV_PIC_MEIPL_OFFSET 'h0000
`define RV_PIC_MEIGWCTRL_COUNT 31
`define RV_PIC_BASE_ADDR 32'hf00c0000
`define RV_PIC_MEIPT_MASK 'h0
`define RV_PIC_MEIE_OFFSET 'h2000
`define RV_PIC_MEIGWCTRL_MASK 'h3
`define RV_PIC_MEIPT_COUNT 31
`define RV_INST_ACCESS_ADDR2 'h00000000
`define RV_DATA_ACCESS_MASK6 'hffffffff
`define RV_DATA_ACCESS_ENABLE0 1'h0
`define RV_INST_ACCESS_ENABLE4 1'h0
`define RV_INST_ACCESS_MASK1 'hffffffff
`define RV_INST_ACCESS_ADDR5 'h00000000
`define RV_INST_ACCESS_ENABLE1 1'h0
`define RV_INST_ACCESS_MASK4 'hffffffff
`define RV_DATA_ACCESS_ADDR2 'h00000000
`define RV_INST_ACCESS_MASK6 'hffffffff
`define RV_INST_ACCESS_ENABLE0 1'h0
`define RV_DATA_ACCESS_ADDR5 'h00000000
`define RV_DATA_ACCESS_MASK1 'hffffffff
`define RV_DATA_ACCESS_ENABLE4 1'h0
`define RV_DATA_ACCESS_ENABLE1 1'h0
`define RV_DATA_ACCESS_MASK4 'hffffffff
`define RV_DATA_ACCESS_ENABLE6 1'h0
`define RV_INST_ACCESS_MASK7 'hffffffff
`define RV_INST_ACCESS_ENABLE5 1'h0
`define RV_DATA_ACCESS_MASK0 'hffffffff
`define RV_INST_ACCESS_ADDR3 'h00000000
`define RV_INST_ACCESS_ENABLE6 1'h0
`define RV_DATA_ACCESS_MASK7 'hffffffff
`define RV_DATA_ACCESS_ENABLE5 1'h0
`define RV_INST_ACCESS_MASK0 'hffffffff
`define RV_DATA_ACCESS_ADDR3 'h00000000
`define RV_DATA_ACCESS_ENABLE3 1'h0
`define RV_DATA_ACCESS_ADDR0 'h00000000
`define RV_INST_ACCESS_MASK3 'hffffffff
`define RV_DATA_ACCESS_ENABLE2 1'h0
`define RV_INST_ACCESS_ADDR7 'h00000000
`define RV_INST_ACCESS_ENABLE3 1'h0
`define RV_INST_ACCESS_ADDR0 'h00000000
`define RV_DATA_ACCESS_MASK3 'hffffffff
`define RV_DATA_ACCESS_ADDR7 'h00000000
`define RV_INST_ACCESS_ENABLE2 1'h0
`define RV_INST_ACCESS_MASK5 'hffffffff
`define RV_INST_ACCESS_ADDR1 'h00000000
`define RV_INST_ACCESS_ADDR4 'h00000000
`define RV_INST_ACCESS_MASK2 'hffffffff
`define RV_INST_ACCESS_ENABLE7 1'h0
`define RV_DATA_ACCESS_ADDR6 'h00000000
`define RV_DATA_ACCESS_ADDR1 'h00000000
`define RV_DATA_ACCESS_MASK5 'hffffffff
`define RV_DATA_ACCESS_ADDR4 'h00000000
`define RV_DATA_ACCESS_MASK2 'hffffffff
`define RV_DATA_ACCESS_ENABLE7 1'h0
`define RV_INST_ACCESS_ADDR6 'h00000000
`define RV_IFU_BUS_PRTY 2
`define RV_SB_BUS_PRTY 2
`define RV_LSU_BUS_ID 1
`define RV_LSU_BUS_TAG 3
`define RV_SB_BUS_TAG 1
`define RV_DMA_BUS_ID 1
`define RV_DMA_BUS_TAG 1
`define RV_LSU_BUS_PRTY 2
`define RV_BUS_PRTY_DEFAULT 2'h3
`define RV_SB_BUS_ID 1
`define RV_DMA_BUS_PRTY 2
`define RV_IFU_BUS_ID 1
`define RV_IFU_BUS_TAG 3
`define RV_XLEN 32
`define RV_BTB_INDEX3_LO 18
`define RV_BTB_INDEX1_LO 2
`define RV_BTB_ADDR_HI 9
`define RV_BTB_INDEX2_LO 10
`define RV_BTB_SIZE 512
`define RV_BTB_BTAG_FOLD 0
`define RV_BTB_ADDR_LO 2
`define RV_BTB_INDEX2_HI 17
`define RV_BTB_ENABLE 1
`define RV_BTB_TOFFSET_SIZE 12
`define RV_BTB_INDEX3_HI 25
`define RV_BTB_ARRAY_DEPTH 256
`define RV_BTB_BTAG_SIZE 5
`define RV_BTB_INDEX1_HI 9
`define RV_BTB_FOLD2_INDEX_HASH 0
`define TEC_RV_ICG clockhdr
`define RV_ASSERT_ON
`define RV_STERR_ROLLBACK 0
`define RV_BUILD_AXI4 1
`define SDVT_AHB 0
`define RV_EXT_DATAWIDTH 64
`define RV_EXT_ADDRWIDTH 32
`define TOP tb_top
`define RV_LDERR_ROLLBACK 1
`define RV_BUILD_AXI_NATIVE 1
`define RV_TOP `TOP.rvtop
`define CLOCK_PERIOD 100
`define CPU_TOP `RV_TOP.swerv
`define RV_ICACHE_INDEX_HI 12
`define RV_ICACHE_TAG_CELL ram_128x25
`define RV_ICACHE_NUM_BEATS 8
`define RV_ICACHE_FDATA_WIDTH 71
`define RV_ICACHE_NUM_BYPASS_WIDTH 2
`define RV_ICACHE_TAG_DEPTH 128
`define RV_ICACHE_TAG_BYPASS_ENABLE 1
`define RV_ICACHE_SIZE 16
`define RV_ICACHE_TAG_NUM_BYPASS 2
`define RV_ICACHE_BANK_WIDTH 8
`define RV_ICACHE_DATA_INDEX_LO 4
`define RV_ICACHE_2BANKS 1
`define RV_ICACHE_NUM_LINES_BANK 64
`define RV_ICACHE_ECC 1
`define RV_ICACHE_STATUS_BITS 1
`define RV_ICACHE_TAG_NUM_BYPASS_WIDTH 2
`define RV_ICACHE_BEAT_BITS 3
`define RV_ICACHE_DATA_WIDTH 64
`define RV_ICACHE_BYPASS_ENABLE 1
`define RV_ICACHE_WAYPACK 1
`define RV_ICACHE_NUM_BYPASS 2
`define RV_ICACHE_DATA_DEPTH 512
`define RV_ICACHE_BEAT_ADDR_HI 5
`define RV_ICACHE_TAG_LO 13
`define RV_ICACHE_BANK_BITS 1
`define RV_ICACHE_ENABLE 1
`define RV_ICACHE_BANK_HI 3
`define RV_ICACHE_NUM_LINES 256
`define RV_ICACHE_TAG_INDEX_LO 6
`define RV_ICACHE_LN_SZ 64
`define RV_ICACHE_NUM_LINES_WAY 128
`define RV_ICACHE_DATA_CELL ram_512x71
`define RV_ICACHE_BANKS_WAY 2
`define RV_ICACHE_NUM_WAYS 2
`define RV_ICACHE_SCND_LAST 6
`define RV_ICACHE_BANK_LO 3
`undef RV_ASSERT_ON

176
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
//
// cmd: swerv -target=default -set build_axi4
//
#ifndef RV_NMI_VEC
#define RV_NMI_VEC 0x11110000
#endif
#define RV_TARGET default
#define RV_DCCM_OFFSET 0x40000
#define RV_DCCM_REGION 0xf
#define RV_DCCM_EADR 0xf004ffff
#define RV_DCCM_SIZE 64
#define RV_DCCM_SADR 0xf0040000
#define RV_DCCM_FDATA_WIDTH 39
#define RV_DCCM_BANK_BITS 2
#define RV_DCCM_NUM_BANKS_4
#define RV_DCCM_ROWS 4096
#define RV_DCCM_ENABLE 1
#define RV_DCCM_INDEX_BITS 12
#define RV_DCCM_BITS 16
#define RV_DCCM_NUM_BANKS 4
#define RV_LSU_SB_BITS 16
#define RV_DCCM_DATA_WIDTH 32
#define RV_DCCM_DATA_CELL ram_4096x39
#define RV_DCCM_RESERVED 0x1400
#define RV_DCCM_SIZE_64
#define RV_DCCM_ECC_WIDTH 7
#define RV_DCCM_WIDTH_BITS 2
#define RV_DCCM_BYTE_WIDTH 4
#ifndef RV_RESET_VEC
#define RV_RESET_VEC 0x80000000
#endif
#define RV_LSU_STBUF_DEPTH 4
#define RV_BITMANIP_ZBR 0
#define RV_BITMANIP_ZBS 1
#define RV_BITMANIP_ZBF 0
#define RV_FPGA_OPTIMIZE 1
#define RV_DMA_BUF_DEPTH 5
#define RV_BITMANIP_ZBC 1
#define RV_BITMANIP_ZBE 0
#define RV_ICCM_ICACHE 1
#define RV_FAST_INTERRUPT_REDIRECT 1
#define RV_LSU_NUM_NBLOAD 4
#define RV_BITMANIP_ZBA 1
#define RV_BITMANIP_ZBP 0
#define RV_LSU2DMA 0
#define RV_LSU_NUM_NBLOAD_WIDTH 2
#define RV_DIV_BIT 4
#define RV_BITMANIP_ZBB 1
#define RV_TIMER_LEGAL_EN 1
#define RV_DIV_NEW 1
#ifndef RV_SERIALIO
#define RV_SERIALIO 0xd0580000
#endif
#ifndef RV_EXTERNAL_DATA
#define RV_EXTERNAL_DATA 0xc0580000
#endif
#define RV_UNUSED_REGION5 0x30000000
#define RV_UNUSED_REGION4 0x40000000
#define RV_UNUSED_REGION1 0x70000000
#define RV_UNUSED_REGION8 0x00000000
#define RV_UNUSED_REGION2 0x60000000
#define RV_UNUSED_REGION7 0x10000000
#define RV_DEBUG_SB_MEM 0xa0580000
#define RV_UNUSED_REGION6 0x20000000
#define RV_UNUSED_REGION3 0x50000000
#define RV_EXTERNAL_DATA_1 0xb0000000
#define RV_UNUSED_REGION0 0x90000000
#define RV_ICCM_NUM_BANKS 4
#define RV_ICCM_BITS 16
#define RV_ICCM_INDEX_BITS 12
#define RV_ICCM_ENABLE 1
#define RV_ICCM_SIZE_64
#define RV_ICCM_DATA_CELL ram_4096x39
#define RV_ICCM_RESERVED 0x1000
#define RV_ICCM_BANK_INDEX_LO 4
#define RV_ICCM_SADR 0xee000000
#define RV_ICCM_EADR 0xee00ffff
#define RV_ICCM_OFFSET 0xe000000
#define RV_ICCM_REGION 0xe
#define RV_ICCM_SIZE 64
#define RV_ICCM_NUM_BANKS_4
#define RV_ICCM_ROWS 4096
#define RV_ICCM_BANK_HI 3
#define RV_ICCM_BANK_BITS 2
#define RV_PIC_MEIPL_MASK 0xf
#define RV_PIC_MEIPL_COUNT 31
#define RV_PIC_MEIE_COUNT 31
#define RV_PIC_MEIP_MASK 0x0
#define RV_PIC_MEIPT_OFFSET 0x3004
#define RV_PIC_REGION 0xf
#define RV_PIC_TOTAL_INT 31
#define RV_PIC_MEIGWCTRL_OFFSET 0x4000
#define RV_PIC_MEIP_COUNT 1
#define RV_PIC_MEIE_MASK 0x1
#define RV_PIC_MPICCFG_OFFSET 0x3000
#define RV_PIC_MEIGWCLR_MASK 0x0
#define RV_PIC_MEIGWCLR_COUNT 31
#define RV_PIC_INT_WORDS 1
#define RV_PIC_OFFSET 0xc0000
#define RV_PIC_MEIP_OFFSET 0x1000
#define RV_PIC_BITS 15
#define RV_PIC_MPICCFG_COUNT 1
#define RV_PIC_MEIGWCLR_OFFSET 0x5000
#define RV_PIC_SIZE 32
#define RV_PIC_MPICCFG_MASK 0x1
#define RV_PIC_TOTAL_INT_PLUS1 32
#define RV_PIC_MEIPL_OFFSET 0x0000
#define RV_PIC_MEIGWCTRL_COUNT 31
#define RV_PIC_BASE_ADDR 0xf00c0000
#define RV_PIC_MEIPT_MASK 0x0
#define RV_PIC_MEIE_OFFSET 0x2000
#define RV_PIC_MEIGWCTRL_MASK 0x3
#define RV_PIC_MEIPT_COUNT 31
#define RV_INST_ACCESS_ADDR2 0x00000000
#define RV_DATA_ACCESS_MASK6 0xffffffff
#define RV_DATA_ACCESS_ENABLE0 0x0
#define RV_INST_ACCESS_ENABLE4 0x0
#define RV_INST_ACCESS_MASK1 0xffffffff
#define RV_INST_ACCESS_ADDR5 0x00000000
#define RV_INST_ACCESS_ENABLE1 0x0
#define RV_INST_ACCESS_MASK4 0xffffffff
#define RV_DATA_ACCESS_ADDR2 0x00000000
#define RV_INST_ACCESS_MASK6 0xffffffff
#define RV_INST_ACCESS_ENABLE0 0x0
#define RV_DATA_ACCESS_ADDR5 0x00000000
#define RV_DATA_ACCESS_MASK1 0xffffffff
#define RV_DATA_ACCESS_ENABLE4 0x0
#define RV_DATA_ACCESS_ENABLE1 0x0
#define RV_DATA_ACCESS_MASK4 0xffffffff
#define RV_DATA_ACCESS_ENABLE6 0x0
#define RV_INST_ACCESS_MASK7 0xffffffff
#define RV_INST_ACCESS_ENABLE5 0x0
#define RV_DATA_ACCESS_MASK0 0xffffffff
#define RV_INST_ACCESS_ADDR3 0x00000000
#define RV_INST_ACCESS_ENABLE6 0x0
#define RV_DATA_ACCESS_MASK7 0xffffffff
#define RV_DATA_ACCESS_ENABLE5 0x0
#define RV_INST_ACCESS_MASK0 0xffffffff
#define RV_DATA_ACCESS_ADDR3 0x00000000
#define RV_DATA_ACCESS_ENABLE3 0x0
#define RV_DATA_ACCESS_ADDR0 0x00000000
#define RV_INST_ACCESS_MASK3 0xffffffff
#define RV_DATA_ACCESS_ENABLE2 0x0
#define RV_INST_ACCESS_ADDR7 0x00000000
#define RV_INST_ACCESS_ENABLE3 0x0
#define RV_INST_ACCESS_ADDR0 0x00000000
#define RV_DATA_ACCESS_MASK3 0xffffffff
#define RV_DATA_ACCESS_ADDR7 0x00000000
#define RV_INST_ACCESS_ENABLE2 0x0
#define RV_INST_ACCESS_MASK5 0xffffffff
#define RV_INST_ACCESS_ADDR1 0x00000000
#define RV_INST_ACCESS_ADDR4 0x00000000
#define RV_INST_ACCESS_MASK2 0xffffffff
#define RV_INST_ACCESS_ENABLE7 0x0
#define RV_DATA_ACCESS_ADDR6 0x00000000
#define RV_DATA_ACCESS_ADDR1 0x00000000
#define RV_DATA_ACCESS_MASK5 0xffffffff
#define RV_DATA_ACCESS_ADDR4 0x00000000
#define RV_DATA_ACCESS_MASK2 0xffffffff
#define RV_DATA_ACCESS_ENABLE7 0x0
#define RV_INST_ACCESS_ADDR6 0x00000000
#define RV_XLEN 32
#define RV_ASSERT_ON
#define RV_STERR_ROLLBACK 0
#define RV_BUILD_AXI4 1
#define SDVT_AHB 0
#define RV_EXT_DATAWIDTH 64
#define RV_EXT_ADDRWIDTH 32
#define TOP tb_top
#define RV_LDERR_ROLLBACK 1
#define RV_BUILD_AXI_NATIVE 1
#define RV_TOP `TOP.rvtop
#define CLOCK_PERIOD 100
#define CPU_TOP `RV_TOP.swerv

175
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parameter el2_param_t pt = '{
BHT_ADDR_HI : 8'h09 ,
BHT_ADDR_LO : 6'h02 ,
BHT_ARRAY_DEPTH : 15'h0100 ,
BHT_GHR_HASH_1 : 5'h00 ,
BHT_GHR_SIZE : 8'h08 ,
BHT_SIZE : 16'h0200 ,
BITMANIP_ZBA : 5'h01 ,
BITMANIP_ZBB : 5'h01 ,
BITMANIP_ZBC : 5'h01 ,
BITMANIP_ZBE : 5'h00 ,
BITMANIP_ZBF : 5'h00 ,
BITMANIP_ZBP : 5'h00 ,
BITMANIP_ZBR : 5'h00 ,
BITMANIP_ZBS : 5'h01 ,
BTB_ADDR_HI : 9'h009 ,
BTB_ADDR_LO : 6'h02 ,
BTB_ARRAY_DEPTH : 13'h0100 ,
BTB_BTAG_FOLD : 5'h00 ,
BTB_BTAG_SIZE : 9'h005 ,
BTB_ENABLE : 5'h01 ,
BTB_FOLD2_INDEX_HASH : 5'h00 ,
BTB_FULLYA : 5'h00 ,
BTB_INDEX1_HI : 9'h009 ,
BTB_INDEX1_LO : 9'h002 ,
BTB_INDEX2_HI : 9'h011 ,
BTB_INDEX2_LO : 9'h00A ,
BTB_INDEX3_HI : 9'h019 ,
BTB_INDEX3_LO : 9'h012 ,
BTB_SIZE : 14'h0200 ,
BTB_TOFFSET_SIZE : 9'h00C ,
BUILD_AHB_LITE : 4'h0 ,
BUILD_AXI4 : 5'h01 ,
BUILD_AXI_NATIVE : 5'h01 ,
BUS_PRTY_DEFAULT : 6'h03 ,
DATA_ACCESS_ADDR0 : 36'h000000000 ,
DATA_ACCESS_ADDR1 : 36'h000000000 ,
DATA_ACCESS_ADDR2 : 36'h000000000 ,
DATA_ACCESS_ADDR3 : 36'h000000000 ,
DATA_ACCESS_ADDR4 : 36'h000000000 ,
DATA_ACCESS_ADDR5 : 36'h000000000 ,
DATA_ACCESS_ADDR6 : 36'h000000000 ,
DATA_ACCESS_ADDR7 : 36'h000000000 ,
DATA_ACCESS_ENABLE0 : 5'h00 ,
DATA_ACCESS_ENABLE1 : 5'h00 ,
DATA_ACCESS_ENABLE2 : 5'h00 ,
DATA_ACCESS_ENABLE3 : 5'h00 ,
DATA_ACCESS_ENABLE4 : 5'h00 ,
DATA_ACCESS_ENABLE5 : 5'h00 ,
DATA_ACCESS_ENABLE6 : 5'h00 ,
DATA_ACCESS_ENABLE7 : 5'h00 ,
DATA_ACCESS_MASK0 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK1 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK2 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK3 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK4 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK5 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK6 : 36'h0FFFFFFFF ,
DATA_ACCESS_MASK7 : 36'h0FFFFFFFF ,
DCCM_BANK_BITS : 7'h02 ,
DCCM_BITS : 9'h010 ,
DCCM_BYTE_WIDTH : 7'h04 ,
DCCM_DATA_WIDTH : 10'h020 ,
DCCM_ECC_WIDTH : 7'h07 ,
DCCM_ENABLE : 5'h01 ,
DCCM_FDATA_WIDTH : 10'h027 ,
DCCM_INDEX_BITS : 8'h0C ,
DCCM_NUM_BANKS : 9'h004 ,
DCCM_REGION : 8'h0F ,
DCCM_SADR : 36'h0F0040000 ,
DCCM_SIZE : 14'h0040 ,
DCCM_WIDTH_BITS : 6'h02 ,
DIV_BIT : 7'h04 ,
DIV_NEW : 5'h01 ,
DMA_BUF_DEPTH : 7'h05 ,
DMA_BUS_ID : 9'h001 ,
DMA_BUS_PRTY : 6'h02 ,
DMA_BUS_TAG : 8'h01 ,
FAST_INTERRUPT_REDIRECT : 5'h01 ,
ICACHE_2BANKS : 5'h01 ,
ICACHE_BANK_BITS : 7'h01 ,
ICACHE_BANK_HI : 7'h03 ,
ICACHE_BANK_LO : 6'h03 ,
ICACHE_BANK_WIDTH : 8'h08 ,
ICACHE_BANKS_WAY : 7'h02 ,
ICACHE_BEAT_ADDR_HI : 8'h05 ,
ICACHE_BEAT_BITS : 8'h03 ,
ICACHE_BYPASS_ENABLE : 5'h01 ,
ICACHE_DATA_DEPTH : 18'h00200 ,
ICACHE_DATA_INDEX_LO : 7'h04 ,
ICACHE_DATA_WIDTH : 11'h040 ,
ICACHE_ECC : 5'h01 ,
ICACHE_ENABLE : 5'h01 ,
ICACHE_FDATA_WIDTH : 11'h047 ,
ICACHE_INDEX_HI : 9'h00C ,
ICACHE_LN_SZ : 11'h040 ,
ICACHE_NUM_BEATS : 8'h08 ,
ICACHE_NUM_BYPASS : 8'h02 ,
ICACHE_NUM_BYPASS_WIDTH : 8'h02 ,
ICACHE_NUM_WAYS : 7'h02 ,
ICACHE_ONLY : 5'h00 ,
ICACHE_SCND_LAST : 8'h06 ,
ICACHE_SIZE : 13'h0010 ,
ICACHE_STATUS_BITS : 7'h01 ,
ICACHE_TAG_BYPASS_ENABLE : 5'h01 ,
ICACHE_TAG_DEPTH : 17'h00080 ,
ICACHE_TAG_INDEX_LO : 7'h06 ,
ICACHE_TAG_LO : 9'h00D ,
ICACHE_TAG_NUM_BYPASS : 8'h02 ,
ICACHE_TAG_NUM_BYPASS_WIDTH : 8'h02 ,
ICACHE_WAYPACK : 5'h01 ,
ICCM_BANK_BITS : 7'h02 ,
ICCM_BANK_HI : 9'h003 ,
ICCM_BANK_INDEX_LO : 9'h004 ,
ICCM_BITS : 9'h010 ,
ICCM_ENABLE : 5'h01 ,
ICCM_ICACHE : 5'h01 ,
ICCM_INDEX_BITS : 8'h0C ,
ICCM_NUM_BANKS : 9'h004 ,
ICCM_ONLY : 5'h00 ,
ICCM_REGION : 8'h0E ,
ICCM_SADR : 36'h0EE000000 ,
ICCM_SIZE : 14'h0040 ,
IFU_BUS_ID : 5'h01 ,
IFU_BUS_PRTY : 6'h02 ,
IFU_BUS_TAG : 8'h03 ,
INST_ACCESS_ADDR0 : 36'h000000000 ,
INST_ACCESS_ADDR1 : 36'h000000000 ,
INST_ACCESS_ADDR2 : 36'h000000000 ,
INST_ACCESS_ADDR3 : 36'h000000000 ,
INST_ACCESS_ADDR4 : 36'h000000000 ,
INST_ACCESS_ADDR5 : 36'h000000000 ,
INST_ACCESS_ADDR6 : 36'h000000000 ,
INST_ACCESS_ADDR7 : 36'h000000000 ,
INST_ACCESS_ENABLE0 : 5'h00 ,
INST_ACCESS_ENABLE1 : 5'h00 ,
INST_ACCESS_ENABLE2 : 5'h00 ,
INST_ACCESS_ENABLE3 : 5'h00 ,
INST_ACCESS_ENABLE4 : 5'h00 ,
INST_ACCESS_ENABLE5 : 5'h00 ,
INST_ACCESS_ENABLE6 : 5'h00 ,
INST_ACCESS_ENABLE7 : 5'h00 ,
INST_ACCESS_MASK0 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK1 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK2 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK3 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK4 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK5 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK6 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK7 : 36'h0FFFFFFFF ,
LOAD_TO_USE_PLUS1 : 5'h00 ,
LSU2DMA : 5'h00 ,
LSU_BUS_ID : 5'h01 ,
LSU_BUS_PRTY : 6'h02 ,
LSU_BUS_TAG : 8'h03 ,
LSU_NUM_NBLOAD : 9'h004 ,
LSU_NUM_NBLOAD_WIDTH : 7'h02 ,
LSU_SB_BITS : 9'h010 ,
LSU_STBUF_DEPTH : 8'h04 ,
NO_ICCM_NO_ICACHE : 5'h00 ,
PIC_2CYCLE : 5'h00 ,
PIC_BASE_ADDR : 36'h0F00C0000 ,
PIC_BITS : 9'h00F ,
PIC_INT_WORDS : 8'h01 ,
PIC_REGION : 8'h0F ,
PIC_SIZE : 13'h0020 ,
PIC_TOTAL_INT : 12'h01F ,
PIC_TOTAL_INT_PLUS1 : 13'h0020 ,
RET_STACK_SIZE : 8'h08 ,
SB_BUS_ID : 5'h01 ,
SB_BUS_PRTY : 6'h02 ,
SB_BUS_TAG : 8'h01 ,
TIMER_LEGAL_EN : 5'h01
}
// parameter el2_param_t pt = 2271'h04840400010040010840000020908200002840004808220A0C848200060210C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104020401C213860103C3C01000000400820428042010840830C2010281840200081002108E0C0801004040800C01002100400606810104100C0810084300800E0EE00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF8001080C080820080007806000003C043C04003E02008084021

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typedef struct packed {
bit [7:0] BHT_ADDR_HI;
bit [5:0] BHT_ADDR_LO;
bit [14:0] BHT_ARRAY_DEPTH;
bit [4:0] BHT_GHR_HASH_1;
bit [7:0] BHT_GHR_SIZE;
bit [15:0] BHT_SIZE;
bit [4:0] BITMANIP_ZBA;
bit [4:0] BITMANIP_ZBB;
bit [4:0] BITMANIP_ZBC;
bit [4:0] BITMANIP_ZBE;
bit [4:0] BITMANIP_ZBF;
bit [4:0] BITMANIP_ZBP;
bit [4:0] BITMANIP_ZBR;
bit [4:0] BITMANIP_ZBS;
bit [8:0] BTB_ADDR_HI;
bit [5:0] BTB_ADDR_LO;
bit [12:0] BTB_ARRAY_DEPTH;
bit [4:0] BTB_BTAG_FOLD;
bit [8:0] BTB_BTAG_SIZE;
bit [4:0] BTB_ENABLE;
bit [4:0] BTB_FOLD2_INDEX_HASH;
bit [4:0] BTB_FULLYA;
bit [8:0] BTB_INDEX1_HI;
bit [8:0] BTB_INDEX1_LO;
bit [8:0] BTB_INDEX2_HI;
bit [8:0] BTB_INDEX2_LO;
bit [8:0] BTB_INDEX3_HI;
bit [8:0] BTB_INDEX3_LO;
bit [13:0] BTB_SIZE;
bit [8:0] BTB_TOFFSET_SIZE;
bit BUILD_AHB_LITE;
bit [4:0] BUILD_AXI4;
bit [4:0] BUILD_AXI_NATIVE;
bit [5:0] BUS_PRTY_DEFAULT;
bit [35:0] DATA_ACCESS_ADDR0;
bit [35:0] DATA_ACCESS_ADDR1;
bit [35:0] DATA_ACCESS_ADDR2;
bit [35:0] DATA_ACCESS_ADDR3;
bit [35:0] DATA_ACCESS_ADDR4;
bit [35:0] DATA_ACCESS_ADDR5;
bit [35:0] DATA_ACCESS_ADDR6;
bit [35:0] DATA_ACCESS_ADDR7;
bit [4:0] DATA_ACCESS_ENABLE0;
bit [4:0] DATA_ACCESS_ENABLE1;
bit [4:0] DATA_ACCESS_ENABLE2;
bit [4:0] DATA_ACCESS_ENABLE3;
bit [4:0] DATA_ACCESS_ENABLE4;
bit [4:0] DATA_ACCESS_ENABLE5;
bit [4:0] DATA_ACCESS_ENABLE6;
bit [4:0] DATA_ACCESS_ENABLE7;
bit [35:0] DATA_ACCESS_MASK0;
bit [35:0] DATA_ACCESS_MASK1;
bit [35:0] DATA_ACCESS_MASK2;
bit [35:0] DATA_ACCESS_MASK3;
bit [35:0] DATA_ACCESS_MASK4;
bit [35:0] DATA_ACCESS_MASK5;
bit [35:0] DATA_ACCESS_MASK6;
bit [35:0] DATA_ACCESS_MASK7;
bit [6:0] DCCM_BANK_BITS;
bit [8:0] DCCM_BITS;
bit [6:0] DCCM_BYTE_WIDTH;
bit [9:0] DCCM_DATA_WIDTH;
bit [6:0] DCCM_ECC_WIDTH;
bit [4:0] DCCM_ENABLE;
bit [9:0] DCCM_FDATA_WIDTH;
bit [7:0] DCCM_INDEX_BITS;
bit [8:0] DCCM_NUM_BANKS;
bit [7:0] DCCM_REGION;
bit [35:0] DCCM_SADR;
bit [13:0] DCCM_SIZE;
bit [5:0] DCCM_WIDTH_BITS;
bit [6:0] DIV_BIT;
bit [4:0] DIV_NEW;
bit [6:0] DMA_BUF_DEPTH;
bit [8:0] DMA_BUS_ID;
bit [5:0] DMA_BUS_PRTY;
bit [7:0] DMA_BUS_TAG;
bit [4:0] FAST_INTERRUPT_REDIRECT;
bit [4:0] ICACHE_2BANKS;
bit [6:0] ICACHE_BANK_BITS;
bit [6:0] ICACHE_BANK_HI;
bit [5:0] ICACHE_BANK_LO;
bit [7:0] ICACHE_BANK_WIDTH;
bit [6:0] ICACHE_BANKS_WAY;
bit [7:0] ICACHE_BEAT_ADDR_HI;
bit [7:0] ICACHE_BEAT_BITS;
bit [4:0] ICACHE_BYPASS_ENABLE;
bit [17:0] ICACHE_DATA_DEPTH;
bit [6:0] ICACHE_DATA_INDEX_LO;
bit [10:0] ICACHE_DATA_WIDTH;
bit [4:0] ICACHE_ECC;
bit [4:0] ICACHE_ENABLE;
bit [10:0] ICACHE_FDATA_WIDTH;
bit [8:0] ICACHE_INDEX_HI;
bit [10:0] ICACHE_LN_SZ;
bit [7:0] ICACHE_NUM_BEATS;
bit [7:0] ICACHE_NUM_BYPASS;
bit [7:0] ICACHE_NUM_BYPASS_WIDTH;
bit [6:0] ICACHE_NUM_WAYS;
bit [4:0] ICACHE_ONLY;
bit [7:0] ICACHE_SCND_LAST;
bit [12:0] ICACHE_SIZE;
bit [6:0] ICACHE_STATUS_BITS;
bit [4:0] ICACHE_TAG_BYPASS_ENABLE;
bit [16:0] ICACHE_TAG_DEPTH;
bit [6:0] ICACHE_TAG_INDEX_LO;
bit [8:0] ICACHE_TAG_LO;
bit [7:0] ICACHE_TAG_NUM_BYPASS;
bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH;
bit [4:0] ICACHE_WAYPACK;
bit [6:0] ICCM_BANK_BITS;
bit [8:0] ICCM_BANK_HI;
bit [8:0] ICCM_BANK_INDEX_LO;
bit [8:0] ICCM_BITS;
bit [4:0] ICCM_ENABLE;
bit [4:0] ICCM_ICACHE;
bit [7:0] ICCM_INDEX_BITS;
bit [8:0] ICCM_NUM_BANKS;
bit [4:0] ICCM_ONLY;
bit [7:0] ICCM_REGION;
bit [35:0] ICCM_SADR;
bit [13:0] ICCM_SIZE;
bit [4:0] IFU_BUS_ID;
bit [5:0] IFU_BUS_PRTY;
bit [7:0] IFU_BUS_TAG;
bit [35:0] INST_ACCESS_ADDR0;
bit [35:0] INST_ACCESS_ADDR1;
bit [35:0] INST_ACCESS_ADDR2;
bit [35:0] INST_ACCESS_ADDR3;
bit [35:0] INST_ACCESS_ADDR4;
bit [35:0] INST_ACCESS_ADDR5;
bit [35:0] INST_ACCESS_ADDR6;
bit [35:0] INST_ACCESS_ADDR7;
bit [4:0] INST_ACCESS_ENABLE0;
bit [4:0] INST_ACCESS_ENABLE1;
bit [4:0] INST_ACCESS_ENABLE2;
bit [4:0] INST_ACCESS_ENABLE3;
bit [4:0] INST_ACCESS_ENABLE4;
bit [4:0] INST_ACCESS_ENABLE5;
bit [4:0] INST_ACCESS_ENABLE6;
bit [4:0] INST_ACCESS_ENABLE7;
bit [35:0] INST_ACCESS_MASK0;
bit [35:0] INST_ACCESS_MASK1;
bit [35:0] INST_ACCESS_MASK2;
bit [35:0] INST_ACCESS_MASK3;
bit [35:0] INST_ACCESS_MASK4;
bit [35:0] INST_ACCESS_MASK5;
bit [35:0] INST_ACCESS_MASK6;
bit [35:0] INST_ACCESS_MASK7;
bit [4:0] LOAD_TO_USE_PLUS1;
bit [4:0] LSU2DMA;
bit [4:0] LSU_BUS_ID;
bit [5:0] LSU_BUS_PRTY;
bit [7:0] LSU_BUS_TAG;
bit [8:0] LSU_NUM_NBLOAD;
bit [6:0] LSU_NUM_NBLOAD_WIDTH;
bit [8:0] LSU_SB_BITS;
bit [7:0] LSU_STBUF_DEPTH;
bit [4:0] NO_ICCM_NO_ICACHE;
bit [4:0] PIC_2CYCLE;
bit [35:0] PIC_BASE_ADDR;
bit [8:0] PIC_BITS;
bit [7:0] PIC_INT_WORDS;
bit [7:0] PIC_REGION;
bit [12:0] PIC_SIZE;
bit [11:0] PIC_TOTAL_INT;
bit [12:0] PIC_TOTAL_INT_PLUS1;
bit [7:0] RET_STACK_SIZE;
bit [4:0] SB_BUS_ID;
bit [5:0] SB_BUS_PRTY;
bit [7:0] SB_BUS_TAG;
bit [4:0] TIMER_LEGAL_EN;
} el2_param_t;

28
tools/snapshots/default/link.ld Normal file
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/*
NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
cmd: swerv -target=default -set build_axi4
*/
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x80000000;
.text.init . : { *(.text.init) }
.text . : { *(.text) }
_end = .;
. = 0xd0580000;
.data.io . : { *(.data.io) }
. = 0xf0040000 ;
.data : ALIGN(0x800) { *(.*data) *(.rodata*)}
.bss : {BSS_START = .; *(.*bss)}
BSS_END = .;
STACK = ALIGN(16) + 0x1000;
. = 0xfffffff8; .data.ctl : { LONG(0xf0040000); LONG(STACK) }
}

10
tools/snapshots/default/pd_defines.vh Normal file
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
//
// cmd: swerv -target=default -set build_axi4
//
`include "common_defines.vh"
`undef RV_ASSERT_ON
`undef TEC_RV_ICG
`define RV_PHYSICAL 1

778
tools/snapshots/default/perl_configs.pl Normal file
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# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
# This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
#
# cmd: swerv -target=default -set build_axi4
#
# To use this in a perf script, use 'require $RV_ROOT/configs/config.pl'
# Reference the hash via $config{name}..
%config = (
'nmi_vec' => '0x11110000',
'numiregs' => '32',
'perf_events' => [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
30,
31,
32,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
54,
55,
56,
512,
513,
514,
515,
516
],
'bht' => {
'bht_ghr_range' => '7:0',
'bht_hash_string' => '{hashin[8+1:2]^ghr[8-1:0]}// cf2',
'bht_addr_hi' => 9,
'bht_ghr_size' => 8,
'bht_array_depth' => 256,
'bht_ghr_hash_1' => '',
'bht_size' => 512,
'bht_addr_lo' => '2'
},
'retstack' => {
'ret_stack_size' => '8'
},
'config_key' => '32\'hdeadbeef',
'even_odd_trigger_chains' => 'true',
'target' => 'default',
'dccm' => {
'dccm_offset' => '0x40000',
'dccm_region' => '0xf',
'dccm_eadr' => '0xf004ffff',
'dccm_size' => 64,
'dccm_sadr' => '0xf0040000',
'dccm_fdata_width' => 39,
'dccm_bank_bits' => 2,
'dccm_num_banks_4' => '',
'dccm_rows' => '4096',
'dccm_enable' => '1',
'dccm_index_bits' => 12,
'dccm_bits' => 16,
'dccm_num_banks' => '4',
'lsu_sb_bits' => 16,
'dccm_data_width' => 32,
'dccm_data_cell' => 'ram_4096x39',
'dccm_reserved' => '0x1400',
'dccm_size_64' => '',
'dccm_ecc_width' => 7,
'dccm_width_bits' => 2,
'dccm_byte_width' => '4'
},
'max_mmode_perf_event' => '516',
'regwidth' => '32',
'reset_vec' => '0x80000000',
'core' => {
'lsu_stbuf_depth' => '4',
'bitmanip_zbr' => 0,
'bitmanip_zbs' => 1,
'bitmanip_zbf' => 0,
'fpga_optimize' => 1,
'icache_only' => 'derived',
'dma_buf_depth' => '5',
'bitmanip_zbc' => 1,
'bitmanip_zbe' => 0,
'iccm_icache' => 1,
'fast_interrupt_redirect' => '1',
'lsu_num_nbload' => '4',
'iccm_only' => 'derived',
'bitmanip_zba' => 1,
'bitmanip_zbp' => 0,
'lsu2dma' => 0,
'lsu_num_nbload_width' => '2',
'div_bit' => '4',
'bitmanip_zbb' => 1,
'no_iccm_no_icache' => 'derived',
'timer_legal_en' => '1',
'div_new' => 1
},
'memmap' => {
'unused_region8' => '0x00000000',
'unused_region2' => '0x60000000',
'unused_region1' => '0x70000000',
'unused_region5' => '0x30000000',
'unused_region4' => '0x40000000',
'serialio' => '0xd0580000',
'external_data' => '0xc0580000',
'external_data_1' => '0xb0000000',
'unused_region0' => '0x90000000',
'unused_region3' => '0x50000000',
'consoleio' => '0xd0580000',
'unused_region7' => '0x10000000',
'debug_sb_mem' => '0xa0580000',
'unused_region6' => '0x20000000'
},
'iccm' => {
'iccm_num_banks' => '4',
'iccm_bits' => 16,
'iccm_index_bits' => 12,
'iccm_enable' => 1,
'iccm_size_64' => '',
'iccm_data_cell' => 'ram_4096x39',
'iccm_reserved' => '0x1000',
'iccm_bank_index_lo' => 4,
'iccm_sadr' => '0xee000000',
'iccm_eadr' => '0xee00ffff',
'iccm_offset' => '0xe000000',
'iccm_region' => '0xe',
'iccm_size' => 64,
'iccm_num_banks_4' => '',
'iccm_rows' => '4096',
'iccm_bank_hi' => 3,
'iccm_bank_bits' => 2
},
'pic' => {
'pic_meipl_mask' => '0xf',
'pic_meipl_count' => 31,
'pic_meie_count' => 31,
'pic_meip_mask' => '0x0',
'pic_meipt_offset' => '0x3004',
'pic_region' => '0xf',
'pic_total_int' => 31,
'pic_meigwctrl_offset' => '0x4000',
'pic_meip_count' => 1,
'pic_meie_mask' => '0x1',
'pic_mpiccfg_offset' => '0x3000',
'pic_meigwclr_mask' => '0x0',
'pic_meigwclr_count' => 31,
'pic_int_words' => 1,
'pic_offset' => '0xc0000',
'pic_meip_offset' => '0x1000',
'pic_bits' => 15,
'pic_mpiccfg_count' => 1,
'pic_meigwclr_offset' => '0x5000',
'pic_size' => 32,
'pic_mpiccfg_mask' => '0x1',
'pic_total_int_plus1' => 32,
'pic_meipl_offset' => '0x0000',
'pic_meigwctrl_count' => 31,
'pic_base_addr' => '0xf00c0000',
'pic_meipt_mask' => '0x0',
'pic_meie_offset' => '0x2000',
'pic_meigwctrl_mask' => '0x3',
'pic_meipt_count' => 31
},
'protection' => {
'inst_access_addr2' => '0x00000000',
'data_access_mask6' => '0xffffffff',
'data_access_enable0' => '0x0',
'inst_access_enable4' => '0x0',
'inst_access_mask1' => '0xffffffff',
'inst_access_addr5' => '0x00000000',
'inst_access_enable1' => '0x0',
'inst_access_mask4' => '0xffffffff',
'data_access_addr2' => '0x00000000',
'inst_access_mask6' => '0xffffffff',
'inst_access_enable0' => '0x0',
'data_access_addr5' => '0x00000000',
'data_access_mask1' => '0xffffffff',
'data_access_enable4' => '0x0',
'data_access_enable1' => '0x0',
'data_access_mask4' => '0xffffffff',
'data_access_enable6' => '0x0',
'inst_access_mask7' => '0xffffffff',
'inst_access_enable5' => '0x0',
'data_access_mask0' => '0xffffffff',
'inst_access_addr3' => '0x00000000',
'inst_access_enable6' => '0x0',
'data_access_mask7' => '0xffffffff',
'data_access_enable5' => '0x0',
'inst_access_mask0' => '0xffffffff',
'data_access_addr3' => '0x00000000',
'data_access_enable3' => '0x0',
'data_access_addr0' => '0x00000000',
'inst_access_mask3' => '0xffffffff',
'data_access_enable2' => '0x0',
'inst_access_addr7' => '0x00000000',
'inst_access_enable3' => '0x0',
'inst_access_addr0' => '0x00000000',
'data_access_mask3' => '0xffffffff',
'data_access_addr7' => '0x00000000',
'inst_access_enable2' => '0x0',
'inst_access_mask5' => '0xffffffff',
'inst_access_addr1' => '0x00000000',
'inst_access_addr4' => '0x00000000',
'inst_access_mask2' => '0xffffffff',
'inst_access_enable7' => '0x0',
'data_access_addr6' => '0x00000000',
'data_access_addr1' => '0x00000000',
'data_access_mask5' => '0xffffffff',
'data_access_addr4' => '0x00000000',
'data_access_mask2' => '0xffffffff',
'data_access_enable7' => '0x0',
'inst_access_addr6' => '0x00000000'
},
'physical' => '1',
'bus' => {
'ifu_bus_prty' => '2',
'sb_bus_prty' => '2',
'lsu_bus_id' => '1',
'lsu_bus_tag' => 3,
'sb_bus_tag' => '1',
'dma_bus_id' => '1',
'dma_bus_tag' => '1',
'lsu_bus_prty' => '2',
'bus_prty_default' => '3',
'sb_bus_id' => '1',
'dma_bus_prty' => '2',
'ifu_bus_id' => '1',
'ifu_bus_tag' => '3'
},
'harts' => 1,
'xlen' => 32,
'btb' => {
'btb_index3_lo' => 18,
'btb_index1_lo' => '2',
'btb_addr_hi' => 9,
'btb_index2_lo' => 10,
'btb_size' => 512,
'btb_btag_fold' => 0,
'btb_addr_lo' => '2',
'btb_index2_hi' => 17,
'btb_enable' => '1',
'btb_toffset_size' => '12',
'btb_index3_hi' => 25,
'btb_array_depth' => 256,
'btb_btag_size' => 5,
'btb_index1_hi' => 9,
'btb_fold2_index_hash' => 0
},
'tec_rv_icg' => 'clockhdr',
'triggers' => [
{
'poke_mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
]
},
{
'poke_mask' => [
'0x081810c7',
'0xffffffff',
'0x00000000'
],
'mask' => [
'0x081810c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
]
},
{
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
],
'poke_mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
]
},
{
'poke_mask' => [
'0x081810c7',
'0xffffffff',
'0x00000000'
],
'mask' => [
'0x081810c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
]
}
],
'num_mmode_perf_regs' => '4',
'testbench' => {
'assert_on' => '',
'sterr_rollback' => '0',
'build_axi4' => 1,
'SDVT_AHB' => '0',
'ext_datawidth' => '64',
'ext_addrwidth' => '32',
'TOP' => 'tb_top',
'lderr_rollback' => '1',
'build_axi_native' => 1,
'RV_TOP' => '`TOP.rvtop',
'clock_period' => '100',
'CPU_TOP' => '`RV_TOP.swerv'
},
'icache' => {
'icache_index_hi' => 12,
'icache_tag_cell' => 'ram_128x25',
'icache_num_beats' => 8,
'icache_fdata_width' => 71,
'icache_num_bypass_width' => 2,
'icache_tag_depth' => 128,
'icache_tag_bypass_enable' => '1',
'icache_size' => 16,
'icache_tag_num_bypass' => '2',
'icache_bank_width' => 8,
'icache_data_index_lo' => 4,
'icache_2banks' => '1',
'icache_num_lines_bank' => '64',
'icache_ecc' => '1',
'icache_status_bits' => 1,
'icache_tag_num_bypass_width' => 2,
'icache_beat_bits' => 3,
'icache_data_width' => 64,
'icache_bypass_enable' => '1',
'icache_waypack' => '1',
'icache_num_bypass' => '2',
'icache_data_depth' => '512',
'icache_beat_addr_hi' => 5,
'icache_tag_lo' => 13,
'icache_bank_bits' => 1,
'icache_enable' => 1,
'icache_bank_hi' => 3,
'icache_num_lines' => 256,
'icache_tag_index_lo' => '6',
'icache_ln_sz' => 64,
'icache_num_lines_way' => '128',
'icache_data_cell' => 'ram_512x71',
'icache_banks_way' => 2,
'icache_num_ways' => 2,
'icache_scnd_last' => 6,
'icache_bank_lo' => 3
},
'csr' => {
'mip' => {
'exists' => 'true',
'mask' => '0x0',
'poke_mask' => '0x70000888',
'reset' => '0x0'
},
'mscause' => {
'mask' => '0x0000000f',
'reset' => '0x0',
'exists' => 'true',
'number' => '0x7ff'
},
'micect' => {
'exists' => 'true',
'number' => '0x7f0',
'mask' => '0xffffffff',
'reset' => '0x0'
},
'pmpaddr12' => {
'exists' => 'false'
},
'dicago' => {
'number' => '0x7cb',
'exists' => 'true',
'debug' => 'true',
'comment' => 'Cache diagnostics.',
'reset' => '0x0',
'mask' => '0x0'
},
'mrac' => {
'exists' => 'true',
'reset' => '0x0',
'comment' => 'Memory region io and cache control.',
'mask' => '0xffffffff',
'number' => '0x7c0',
'shared' => 'true'
},
'tselect' => {
'mask' => '0x3',
'reset' => '0x0',
'exists' => 'true'
},
'mhpmcounter4' => {
'reset' => '0x0',
'mask' => '0xffffffff',
'exists' => 'true'
},
'pmpcfg1' => {
'exists' => 'false'
},
'pmpaddr11' => {
'exists' => 'false'
},
'mimpid' => {
'mask' => '0x0',
'reset' => '0x4',
'exists' => 'true'
},
'pmpaddr2' => {
'exists' => 'false'
},
'mhpmevent6' => {
'exists' => 'true',
'reset' => '0x0',
'mask' => '0xffffffff'
},
'cycle' => {
'exists' => 'false'
},
'mitcnt1' => {
'number' => '0x7d5',
'exists' => 'true',
'reset' => '0x0',
'mask' => '0xffffffff'
},
'mcpc' => {
'number' => '0x7c2',
'exists' => 'true',
'mask' => '0x0',
'comment' => 'Core pause',
'reset' => '0x0'
},
'pmpaddr6' => {
'exists' => 'false'
},
'pmpaddr1' => {
'exists' => 'false'
},
'mhpmevent3' => {
'mask' => '0xffffffff',
'reset' => '0x0',
'exists' => 'true'
},
'mdccmect' => {
'mask' => '0xffffffff',
'reset' => '0x0',
'number' => '0x7f2',
'exists' => 'true'
},
'mitbnd0' => {
'number' => '0x7d3',
'exists' => 'true',
'mask' => '0xffffffff',
'reset' => '0xffffffff'
},
'instret' => {
'exists' => 'false'
},
'pmpaddr14' => {
'exists' => 'false'
},
'mvendorid' => {
'exists' => 'true',
'mask' => '0x0',
'reset' => '0x45'
},
'mhpmcounter3' => {
'reset' => '0x0',
'mask' => '0xffffffff',
'exists' => 'true'
},
'mfdhs' => {
'mask' => '0x00000003',
'comment' => 'Force Debug Halt Status',
'reset' => '0x0',
'number' => '0x7cf',
'exists' => 'true'
},
'dicad1' => {
'number' => '0x7ca',
'exists' => 'true',
'debug' => 'true',
'comment' => 'Cache diagnostics.',
'reset' => '0x0',
'mask' => '0x3'
},
'pmpcfg2' => {
'exists' => 'false'
},
'mhpmcounter4h' => {
'exists' => 'true',
'mask' => '0xffffffff',
'reset' => '0x0'
},
'mfdht' => {
'number' => '0x7ce',
'shared' => 'true',
'exists' => 'true',
'reset' => '0x0',
'comment' => 'Force Debug Halt Threshold',
'mask' => '0x0000003f'
},
'pmpaddr13' => {
'exists' => 'false'
},
'mhpmevent4' => {
'reset' => '0x0',
'mask' => '0xffffffff',
'exists' => 'true'
},
'mitctl1' => {
'mask' => '0x0000000f',
'reset' => '0x1',
'exists' => 'true',
'number' => '0x7d7'
},
'pmpaddr4' => {
'exists' => 'false'
},
'mie' => {
'exists' => 'true',
'reset' => '0x0',
'mask' => '0x70000888'
},
'mfdc' => {
'number' => '0x7f9',
'exists' => 'true',
'mask' => '0x00071fff',
'reset' => '0x00070040'
},
'pmpaddr9' => {
'exists' => 'false'
},
'pmpaddr0' => {
'exists' => 'false'
},
'mpmc' => {
'exists' => 'true',
'number' => '0x7c6',
'reset' => '0x2',
'mask' => '0x2'
},
'pmpaddr3' => {
'exists' => 'false'
},
'marchid' => {
'exists' => 'true',
'reset' => '0x00000010',
'mask' => '0x0'
},
'meicidpl' => {
'comment' => 'External interrupt claim id priority level.',
'reset' => '0x0',
'mask' => '0xf',
'number' => '0xbcb',
'exists' => 'true'
},
'mhpmcounter3h' => {
'exists' => 'true',
'reset' => '0x0',
'mask' => '0xffffffff'
},
'dmst' => {
'exists' => 'true',
'number' => '0x7c4',
'debug' => 'true',
'reset' => '0x0',
'comment' => 'Memory synch trigger: Flush caches in debug mode.',
'mask' => '0x0'
},
'mstatus' => {
'exists' => 'true',
'mask' => '0x88',
'reset' => '0x1800'
},
'dicad0' => {
'debug' => 'true',
'exists' => 'true',
'number' => '0x7c9',
'mask' => '0xffffffff',
'reset' => '0x0',
'comment' => 'Cache diagnostics.'
},
'mcgc' => {
'reset' => '0x200',
'poke_mask' => '0x000003ff',
'mask' => '0x000003ff',
'number' => '0x7f8',
'exists' => 'true'
},
'mhpmcounter5' => {
'reset' => '0x0',
'mask' => '0xffffffff',
'exists' => 'true'
},
'mhpmcounter6h' => {
'exists' => 'true',
'reset' => '0x0',
'mask' => '0xffffffff'
},
'mcounteren' => {
'exists' => 'false'
},
'misa' => {
'exists' => 'true',
'reset' => '0x40001104',
'mask' => '0x0'
},
'pmpcfg0' => {
'exists' => 'false'
},
'mcountinhibit' => {
'commnet' => 'Performance counter inhibit. One bit per counter.',
'exists' => 'true',
'poke_mask' => '0x7d',
'mask' => '0x7d',
'reset' => '0x0'
},
'dcsr' => {
'debug' => 'true',
'exists' => 'true',
'mask' => '0x00008c04',
'poke_mask' => '0x00008dcc',
'reset' => '0x40000003'
},
'time' => {
'exists' => 'false'
},
'mhpmevent5' => {
'exists' => 'true',
'mask' => '0xffffffff',
'reset' => '0x0'
},
'pmpaddr8' => {
'exists' => 'false'
},
'pmpcfg3' => {
'exists' => 'false'
},
'mitbnd1' => {
'mask' => '0xffffffff',
'reset' => '0xffffffff',
'exists' => 'true',
'number' => '0x7d6'
},
'mitcnt0' => {
'reset' => '0x0',
'mask' => '0xffffffff',
'number' => '0x7d2',
'exists' => 'true'
},
'miccmect' => {
'exists' => 'true',
'number' => '0x7f1',
'mask' => '0xffffffff',
'reset' => '0x0'
},
'mhpmcounter6' => {
'exists' => 'true',
'reset' => '0x0',
'mask' => '0xffffffff'
},
'mhpmcounter5h' => {
'exists' => 'true',
'reset' => '0x0',
'mask' => '0xffffffff'
},
'pmpaddr7' => {
'exists' => 'false'
},
'pmpaddr5' => {
'exists' => 'false'
},
'mitctl0' => {
'number' => '0x7d4',
'exists' => 'true',
'mask' => '0x00000007',
'reset' => '0x1'
},
'meicurpl' => {
'exists' => 'true',
'number' => '0xbcc',
'reset' => '0x0',
'comment' => 'External interrupt current priority level.',
'mask' => '0xf'
},
'pmpaddr10' => {
'exists' => 'false'
},
'meipt' => {
'exists' => 'true',
'number' => '0xbc9',
'reset' => '0x0',
'comment' => 'External interrupt priority threshold.',
'mask' => '0xf'
},
'pmpaddr15' => {
'exists' => 'false'
},
'dicawics' => {
'mask' => '0x0130fffc',
'reset' => '0x0',
'comment' => 'Cache diagnostics.',
'debug' => 'true',
'exists' => 'true',
'number' => '0x7c8'
},
'mhartid' => {
'exists' => 'true',
'mask' => '0x0',
'poke_mask' => '0xfffffff0',
'reset' => '0x0'
}
}
);
1;

100
tools/snapshots/default/pic_map_auto.h Normal file
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@ -0,0 +1,100 @@
// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }
always_comb begin
case (address[14:0])
15'b011000000000000 : mask[3:0] = 4'b0100;
15'b100000000000100 : mask[3:0] = 4'b1000;
15'b100000000001000 : mask[3:0] = 4'b1000;
15'b100000000001100 : mask[3:0] = 4'b1000;
15'b100000000010000 : mask[3:0] = 4'b1000;
15'b100000000010100 : mask[3:0] = 4'b1000;
15'b100000000011000 : mask[3:0] = 4'b1000;
15'b100000000011100 : mask[3:0] = 4'b1000;
15'b100000000100000 : mask[3:0] = 4'b1000;
15'b100000000100100 : mask[3:0] = 4'b1000;
15'b100000000101000 : mask[3:0] = 4'b1000;
15'b100000000101100 : mask[3:0] = 4'b1000;
15'b100000000110000 : mask[3:0] = 4'b1000;
15'b100000000110100 : mask[3:0] = 4'b1000;
15'b100000000111000 : mask[3:0] = 4'b1000;
15'b100000000111100 : mask[3:0] = 4'b1000;
15'b100000001000000 : mask[3:0] = 4'b1000;
15'b100000001000100 : mask[3:0] = 4'b1000;
15'b100000001001000 : mask[3:0] = 4'b1000;
15'b100000001001100 : mask[3:0] = 4'b1000;
15'b100000001010000 : mask[3:0] = 4'b1000;
15'b100000001010100 : mask[3:0] = 4'b1000;
15'b100000001011000 : mask[3:0] = 4'b1000;
15'b100000001011100 : mask[3:0] = 4'b1000;
15'b100000001100000 : mask[3:0] = 4'b1000;
15'b100000001100100 : mask[3:0] = 4'b1000;
15'b100000001101000 : mask[3:0] = 4'b1000;
15'b100000001101100 : mask[3:0] = 4'b1000;
15'b100000001110000 : mask[3:0] = 4'b1000;
15'b100000001110100 : mask[3:0] = 4'b1000;
15'b100000001111000 : mask[3:0] = 4'b1000;
15'b100000001111100 : mask[3:0] = 4'b1000;
15'b010000000000100 : mask[3:0] = 4'b0100;
15'b010000000001000 : mask[3:0] = 4'b0100;
15'b010000000001100 : mask[3:0] = 4'b0100;
15'b010000000010000 : mask[3:0] = 4'b0100;
15'b010000000010100 : mask[3:0] = 4'b0100;
15'b010000000011000 : mask[3:0] = 4'b0100;
15'b010000000011100 : mask[3:0] = 4'b0100;
15'b010000000100000 : mask[3:0] = 4'b0100;
15'b010000000100100 : mask[3:0] = 4'b0100;
15'b010000000101000 : mask[3:0] = 4'b0100;
15'b010000000101100 : mask[3:0] = 4'b0100;
15'b010000000110000 : mask[3:0] = 4'b0100;
15'b010000000110100 : mask[3:0] = 4'b0100;
15'b010000000111000 : mask[3:0] = 4'b0100;
15'b010000000111100 : mask[3:0] = 4'b0100;
15'b010000001000000 : mask[3:0] = 4'b0100;
15'b010000001000100 : mask[3:0] = 4'b0100;
15'b010000001001000 : mask[3:0] = 4'b0100;
15'b010000001001100 : mask[3:0] = 4'b0100;
15'b010000001010000 : mask[3:0] = 4'b0100;
15'b010000001010100 : mask[3:0] = 4'b0100;
15'b010000001011000 : mask[3:0] = 4'b0100;
15'b010000001011100 : mask[3:0] = 4'b0100;
15'b010000001100000 : mask[3:0] = 4'b0100;
15'b010000001100100 : mask[3:0] = 4'b0100;
15'b010000001101000 : mask[3:0] = 4'b0100;
15'b010000001101100 : mask[3:0] = 4'b0100;
15'b010000001110000 : mask[3:0] = 4'b0100;
15'b010000001110100 : mask[3:0] = 4'b0100;
15'b010000001111000 : mask[3:0] = 4'b0100;
15'b010000001111100 : mask[3:0] = 4'b0100;
15'b000000000000100 : mask[3:0] = 4'b0010;
15'b000000000001000 : mask[3:0] = 4'b0010;
15'b000000000001100 : mask[3:0] = 4'b0010;
15'b000000000010000 : mask[3:0] = 4'b0010;
15'b000000000010100 : mask[3:0] = 4'b0010;
15'b000000000011000 : mask[3:0] = 4'b0010;
15'b000000000011100 : mask[3:0] = 4'b0010;
15'b000000000100000 : mask[3:0] = 4'b0010;
15'b000000000100100 : mask[3:0] = 4'b0010;
15'b000000000101000 : mask[3:0] = 4'b0010;
15'b000000000101100 : mask[3:0] = 4'b0010;
15'b000000000110000 : mask[3:0] = 4'b0010;
15'b000000000110100 : mask[3:0] = 4'b0010;
15'b000000000111000 : mask[3:0] = 4'b0010;
15'b000000000111100 : mask[3:0] = 4'b0010;
15'b000000001000000 : mask[3:0] = 4'b0010;
15'b000000001000100 : mask[3:0] = 4'b0010;
15'b000000001001000 : mask[3:0] = 4'b0010;
15'b000000001001100 : mask[3:0] = 4'b0010;
15'b000000001010000 : mask[3:0] = 4'b0010;
15'b000000001010100 : mask[3:0] = 4'b0010;
15'b000000001011000 : mask[3:0] = 4'b0010;
15'b000000001011100 : mask[3:0] = 4'b0010;
15'b000000001100000 : mask[3:0] = 4'b0010;
15'b000000001100100 : mask[3:0] = 4'b0010;
15'b000000001101000 : mask[3:0] = 4'b0010;
15'b000000001101100 : mask[3:0] = 4'b0010;
15'b000000001110000 : mask[3:0] = 4'b0010;
15'b000000001110100 : mask[3:0] = 4'b0010;
15'b000000001111000 : mask[3:0] = 4'b0010;
15'b000000001111100 : mask[3:0] = 4'b0010;
default : mask[3:0] = 4'b0001;
endcase
end

566
tools/snapshots/default/whisper.json Normal file
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@ -0,0 +1,566 @@
{
"enable_zbs" : 1,
"nmi_vec" : "0x11110000",
"enable_zbc" : 1,
"effective_address_compatible_with_base" : "true",
"mmode_perf_events" : [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
30,
31,
32,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
54,
55,
56,
512,
513,
514,
515,
516
],
"even_odd_trigger_chains" : "true",
"max_mmode_perf_event" : "516",
"dccm" : {
"offset" : "0x40000",
"size" : "0x10000",
"region" : "0xf"
},
"reset_vec" : "0x80000000",
"enable_zbp" : 0,
"enable_zbb" : 1,
"store_error_rollback" : "0",
"memmap" : {
"serialio" : "0xd0580000",
"consoleio" : "0xd0580000"
},
"harts" : 1,
"xlen" : 32,
"enable_zbe" : 0,
"enable_zbr" : 0,
"amo_illegal_outside_dccm" : "true",
"iccm" : {
"region" : "0xe",
"size" : "0x10000",
"offset" : "0xe000000"
},
"enable_zba" : 1,
"num_mmode_perf_regs" : "4",
"enable_zbf" : 0,
"load_error_rollback" : "1",
"triggers" : [
{
"poke_mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
]
},
{
"poke_mask" : [
"0x081810c7",
"0xffffffff",
"0x00000000"
],
"mask" : [
"0x081810c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
]
},
{
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
],
"poke_mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
]
},
{
"poke_mask" : [
"0x081810c7",
"0xffffffff",
"0x00000000"
],
"mask" : [
"0x081810c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
]
}
],
"fast_interrupt_redirect" : "1",
"csr" : {
"mip" : {
"exists" : "true",
"mask" : "0x0",
"poke_mask" : "0x70000888",
"reset" : "0x0"
},
"mscause" : {
"mask" : "0x0000000f",
"reset" : "0x0",
"exists" : "true",
"number" : "0x7ff"
},
"micect" : {
"exists" : "true",
"number" : "0x7f0",
"mask" : "0xffffffff",
"reset" : "0x0"
},
"pmpaddr12" : {
"exists" : "false"
},
"dicago" : {
"number" : "0x7cb",
"exists" : "true",
"debug" : "true",
"comment" : "Cache diagnostics.",
"reset" : "0x0",
"mask" : "0x0"
},
"mrac" : {
"exists" : "true",
"reset" : "0x0",
"comment" : "Memory region io and cache control.",
"mask" : "0xffffffff",
"number" : "0x7c0",
"shared" : "true"
},
"tselect" : {
"mask" : "0x3",
"reset" : "0x0",
"exists" : "true"
},
"mhpmcounter4" : {
"reset" : "0x0",
"mask" : "0xffffffff",
"exists" : "true"
},
"pmpcfg1" : {
"exists" : "false"
},
"pmpaddr11" : {
"exists" : "false"
},
"mimpid" : {
"mask" : "0x0",
"reset" : "0x4",
"exists" : "true"
},
"pmpaddr2" : {
"exists" : "false"
},
"mhpmevent6" : {
"exists" : "true",
"reset" : "0x0",
"mask" : "0xffffffff"
},
"cycle" : {
"exists" : "false"
},
"mitcnt1" : {
"number" : "0x7d5",
"exists" : "true",
"reset" : "0x0",
"mask" : "0xffffffff"
},
"mcpc" : {
"number" : "0x7c2",
"exists" : "true",
"mask" : "0x0",
"comment" : "Core pause",
"reset" : "0x0"
},
"pmpaddr6" : {
"exists" : "false"
},
"pmpaddr1" : {
"exists" : "false"
},
"mhpmevent3" : {
"mask" : "0xffffffff",
"reset" : "0x0",
"exists" : "true"
},
"mdccmect" : {
"mask" : "0xffffffff",
"reset" : "0x0",
"number" : "0x7f2",
"exists" : "true"
},
"mitbnd0" : {
"number" : "0x7d3",
"exists" : "true",
"mask" : "0xffffffff",
"reset" : "0xffffffff"
},
"instret" : {
"exists" : "false"
},
"pmpaddr14" : {
"exists" : "false"
},
"mvendorid" : {
"exists" : "true",
"mask" : "0x0",
"reset" : "0x45"
},
"mhpmcounter3" : {
"reset" : "0x0",
"mask" : "0xffffffff",
"exists" : "true"
},
"mfdhs" : {
"mask" : "0x00000003",
"comment" : "Force Debug Halt Status",
"reset" : "0x0",
"number" : "0x7cf",
"exists" : "true"
},
"dicad1" : {
"number" : "0x7ca",
"exists" : "true",
"debug" : "true",
"comment" : "Cache diagnostics.",
"reset" : "0x0",
"mask" : "0x3"
},
"pmpcfg2" : {
"exists" : "false"
},
"mhpmcounter4h" : {
"exists" : "true",
"mask" : "0xffffffff",
"reset" : "0x0"
},
"mfdht" : {
"number" : "0x7ce",
"shared" : "true",
"exists" : "true",
"reset" : "0x0",
"comment" : "Force Debug Halt Threshold",
"mask" : "0x0000003f"
},
"pmpaddr13" : {
"exists" : "false"
},
"mhpmevent4" : {
"reset" : "0x0",
"mask" : "0xffffffff",
"exists" : "true"
},
"mitctl1" : {
"mask" : "0x0000000f",
"reset" : "0x1",
"exists" : "true",
"number" : "0x7d7"
},
"pmpaddr4" : {
"exists" : "false"
},
"mie" : {
"exists" : "true",
"reset" : "0x0",
"mask" : "0x70000888"
},
"mfdc" : {
"number" : "0x7f9",
"exists" : "true",
"mask" : "0x00071fff",
"reset" : "0x00070040"
},
"pmpaddr9" : {
"exists" : "false"
},
"pmpaddr0" : {
"exists" : "false"
},
"mpmc" : {
"exists" : "true",
"number" : "0x7c6",
"reset" : "0x2",
"mask" : "0x2"
},
"pmpaddr3" : {
"exists" : "false"
},
"marchid" : {
"exists" : "true",
"reset" : "0x00000010",
"mask" : "0x0"
},
"meicidpl" : {
"comment" : "External interrupt claim id priority level.",
"reset" : "0x0",
"mask" : "0xf",
"number" : "0xbcb",
"exists" : "true"
},
"mhpmcounter3h" : {
"exists" : "true",
"reset" : "0x0",
"mask" : "0xffffffff"
},
"dmst" : {
"exists" : "true",
"number" : "0x7c4",
"debug" : "true",
"reset" : "0x0",
"comment" : "Memory synch trigger: Flush caches in debug mode.",
"mask" : "0x0"
},
"mstatus" : {
"exists" : "true",
"mask" : "0x88",
"reset" : "0x1800"
},
"dicad0" : {
"debug" : "true",
"exists" : "true",
"number" : "0x7c9",
"mask" : "0xffffffff",
"reset" : "0x0",
"comment" : "Cache diagnostics."
},
"mcgc" : {
"reset" : "0x200",
"poke_mask" : "0x000003ff",
"mask" : "0x000003ff",
"number" : "0x7f8",
"exists" : "true"
},
"mhpmcounter5" : {
"reset" : "0x0",
"mask" : "0xffffffff",
"exists" : "true"
},
"mhpmcounter6h" : {
"exists" : "true",
"reset" : "0x0",
"mask" : "0xffffffff"
},
"mcounteren" : {
"exists" : "false"
},
"misa" : {
"exists" : "true",
"reset" : "0x40001104",
"mask" : "0x0"
},
"pmpcfg0" : {
"exists" : "false"
},
"mcountinhibit" : {
"commnet" : "Performance counter inhibit. One bit per counter.",
"exists" : "true",
"poke_mask" : "0x7d",
"mask" : "0x7d",
"reset" : "0x0"
},
"dcsr" : {
"debug" : "true",
"exists" : "true",
"mask" : "0x00008c04",
"poke_mask" : "0x00008dcc",
"reset" : "0x40000003"
},
"time" : {
"exists" : "false"
},
"mhpmevent5" : {
"exists" : "true",
"mask" : "0xffffffff",
"reset" : "0x0"
},
"pmpaddr8" : {
"exists" : "false"
},
"pmpcfg3" : {
"exists" : "false"
},
"mitbnd1" : {
"mask" : "0xffffffff",
"reset" : "0xffffffff",
"exists" : "true",
"number" : "0x7d6"
},
"mitcnt0" : {
"reset" : "0x0",
"mask" : "0xffffffff",
"number" : "0x7d2",
"exists" : "true"
},
"miccmect" : {
"exists" : "true",
"number" : "0x7f1",
"mask" : "0xffffffff",
"reset" : "0x0"
},
"mhpmcounter6" : {
"exists" : "true",
"reset" : "0x0",
"mask" : "0xffffffff"
},
"mhpmcounter5h" : {
"exists" : "true",
"reset" : "0x0",
"mask" : "0xffffffff"
},
"pmpaddr7" : {
"exists" : "false"
},
"pmpaddr5" : {
"exists" : "false"
},
"mitctl0" : {
"number" : "0x7d4",
"exists" : "true",
"mask" : "0x00000007",
"reset" : "0x1"
},
"meicurpl" : {
"exists" : "true",
"number" : "0xbcc",
"reset" : "0x0",
"comment" : "External interrupt current priority level.",
"mask" : "0xf"
},
"pmpaddr10" : {
"exists" : "false"
},
"meipt" : {
"exists" : "true",
"number" : "0xbc9",
"reset" : "0x0",
"comment" : "External interrupt priority threshold.",
"mask" : "0xf"
},
"pmpaddr15" : {
"exists" : "false"
},
"dicawics" : {
"mask" : "0x0130fffc",
"reset" : "0x0",
"comment" : "Cache diagnostics.",
"debug" : "true",
"exists" : "true",
"number" : "0x7c8"
},
"mhartid" : {
"exists" : "true",
"mask" : "0x0",
"poke_mask" : "0xfffffff0",
"reset" : "0x0"
}
},
"memory_mapped_registers" : {
"registers" : {
"meigwclr" : {
"mask" : "0x0",
"address" : "0xf00c5004",
"count" : 31
},
"meigwctrl" : {
"mask" : "0x3",
"address" : "0xf00c4004",
"count" : 31
},
"meip" : {
"mask" : "0x0",
"address" : "0xf00c1000",
"count" : 1
},
"meie" : {
"count" : 31,
"address" : "0xf00c2004",
"mask" : "0x1"
},
"meipl" : {
"mask" : "0xf",
"address" : "0xf00c0004",
"count" : 31
},
"mpiccfg" : {
"count" : 1,
"address" : "0xf00c3000",
"mask" : "0x1"
}
},
"default_mask" : 0,
"address" : "0xf00c0000",
"size" : "0x8000"
}
}

0
tools/verilator-build Normal file
View File