Move demo/build to demo.
This commit is contained in:
colin
parent
94c3d5f8ad
commit
e98bbf2deb
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@ -1,4 +1,4 @@
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export RV_ROOT = ${PWD}/../..
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export RV_ROOT = ${PWD}/..
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GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
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GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
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@ -0,0 +1,246 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by colin on Wed Mar 23 01:03:51 PM UTC 2022
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//
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// cmd: swerv -target=default -set build_axi4
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//
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`define RV_ROOT "/home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/.."
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`define RV_NUMIREGS 32
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`define RV_TOP `TOP.rvtop
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`define RV_BUILD_AXI_NATIVE 1
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`define CPU_TOP `RV_TOP.swerv
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`define RV_STERR_ROLLBACK 0
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`define SDVT_AHB 0
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`define RV_ASSERT_ON
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`define CLOCK_PERIOD 100
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`define RV_EXT_DATAWIDTH 64
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`define RV_LDERR_ROLLBACK 1
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`define RV_BUILD_AXI4 1
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`define TOP tb_top
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`define RV_EXT_ADDRWIDTH 32
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`define RV_INST_ACCESS_MASK1 'hffffffff
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`define RV_INST_ACCESS_MASK3 'hffffffff
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`define RV_DATA_ACCESS_ENABLE4 1'h0
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`define RV_DATA_ACCESS_MASK3 'hffffffff
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`define RV_INST_ACCESS_ENABLE4 1'h0
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`define RV_DATA_ACCESS_MASK1 'hffffffff
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`define RV_INST_ACCESS_ADDR3 'h00000000
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`define RV_INST_ACCESS_ENABLE7 1'h0
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`define RV_INST_ACCESS_ADDR1 'h00000000
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`define RV_DATA_ACCESS_ADDR1 'h00000000
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`define RV_DATA_ACCESS_ADDR3 'h00000000
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`define RV_DATA_ACCESS_ENABLE7 1'h0
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`define RV_INST_ACCESS_ENABLE0 1'h0
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`define RV_DATA_ACCESS_ADDR5 'h00000000
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`define RV_INST_ACCESS_ADDR0 'h00000000
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`define RV_INST_ACCESS_ADDR5 'h00000000
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`define RV_DATA_ACCESS_ADDR0 'h00000000
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`define RV_DATA_ACCESS_ENABLE0 1'h0
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`define RV_DATA_ACCESS_MASK5 'hffffffff
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`define RV_INST_ACCESS_MASK0 'hffffffff
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`define RV_DATA_ACCESS_ENABLE6 1'h0
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`define RV_DATA_ACCESS_ENABLE2 1'h0
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`define RV_INST_ACCESS_ENABLE1 1'h0
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`define RV_INST_ACCESS_ENABLE6 1'h0
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`define RV_DATA_ACCESS_ENABLE1 1'h0
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`define RV_INST_ACCESS_ENABLE2 1'h0
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`define RV_INST_ACCESS_MASK5 'hffffffff
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`define RV_DATA_ACCESS_MASK0 'hffffffff
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`define RV_INST_ACCESS_MASK6 'hffffffff
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`define RV_INST_ACCESS_ADDR4 'h00000000
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`define RV_DATA_ACCESS_ADDR7 'h00000000
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`define RV_INST_ACCESS_ADDR7 'h00000000
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`define RV_DATA_ACCESS_ADDR4 'h00000000
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`define RV_DATA_ACCESS_MASK6 'hffffffff
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`define RV_DATA_ACCESS_ENABLE5 1'h0
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`define RV_DATA_ACCESS_MASK7 'hffffffff
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`define RV_INST_ACCESS_ENABLE3 1'h0
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`define RV_INST_ACCESS_ADDR6 'h00000000
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`define RV_INST_ACCESS_MASK4 'hffffffff
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`define RV_DATA_ACCESS_MASK4 'hffffffff
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`define RV_DATA_ACCESS_ADDR6 'h00000000
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`define RV_INST_ACCESS_MASK7 'hffffffff
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`define RV_INST_ACCESS_ENABLE5 1'h0
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`define RV_DATA_ACCESS_ENABLE3 1'h0
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`define RV_INST_ACCESS_ADDR2 'h00000000
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`define RV_DATA_ACCESS_ADDR2 'h00000000
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`define RV_INST_ACCESS_MASK2 'hffffffff
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`define RV_DATA_ACCESS_MASK2 'hffffffff
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`define RV_ICCM_BANK_INDEX_LO 5
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`define RV_ICCM_DATA_CELL ram_1024x39
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`define RV_ICCM_SADR 32'hee000000
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`define RV_ICCM_NUM_BANKS_8
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`define RV_ICCM_SIZE 32
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`define RV_ICCM_BANK_BITS 3
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`define RV_ICCM_ROWS 1024
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`define RV_ICCM_EADR 32'hee007fff
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`define RV_ICCM_SIZE_32
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`define RV_ICCM_INDEX_BITS 10
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`define RV_ICCM_BITS 15
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`define RV_ICCM_NUM_BANKS 8
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`define RV_ICCM_RESERVED 'h1000
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`define RV_ICCM_REGION 4'he
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`define RV_ICCM_OFFSET 10'he000000
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`define RV_ICCM_BANK_HI 4
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`define RV_TARGET default
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`define RV_RET_STACK_SIZE 4
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`define RV_UNUSED_REGION7 'h10000000
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`define RV_DEBUG_SB_MEM 'ha0580000
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`define RV_UNUSED_REGION8 'h00000000
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`define RV_UNUSED_REGION4 'h40000000
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`define RV_UNUSED_REGION0 'h90000000
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`define RV_UNUSED_REGION3 'h50000000
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`define RV_SERIALIO 'hd0580000
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`define RV_EXTERNAL_DATA_1 'hb0000000
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`define RV_UNUSED_REGION2 'h60000000
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`define RV_UNUSED_REGION5 'h30000000
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`define RV_UNUSED_REGION6 'h20000000
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`define RV_EXTERNAL_DATA 'hc0580000
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`define RV_UNUSED_REGION1 'h70000000
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`define RV_XLEN 32
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`define RV_BTB_ARRAY_DEPTH 16
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`define RV_BTB_INDEX1_LO 2
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`define RV_BTB_FOLD2_INDEX_HASH 0
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`define RV_BTB_INDEX3_LO 10
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`define RV_BTB_TOFFSET_SIZE 12
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`define RV_BTB_INDEX2_LO 6
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`define RV_BTB_BTAG_SIZE 9
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`define RV_BTB_ENABLE 1
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`define RV_BTB_ADDR_LO 2
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`define RV_BTB_INDEX3_HI 13
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`define RV_BTB_INDEX2_HI 9
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`define RV_BTB_BTAG_FOLD 1
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`define RV_BTB_SIZE 32
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`define RV_BTB_ADDR_HI 5
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`define RV_BTB_INDEX1_HI 5
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`define TEC_RV_ICG clockhdr
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`define RV_BHT_ADDR_HI 7
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`define RV_BHT_SIZE 128
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`define RV_BHT_GHR_SIZE 6
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`define RV_BHT_ARRAY_DEPTH 64
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`define RV_BHT_GHR_HASH_1 1
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`define RV_BHT_ADDR_LO 2
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`define RV_BHT_HASH_STRING {ghr[5:4], hashin[5:2]^ghr[4-1:0]} // cf1
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`define RV_BHT_GHR_RANGE 5:0
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`define RV_DCCM_ROWS 1024
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`define RV_DCCM_SADR 32'hf0040000
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`define RV_DCCM_DATA_CELL ram_1024x39
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`define RV_DCCM_BANK_BITS 3
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`define RV_DCCM_NUM_BANKS_8
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`define RV_DCCM_SIZE 32
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`define RV_DCCM_ENABLE 1
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`define RV_DCCM_FDATA_WIDTH 39
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`define RV_DCCM_OFFSET 28'h40000
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`define RV_DCCM_RESERVED 'h1400
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`define RV_DCCM_DATA_WIDTH 32
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`define RV_DCCM_ECC_WIDTH 7
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`define RV_DCCM_REGION 4'hf
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`define RV_DCCM_BITS 15
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`define RV_LSU_SB_BITS 15
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`define RV_DCCM_INDEX_BITS 10
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`define RV_DCCM_WIDTH_BITS 2
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`define RV_DCCM_NUM_BANKS 8
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`define RV_DCCM_EADR 32'hf0047fff
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`define RV_DCCM_BYTE_WIDTH 4
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`define RV_DCCM_SIZE_32
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`define RV_CONFIG_KEY 32'hdeadbeef
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`define REGWIDTH 32
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`define RV_SB_BUS_ID 1
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`define RV_SB_BUS_PRTY 2
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`define RV_SB_BUS_TAG 1
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`define RV_BUS_PRTY_DEFAULT 2'h3
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`define RV_LSU_BUS_ID 1
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`define RV_LSU_BUS_PRTY 2
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`define RV_LSU_BUS_TAG 3
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`define RV_IFU_BUS_ID 1
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`define RV_DMA_BUS_TAG 1
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`define RV_IFU_BUS_PRTY 2
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`define RV_IFU_BUS_TAG 3
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`define RV_DMA_BUS_ID 1
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`define RV_DMA_BUS_PRTY 2
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`define RV_NMI_VEC 'h11110000
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`define RV_ICACHE_TAG_BYPASS_ENABLE 1
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`define RV_ICACHE_BANKS_WAY 2
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`define RV_ICACHE_DATA_INDEX_LO 4
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`define RV_ICACHE_TAG_NUM_BYPASS_WIDTH 2
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`define RV_ICACHE_TAG_LO 13
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`define RV_ICACHE_SIZE 16
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`define RV_ICACHE_NUM_LINES_BANK 64
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`define RV_ICACHE_BYPASS_ENABLE 1
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`define RV_ICACHE_DATA_CELL ram_512x68
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`define RV_ICACHE_BANK_HI 3
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`define RV_ICACHE_BANK_LO 3
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`define RV_ICACHE_DATA_WIDTH 64
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`define RV_ICACHE_TAG_CELL ram_128x21
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`define RV_ICACHE_STATUS_BITS 1
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`define RV_ICACHE_TAG_DEPTH 128
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`define RV_ICACHE_BANK_BITS 1
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`define RV_ICACHE_NUM_LINES_WAY 128
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`define RV_ICACHE_BANK_WIDTH 8
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`define RV_ICACHE_NUM_BYPASS 2
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`define RV_ICACHE_LN_SZ 64
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`define RV_ICACHE_WAYPACK 1
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`define RV_ICACHE_NUM_BYPASS_WIDTH 2
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`define RV_ICACHE_TAG_INDEX_LO 6
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`define RV_ICACHE_ECC 0
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`define RV_ICACHE_NUM_LINES 256
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`define RV_ICACHE_DATA_DEPTH 512
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`define RV_ICACHE_ENABLE 1
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`define RV_ICACHE_NUM_WAYS 2
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`define RV_ICACHE_NUM_BEATS 8
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`define RV_ICACHE_BEAT_BITS 3
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`define RV_ICACHE_FDATA_WIDTH 68
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`define RV_ICACHE_TAG_NUM_BYPASS 2
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`define RV_ICACHE_2BANKS 1
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`define RV_ICACHE_INDEX_HI 12
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`define RV_ICACHE_SCND_LAST 6
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`define RV_ICACHE_BEAT_ADDR_HI 5
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`define RV_PIC_MEIGWCLR_MASK 'h0
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`define RV_PIC_MEIP_MASK 'h0
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`define RV_PIC_MEIPL_MASK 'hf
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`define RV_PIC_TOTAL_INT_PLUS1 9
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`define RV_PIC_MEIPL_COUNT 8
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`define RV_PIC_MEIGWCLR_COUNT 8
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`define RV_PIC_MEIE_OFFSET 'h2000
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`define RV_PIC_BITS 15
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`define RV_PIC_MPICCFG_MASK 'h1
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`define RV_PIC_MPICCFG_OFFSET 'h3000
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`define RV_PIC_OFFSET 10'hc0000
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`define RV_PIC_MPICCFG_COUNT 1
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`define RV_PIC_MEIE_COUNT 8
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`define RV_PIC_MEIPT_OFFSET 'h3004
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`define RV_PIC_MEIGWCLR_OFFSET 'h5000
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`define RV_PIC_SIZE 32
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`define RV_PIC_MEIGWCTRL_COUNT 8
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`define RV_PIC_MEIP_OFFSET 'h1000
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`define RV_PIC_INT_WORDS 1
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`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
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`define RV_PIC_MEIPT_COUNT 8
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`define RV_PIC_REGION 4'hf
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`define RV_PIC_TOTAL_INT 8
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`define RV_PIC_MEIP_COUNT 1
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`define RV_PIC_MEIPT_MASK 'h0
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`define RV_PIC_MEIE_MASK 'h1
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`define RV_PIC_MEIPL_OFFSET 'h0000
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`define RV_PIC_BASE_ADDR 32'hf00c0000
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`define RV_PIC_MEIGWCTRL_MASK 'h3
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`define RV_RESET_VEC 'h80000000
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`define RV_FPGA_OPTIMIZE 1
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`define RV_LSU_NUM_NBLOAD_WIDTH 2
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`define RV_ICACHE_ONLY 1
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`define RV_BITMANIP_ZBF 0
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`define RV_BITMANIP_ZBB 1
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`define RV_LSU_STBUF_DEPTH 4
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`define RV_TIMER_LEGAL_EN 1
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`define RV_FAST_INTERRUPT_REDIRECT 1
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`define RV_LSU2DMA 0
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`define RV_BITMANIP_ZBE 0
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`define RV_DIV_NEW 1
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`define RV_BITMANIP_ZBA 1
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`define RV_DMA_BUF_DEPTH 5
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`define RV_BITMANIP_ZBP 0
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`define RV_BITMANIP_ZBR 0
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`define RV_LSU_NUM_NBLOAD 4
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`define RV_DIV_BIT 4
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`define RV_BITMANIP_ZBS 1
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`define RV_BITMANIP_ZBC 1
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`undef RV_ASSERT_ON
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@ -0,0 +1,175 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by colin on Wed Mar 23 01:03:51 PM UTC 2022
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//
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// cmd: swerv -target=default -set build_axi4
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//
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#define RV_TOP `TOP.rvtop
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#define RV_BUILD_AXI_NATIVE 1
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#define CPU_TOP `RV_TOP.swerv
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#define RV_STERR_ROLLBACK 0
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#define SDVT_AHB 0
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#define RV_ASSERT_ON
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#define CLOCK_PERIOD 100
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#define RV_EXT_DATAWIDTH 64
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#define RV_LDERR_ROLLBACK 1
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#define RV_BUILD_AXI4 1
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#define TOP tb_top
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#define RV_EXT_ADDRWIDTH 32
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#define RV_INST_ACCESS_MASK1 0xffffffff
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#define RV_INST_ACCESS_MASK3 0xffffffff
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#define RV_DATA_ACCESS_ENABLE4 0x0
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#define RV_DATA_ACCESS_MASK3 0xffffffff
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#define RV_INST_ACCESS_ENABLE4 0x0
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#define RV_DATA_ACCESS_MASK1 0xffffffff
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#define RV_INST_ACCESS_ADDR3 0x00000000
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#define RV_INST_ACCESS_ENABLE7 0x0
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#define RV_INST_ACCESS_ADDR1 0x00000000
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#define RV_DATA_ACCESS_ADDR1 0x00000000
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#define RV_DATA_ACCESS_ADDR3 0x00000000
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#define RV_DATA_ACCESS_ENABLE7 0x0
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#define RV_INST_ACCESS_ENABLE0 0x0
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#define RV_DATA_ACCESS_ADDR5 0x00000000
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#define RV_INST_ACCESS_ADDR0 0x00000000
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#define RV_INST_ACCESS_ADDR5 0x00000000
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#define RV_DATA_ACCESS_ADDR0 0x00000000
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#define RV_DATA_ACCESS_ENABLE0 0x0
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#define RV_DATA_ACCESS_MASK5 0xffffffff
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#define RV_INST_ACCESS_MASK0 0xffffffff
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#define RV_DATA_ACCESS_ENABLE6 0x0
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#define RV_DATA_ACCESS_ENABLE2 0x0
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#define RV_INST_ACCESS_ENABLE1 0x0
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#define RV_INST_ACCESS_ENABLE6 0x0
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#define RV_DATA_ACCESS_ENABLE1 0x0
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#define RV_INST_ACCESS_ENABLE2 0x0
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#define RV_INST_ACCESS_MASK5 0xffffffff
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#define RV_DATA_ACCESS_MASK0 0xffffffff
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#define RV_INST_ACCESS_MASK6 0xffffffff
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#define RV_INST_ACCESS_ADDR4 0x00000000
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#define RV_DATA_ACCESS_ADDR7 0x00000000
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#define RV_INST_ACCESS_ADDR7 0x00000000
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#define RV_DATA_ACCESS_ADDR4 0x00000000
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#define RV_DATA_ACCESS_MASK6 0xffffffff
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#define RV_DATA_ACCESS_ENABLE5 0x0
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#define RV_DATA_ACCESS_MASK7 0xffffffff
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#define RV_INST_ACCESS_ENABLE3 0x0
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#define RV_INST_ACCESS_ADDR6 0x00000000
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#define RV_INST_ACCESS_MASK4 0xffffffff
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#define RV_DATA_ACCESS_MASK4 0xffffffff
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#define RV_DATA_ACCESS_ADDR6 0x00000000
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#define RV_INST_ACCESS_MASK7 0xffffffff
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#define RV_INST_ACCESS_ENABLE5 0x0
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#define RV_DATA_ACCESS_ENABLE3 0x0
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#define RV_INST_ACCESS_ADDR2 0x00000000
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#define RV_DATA_ACCESS_ADDR2 0x00000000
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#define RV_INST_ACCESS_MASK2 0xffffffff
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#define RV_DATA_ACCESS_MASK2 0xffffffff
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#define RV_ICCM_BANK_INDEX_LO 5
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#define RV_ICCM_DATA_CELL ram_1024x39
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#define RV_ICCM_SADR 0xee000000
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#define RV_ICCM_NUM_BANKS_8
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#define RV_ICCM_SIZE 32
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#define RV_ICCM_BANK_BITS 3
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#define RV_ICCM_ROWS 1024
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#define RV_ICCM_EADR 0xee007fff
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#define RV_ICCM_SIZE_32
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#define RV_ICCM_INDEX_BITS 10
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#define RV_ICCM_BITS 15
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#define RV_ICCM_NUM_BANKS 8
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#define RV_ICCM_RESERVED 0x1000
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#define RV_ICCM_REGION 0xe
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#define RV_ICCM_OFFSET 0xe000000
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#define RV_ICCM_BANK_HI 4
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#define RV_TARGET default
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#define RV_UNUSED_REGION7 0x10000000
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#define RV_DEBUG_SB_MEM 0xa0580000
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#define RV_UNUSED_REGION8 0x00000000
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#define RV_UNUSED_REGION4 0x40000000
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#define RV_UNUSED_REGION0 0x90000000
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#define RV_UNUSED_REGION3 0x50000000
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#ifndef RV_SERIALIO
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#define RV_SERIALIO 0xd0580000
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#endif
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#define RV_EXTERNAL_DATA_1 0xb0000000
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#define RV_UNUSED_REGION2 0x60000000
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#define RV_UNUSED_REGION5 0x30000000
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#define RV_UNUSED_REGION6 0x20000000
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#ifndef RV_EXTERNAL_DATA
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#define RV_EXTERNAL_DATA 0xc0580000
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#endif
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#define RV_UNUSED_REGION1 0x70000000
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#define RV_XLEN 32
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#define RV_DCCM_ROWS 1024
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#define RV_DCCM_SADR 0xf0040000
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#define RV_DCCM_DATA_CELL ram_1024x39
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#define RV_DCCM_BANK_BITS 3
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#define RV_DCCM_NUM_BANKS_8
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#define RV_DCCM_SIZE 32
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#define RV_DCCM_ENABLE 1
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#define RV_DCCM_FDATA_WIDTH 39
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#define RV_DCCM_OFFSET 0x40000
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#define RV_DCCM_RESERVED 0x1400
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#define RV_DCCM_DATA_WIDTH 32
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#define RV_DCCM_ECC_WIDTH 7
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#define RV_DCCM_REGION 0xf
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#define RV_DCCM_BITS 15
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#define RV_LSU_SB_BITS 15
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#define RV_DCCM_INDEX_BITS 10
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#define RV_DCCM_WIDTH_BITS 2
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#define RV_DCCM_NUM_BANKS 8
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#define RV_DCCM_EADR 0xf0047fff
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#define RV_DCCM_BYTE_WIDTH 4
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#define RV_DCCM_SIZE_32
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#ifndef RV_NMI_VEC
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#define RV_NMI_VEC 0x11110000
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#endif
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#define RV_PIC_MEIGWCLR_MASK 0x0
|
||||
#define RV_PIC_MEIP_MASK 0x0
|
||||
#define RV_PIC_MEIPL_MASK 0xf
|
||||
#define RV_PIC_TOTAL_INT_PLUS1 9
|
||||
#define RV_PIC_MEIPL_COUNT 8
|
||||
#define RV_PIC_MEIGWCLR_COUNT 8
|
||||
#define RV_PIC_MEIE_OFFSET 0x2000
|
||||
#define RV_PIC_BITS 15
|
||||
#define RV_PIC_MPICCFG_MASK 0x1
|
||||
#define RV_PIC_MPICCFG_OFFSET 0x3000
|
||||
#define RV_PIC_OFFSET 0xc0000
|
||||
#define RV_PIC_MPICCFG_COUNT 1
|
||||
#define RV_PIC_MEIE_COUNT 8
|
||||
#define RV_PIC_MEIPT_OFFSET 0x3004
|
||||
#define RV_PIC_MEIGWCLR_OFFSET 0x5000
|
||||
#define RV_PIC_SIZE 32
|
||||
#define RV_PIC_MEIGWCTRL_COUNT 8
|
||||
#define RV_PIC_MEIP_OFFSET 0x1000
|
||||
#define RV_PIC_INT_WORDS 1
|
||||
#define RV_PIC_MEIGWCTRL_OFFSET 0x4000
|
||||
#define RV_PIC_MEIPT_COUNT 8
|
||||
#define RV_PIC_REGION 0xf
|
||||
#define RV_PIC_TOTAL_INT 8
|
||||
#define RV_PIC_MEIP_COUNT 1
|
||||
#define RV_PIC_MEIPT_MASK 0x0
|
||||
#define RV_PIC_MEIE_MASK 0x1
|
||||
#define RV_PIC_MEIPL_OFFSET 0x0000
|
||||
#define RV_PIC_BASE_ADDR 0xf00c0000
|
||||
#define RV_PIC_MEIGWCTRL_MASK 0x3
|
||||
#ifndef RV_RESET_VEC
|
||||
#define RV_RESET_VEC 0x80000000
|
||||
#endif
|
||||
#define RV_FPGA_OPTIMIZE 1
|
||||
#define RV_LSU_NUM_NBLOAD_WIDTH 2
|
||||
#define RV_ICACHE_ONLY 1
|
||||
#define RV_BITMANIP_ZBF 0
|
||||
#define RV_BITMANIP_ZBB 1
|
||||
#define RV_LSU_STBUF_DEPTH 4
|
||||
#define RV_TIMER_LEGAL_EN 1
|
||||
#define RV_FAST_INTERRUPT_REDIRECT 1
|
||||
#define RV_LSU2DMA 0
|
||||
#define RV_BITMANIP_ZBE 0
|
||||
#define RV_DIV_NEW 1
|
||||
#define RV_BITMANIP_ZBA 1
|
||||
#define RV_DMA_BUF_DEPTH 5
|
||||
#define RV_BITMANIP_ZBP 0
|
||||
#define RV_BITMANIP_ZBR 0
|
||||
#define RV_LSU_NUM_NBLOAD 4
|
||||
#define RV_DIV_BIT 4
|
||||
#define RV_BITMANIP_ZBS 1
|
||||
#define RV_BITMANIP_ZBC 1
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
parameter el2_param_t pt = '{
|
||||
BHT_ADDR_HI : 8'h07 ,
|
||||
BHT_ADDR_LO : 6'h02 ,
|
||||
BHT_ARRAY_DEPTH : 15'h0040 ,
|
||||
BHT_GHR_HASH_1 : 5'h01 ,
|
||||
BHT_GHR_SIZE : 8'h06 ,
|
||||
BHT_SIZE : 16'h0080 ,
|
||||
BITMANIP_ZBA : 5'h01 ,
|
||||
BITMANIP_ZBB : 5'h01 ,
|
||||
BITMANIP_ZBC : 5'h01 ,
|
||||
BITMANIP_ZBE : 5'h00 ,
|
||||
BITMANIP_ZBF : 5'h00 ,
|
||||
BITMANIP_ZBP : 5'h00 ,
|
||||
BITMANIP_ZBR : 5'h00 ,
|
||||
BITMANIP_ZBS : 5'h01 ,
|
||||
BTB_ADDR_HI : 9'h005 ,
|
||||
BTB_ADDR_LO : 6'h02 ,
|
||||
BTB_ARRAY_DEPTH : 13'h0010 ,
|
||||
BTB_BTAG_FOLD : 5'h01 ,
|
||||
BTB_BTAG_SIZE : 9'h009 ,
|
||||
BTB_ENABLE : 5'h01 ,
|
||||
BTB_FOLD2_INDEX_HASH : 5'h00 ,
|
||||
BTB_FULLYA : 5'h00 ,
|
||||
BTB_INDEX1_HI : 9'h005 ,
|
||||
BTB_INDEX1_LO : 9'h002 ,
|
||||
BTB_INDEX2_HI : 9'h009 ,
|
||||
BTB_INDEX2_LO : 9'h006 ,
|
||||
BTB_INDEX3_HI : 9'h00D ,
|
||||
BTB_INDEX3_LO : 9'h00A ,
|
||||
BTB_SIZE : 14'h0020 ,
|
||||
BTB_TOFFSET_SIZE : 9'h00C ,
|
||||
BUILD_AHB_LITE : 4'h0 ,
|
||||
BUILD_AXI4 : 5'h01 ,
|
||||
BUILD_AXI_NATIVE : 5'h01 ,
|
||||
BUS_PRTY_DEFAULT : 6'h03 ,
|
||||
DATA_ACCESS_ADDR0 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR1 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR2 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR3 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR4 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR5 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR6 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR7 : 36'h000000000 ,
|
||||
DATA_ACCESS_ENABLE0 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE1 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE2 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE3 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE4 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE5 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE6 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE7 : 5'h00 ,
|
||||
DATA_ACCESS_MASK0 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK1 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK2 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK3 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK4 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK5 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK6 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK7 : 36'h0FFFFFFFF ,
|
||||
DCCM_BANK_BITS : 7'h03 ,
|
||||
DCCM_BITS : 9'h00F ,
|
||||
DCCM_BYTE_WIDTH : 7'h04 ,
|
||||
DCCM_DATA_WIDTH : 10'h020 ,
|
||||
DCCM_ECC_WIDTH : 7'h07 ,
|
||||
DCCM_ENABLE : 5'h01 ,
|
||||
DCCM_FDATA_WIDTH : 10'h027 ,
|
||||
DCCM_INDEX_BITS : 8'h0A ,
|
||||
DCCM_NUM_BANKS : 9'h008 ,
|
||||
DCCM_REGION : 8'h0F ,
|
||||
DCCM_SADR : 36'h0F0040000 ,
|
||||
DCCM_SIZE : 14'h0020 ,
|
||||
DCCM_WIDTH_BITS : 6'h02 ,
|
||||
DIV_BIT : 7'h04 ,
|
||||
DIV_NEW : 5'h01 ,
|
||||
DMA_BUF_DEPTH : 7'h05 ,
|
||||
DMA_BUS_ID : 9'h001 ,
|
||||
DMA_BUS_PRTY : 6'h02 ,
|
||||
DMA_BUS_TAG : 8'h01 ,
|
||||
FAST_INTERRUPT_REDIRECT : 5'h01 ,
|
||||
ICACHE_2BANKS : 5'h01 ,
|
||||
ICACHE_BANK_BITS : 7'h01 ,
|
||||
ICACHE_BANK_HI : 7'h03 ,
|
||||
ICACHE_BANK_LO : 6'h03 ,
|
||||
ICACHE_BANK_WIDTH : 8'h08 ,
|
||||
ICACHE_BANKS_WAY : 7'h02 ,
|
||||
ICACHE_BEAT_ADDR_HI : 8'h05 ,
|
||||
ICACHE_BEAT_BITS : 8'h03 ,
|
||||
ICACHE_BYPASS_ENABLE : 5'h01 ,
|
||||
ICACHE_DATA_DEPTH : 18'h00200 ,
|
||||
ICACHE_DATA_INDEX_LO : 7'h04 ,
|
||||
ICACHE_DATA_WIDTH : 11'h040 ,
|
||||
ICACHE_ECC : 5'h00 ,
|
||||
ICACHE_ENABLE : 5'h01 ,
|
||||
ICACHE_FDATA_WIDTH : 11'h044 ,
|
||||
ICACHE_INDEX_HI : 9'h00C ,
|
||||
ICACHE_LN_SZ : 11'h040 ,
|
||||
ICACHE_NUM_BEATS : 8'h08 ,
|
||||
ICACHE_NUM_BYPASS : 8'h02 ,
|
||||
ICACHE_NUM_BYPASS_WIDTH : 8'h02 ,
|
||||
ICACHE_NUM_WAYS : 7'h02 ,
|
||||
ICACHE_ONLY : 5'h01 ,
|
||||
ICACHE_SCND_LAST : 8'h06 ,
|
||||
ICACHE_SIZE : 13'h0010 ,
|
||||
ICACHE_STATUS_BITS : 7'h01 ,
|
||||
ICACHE_TAG_BYPASS_ENABLE : 5'h01 ,
|
||||
ICACHE_TAG_DEPTH : 17'h00080 ,
|
||||
ICACHE_TAG_INDEX_LO : 7'h06 ,
|
||||
ICACHE_TAG_LO : 9'h00D ,
|
||||
ICACHE_TAG_NUM_BYPASS : 8'h02 ,
|
||||
ICACHE_TAG_NUM_BYPASS_WIDTH : 8'h02 ,
|
||||
ICACHE_WAYPACK : 5'h01 ,
|
||||
ICCM_BANK_BITS : 7'h03 ,
|
||||
ICCM_BANK_HI : 9'h004 ,
|
||||
ICCM_BANK_INDEX_LO : 9'h005 ,
|
||||
ICCM_BITS : 9'h00F ,
|
||||
ICCM_ENABLE : 5'h00 ,
|
||||
ICCM_ICACHE : 5'h00 ,
|
||||
ICCM_INDEX_BITS : 8'h0A ,
|
||||
ICCM_NUM_BANKS : 9'h008 ,
|
||||
ICCM_ONLY : 5'h00 ,
|
||||
ICCM_REGION : 8'h0E ,
|
||||
ICCM_SADR : 36'h0EE000000 ,
|
||||
ICCM_SIZE : 14'h0020 ,
|
||||
IFU_BUS_ID : 5'h01 ,
|
||||
IFU_BUS_PRTY : 6'h02 ,
|
||||
IFU_BUS_TAG : 8'h03 ,
|
||||
INST_ACCESS_ADDR0 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR1 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR2 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR3 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR4 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR5 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR6 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR7 : 36'h000000000 ,
|
||||
INST_ACCESS_ENABLE0 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE1 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE2 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE3 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE4 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE5 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE6 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE7 : 5'h00 ,
|
||||
INST_ACCESS_MASK0 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK1 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK2 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK3 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK4 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK5 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK6 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK7 : 36'h0FFFFFFFF ,
|
||||
LOAD_TO_USE_PLUS1 : 5'h00 ,
|
||||
LSU2DMA : 5'h00 ,
|
||||
LSU_BUS_ID : 5'h01 ,
|
||||
LSU_BUS_PRTY : 6'h02 ,
|
||||
LSU_BUS_TAG : 8'h03 ,
|
||||
LSU_NUM_NBLOAD : 9'h004 ,
|
||||
LSU_NUM_NBLOAD_WIDTH : 7'h02 ,
|
||||
LSU_SB_BITS : 9'h00F ,
|
||||
LSU_STBUF_DEPTH : 8'h04 ,
|
||||
NO_ICCM_NO_ICACHE : 5'h00 ,
|
||||
PIC_2CYCLE : 5'h00 ,
|
||||
PIC_BASE_ADDR : 36'h0F00C0000 ,
|
||||
PIC_BITS : 9'h00F ,
|
||||
PIC_INT_WORDS : 8'h01 ,
|
||||
PIC_REGION : 8'h0F ,
|
||||
PIC_SIZE : 13'h0020 ,
|
||||
PIC_TOTAL_INT : 12'h008 ,
|
||||
PIC_TOTAL_INT_PLUS1 : 13'h0009 ,
|
||||
RET_STACK_SIZE : 8'h04 ,
|
||||
SB_BUS_ID : 5'h01 ,
|
||||
SB_BUS_PRTY : 6'h02 ,
|
||||
SB_BUS_TAG : 8'h01 ,
|
||||
TIMER_LEGAL_EN : 5'h01
|
||||
}
|
||||
// parameter el2_param_t pt = 2271'h0384010020C010010840000020508020104840002808120606828020060210C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC183C20401C213850203C3C01000000200820428042010840830C201028184020008100010880C0801004040820C0100210040060681010418100A0F000281000E0EE00000000802101800000000000000000000000000000000000000000000000000000000000000000000000000000000007FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF8001080C08081E080007806000003C043C04001000904084021
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
typedef struct packed {
|
||||
bit [7:0] BHT_ADDR_HI;
|
||||
bit [5:0] BHT_ADDR_LO;
|
||||
bit [14:0] BHT_ARRAY_DEPTH;
|
||||
bit [4:0] BHT_GHR_HASH_1;
|
||||
bit [7:0] BHT_GHR_SIZE;
|
||||
bit [15:0] BHT_SIZE;
|
||||
bit [4:0] BITMANIP_ZBA;
|
||||
bit [4:0] BITMANIP_ZBB;
|
||||
bit [4:0] BITMANIP_ZBC;
|
||||
bit [4:0] BITMANIP_ZBE;
|
||||
bit [4:0] BITMANIP_ZBF;
|
||||
bit [4:0] BITMANIP_ZBP;
|
||||
bit [4:0] BITMANIP_ZBR;
|
||||
bit [4:0] BITMANIP_ZBS;
|
||||
bit [8:0] BTB_ADDR_HI;
|
||||
bit [5:0] BTB_ADDR_LO;
|
||||
bit [12:0] BTB_ARRAY_DEPTH;
|
||||
bit [4:0] BTB_BTAG_FOLD;
|
||||
bit [8:0] BTB_BTAG_SIZE;
|
||||
bit [4:0] BTB_ENABLE;
|
||||
bit [4:0] BTB_FOLD2_INDEX_HASH;
|
||||
bit [4:0] BTB_FULLYA;
|
||||
bit [8:0] BTB_INDEX1_HI;
|
||||
bit [8:0] BTB_INDEX1_LO;
|
||||
bit [8:0] BTB_INDEX2_HI;
|
||||
bit [8:0] BTB_INDEX2_LO;
|
||||
bit [8:0] BTB_INDEX3_HI;
|
||||
bit [8:0] BTB_INDEX3_LO;
|
||||
bit [13:0] BTB_SIZE;
|
||||
bit [8:0] BTB_TOFFSET_SIZE;
|
||||
bit BUILD_AHB_LITE;
|
||||
bit [4:0] BUILD_AXI4;
|
||||
bit [4:0] BUILD_AXI_NATIVE;
|
||||
bit [5:0] BUS_PRTY_DEFAULT;
|
||||
bit [35:0] DATA_ACCESS_ADDR0;
|
||||
bit [35:0] DATA_ACCESS_ADDR1;
|
||||
bit [35:0] DATA_ACCESS_ADDR2;
|
||||
bit [35:0] DATA_ACCESS_ADDR3;
|
||||
bit [35:0] DATA_ACCESS_ADDR4;
|
||||
bit [35:0] DATA_ACCESS_ADDR5;
|
||||
bit [35:0] DATA_ACCESS_ADDR6;
|
||||
bit [35:0] DATA_ACCESS_ADDR7;
|
||||
bit [4:0] DATA_ACCESS_ENABLE0;
|
||||
bit [4:0] DATA_ACCESS_ENABLE1;
|
||||
bit [4:0] DATA_ACCESS_ENABLE2;
|
||||
bit [4:0] DATA_ACCESS_ENABLE3;
|
||||
bit [4:0] DATA_ACCESS_ENABLE4;
|
||||
bit [4:0] DATA_ACCESS_ENABLE5;
|
||||
bit [4:0] DATA_ACCESS_ENABLE6;
|
||||
bit [4:0] DATA_ACCESS_ENABLE7;
|
||||
bit [35:0] DATA_ACCESS_MASK0;
|
||||
bit [35:0] DATA_ACCESS_MASK1;
|
||||
bit [35:0] DATA_ACCESS_MASK2;
|
||||
bit [35:0] DATA_ACCESS_MASK3;
|
||||
bit [35:0] DATA_ACCESS_MASK4;
|
||||
bit [35:0] DATA_ACCESS_MASK5;
|
||||
bit [35:0] DATA_ACCESS_MASK6;
|
||||
bit [35:0] DATA_ACCESS_MASK7;
|
||||
bit [6:0] DCCM_BANK_BITS;
|
||||
bit [8:0] DCCM_BITS;
|
||||
bit [6:0] DCCM_BYTE_WIDTH;
|
||||
bit [9:0] DCCM_DATA_WIDTH;
|
||||
bit [6:0] DCCM_ECC_WIDTH;
|
||||
bit [4:0] DCCM_ENABLE;
|
||||
bit [9:0] DCCM_FDATA_WIDTH;
|
||||
bit [7:0] DCCM_INDEX_BITS;
|
||||
bit [8:0] DCCM_NUM_BANKS;
|
||||
bit [7:0] DCCM_REGION;
|
||||
bit [35:0] DCCM_SADR;
|
||||
bit [13:0] DCCM_SIZE;
|
||||
bit [5:0] DCCM_WIDTH_BITS;
|
||||
bit [6:0] DIV_BIT;
|
||||
bit [4:0] DIV_NEW;
|
||||
bit [6:0] DMA_BUF_DEPTH;
|
||||
bit [8:0] DMA_BUS_ID;
|
||||
bit [5:0] DMA_BUS_PRTY;
|
||||
bit [7:0] DMA_BUS_TAG;
|
||||
bit [4:0] FAST_INTERRUPT_REDIRECT;
|
||||
bit [4:0] ICACHE_2BANKS;
|
||||
bit [6:0] ICACHE_BANK_BITS;
|
||||
bit [6:0] ICACHE_BANK_HI;
|
||||
bit [5:0] ICACHE_BANK_LO;
|
||||
bit [7:0] ICACHE_BANK_WIDTH;
|
||||
bit [6:0] ICACHE_BANKS_WAY;
|
||||
bit [7:0] ICACHE_BEAT_ADDR_HI;
|
||||
bit [7:0] ICACHE_BEAT_BITS;
|
||||
bit [4:0] ICACHE_BYPASS_ENABLE;
|
||||
bit [17:0] ICACHE_DATA_DEPTH;
|
||||
bit [6:0] ICACHE_DATA_INDEX_LO;
|
||||
bit [10:0] ICACHE_DATA_WIDTH;
|
||||
bit [4:0] ICACHE_ECC;
|
||||
bit [4:0] ICACHE_ENABLE;
|
||||
bit [10:0] ICACHE_FDATA_WIDTH;
|
||||
bit [8:0] ICACHE_INDEX_HI;
|
||||
bit [10:0] ICACHE_LN_SZ;
|
||||
bit [7:0] ICACHE_NUM_BEATS;
|
||||
bit [7:0] ICACHE_NUM_BYPASS;
|
||||
bit [7:0] ICACHE_NUM_BYPASS_WIDTH;
|
||||
bit [6:0] ICACHE_NUM_WAYS;
|
||||
bit [4:0] ICACHE_ONLY;
|
||||
bit [7:0] ICACHE_SCND_LAST;
|
||||
bit [12:0] ICACHE_SIZE;
|
||||
bit [6:0] ICACHE_STATUS_BITS;
|
||||
bit [4:0] ICACHE_TAG_BYPASS_ENABLE;
|
||||
bit [16:0] ICACHE_TAG_DEPTH;
|
||||
bit [6:0] ICACHE_TAG_INDEX_LO;
|
||||
bit [8:0] ICACHE_TAG_LO;
|
||||
bit [7:0] ICACHE_TAG_NUM_BYPASS;
|
||||
bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH;
|
||||
bit [4:0] ICACHE_WAYPACK;
|
||||
bit [6:0] ICCM_BANK_BITS;
|
||||
bit [8:0] ICCM_BANK_HI;
|
||||
bit [8:0] ICCM_BANK_INDEX_LO;
|
||||
bit [8:0] ICCM_BITS;
|
||||
bit [4:0] ICCM_ENABLE;
|
||||
bit [4:0] ICCM_ICACHE;
|
||||
bit [7:0] ICCM_INDEX_BITS;
|
||||
bit [8:0] ICCM_NUM_BANKS;
|
||||
bit [4:0] ICCM_ONLY;
|
||||
bit [7:0] ICCM_REGION;
|
||||
bit [35:0] ICCM_SADR;
|
||||
bit [13:0] ICCM_SIZE;
|
||||
bit [4:0] IFU_BUS_ID;
|
||||
bit [5:0] IFU_BUS_PRTY;
|
||||
bit [7:0] IFU_BUS_TAG;
|
||||
bit [35:0] INST_ACCESS_ADDR0;
|
||||
bit [35:0] INST_ACCESS_ADDR1;
|
||||
bit [35:0] INST_ACCESS_ADDR2;
|
||||
bit [35:0] INST_ACCESS_ADDR3;
|
||||
bit [35:0] INST_ACCESS_ADDR4;
|
||||
bit [35:0] INST_ACCESS_ADDR5;
|
||||
bit [35:0] INST_ACCESS_ADDR6;
|
||||
bit [35:0] INST_ACCESS_ADDR7;
|
||||
bit [4:0] INST_ACCESS_ENABLE0;
|
||||
bit [4:0] INST_ACCESS_ENABLE1;
|
||||
bit [4:0] INST_ACCESS_ENABLE2;
|
||||
bit [4:0] INST_ACCESS_ENABLE3;
|
||||
bit [4:0] INST_ACCESS_ENABLE4;
|
||||
bit [4:0] INST_ACCESS_ENABLE5;
|
||||
bit [4:0] INST_ACCESS_ENABLE6;
|
||||
bit [4:0] INST_ACCESS_ENABLE7;
|
||||
bit [35:0] INST_ACCESS_MASK0;
|
||||
bit [35:0] INST_ACCESS_MASK1;
|
||||
bit [35:0] INST_ACCESS_MASK2;
|
||||
bit [35:0] INST_ACCESS_MASK3;
|
||||
bit [35:0] INST_ACCESS_MASK4;
|
||||
bit [35:0] INST_ACCESS_MASK5;
|
||||
bit [35:0] INST_ACCESS_MASK6;
|
||||
bit [35:0] INST_ACCESS_MASK7;
|
||||
bit [4:0] LOAD_TO_USE_PLUS1;
|
||||
bit [4:0] LSU2DMA;
|
||||
bit [4:0] LSU_BUS_ID;
|
||||
bit [5:0] LSU_BUS_PRTY;
|
||||
bit [7:0] LSU_BUS_TAG;
|
||||
bit [8:0] LSU_NUM_NBLOAD;
|
||||
bit [6:0] LSU_NUM_NBLOAD_WIDTH;
|
||||
bit [8:0] LSU_SB_BITS;
|
||||
bit [7:0] LSU_STBUF_DEPTH;
|
||||
bit [4:0] NO_ICCM_NO_ICACHE;
|
||||
bit [4:0] PIC_2CYCLE;
|
||||
bit [35:0] PIC_BASE_ADDR;
|
||||
bit [8:0] PIC_BITS;
|
||||
bit [7:0] PIC_INT_WORDS;
|
||||
bit [7:0] PIC_REGION;
|
||||
bit [12:0] PIC_SIZE;
|
||||
bit [11:0] PIC_TOTAL_INT;
|
||||
bit [12:0] PIC_TOTAL_INT_PLUS1;
|
||||
bit [7:0] RET_STACK_SIZE;
|
||||
bit [4:0] SB_BUS_ID;
|
||||
bit [5:0] SB_BUS_PRTY;
|
||||
bit [7:0] SB_BUS_TAG;
|
||||
bit [4:0] TIMER_LEGAL_EN;
|
||||
} el2_param_t;
|
||||
|
||||
Binary file not shown.
|
|
@ -0,0 +1,71 @@
|
|||
# 0 "jtag.s"
|
||||
# 1 "/home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo//"
|
||||
# 0 "<built-in>"
|
||||
# 0 "<command-line>"
|
||||
# 1 "jtag.s"
|
||||
# 21 "jtag.s"
|
||||
# 1 "/home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/defines.h" 1
|
||||
# 22 "jtag.s" 2
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
.section .text
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
|
||||
csrw minstret, zero
|
||||
csrw minstreth, zero
|
||||
|
||||
|
||||
li x1, 0xee000000
|
||||
csrw mtvec, x1
|
||||
|
||||
|
||||
|
||||
li x1, 0x5f555555
|
||||
csrw 0x7c0, x1
|
||||
|
||||
|
||||
|
||||
|
||||
li x3, 0xd0580000
|
||||
la x4, hw_data
|
||||
|
||||
loop:
|
||||
lb x5, 0(x4)
|
||||
sb x5, 0(x3)
|
||||
addi x4, x4, 1
|
||||
bnez x5, loop
|
||||
|
||||
li x3, 0xd0580000
|
||||
la x4, hw_data
|
||||
|
||||
loop2:
|
||||
lb x5, 0(x4)
|
||||
sb x5, 0(x3)
|
||||
addi x4, x4, 1
|
||||
bnez x5, loop2
|
||||
|
||||
loop3:
|
||||
beq x0, x0, loop3
|
||||
|
||||
|
||||
_finish:
|
||||
li x3, 0xd0580000
|
||||
addi x5, x0, 0xff
|
||||
sb x5, 0(x3)
|
||||
beq x0, x0, _finish
|
||||
.rept 100
|
||||
nop
|
||||
.endr
|
||||
|
||||
.global hw_data
|
||||
.data
|
||||
hw_data:
|
||||
.ascii "----------------------------------\n"
|
||||
.ascii "Hello World Colin.liang EL2@WDC !!\n"
|
||||
.ascii "----------------------------------\n"
|
||||
.byte 0
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
|
||||
/home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.bin: file format elf32-littleriscv
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
80000000 <_start>:
|
||||
.section .text
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
// Clear minstret
|
||||
csrw minstret, zero
|
||||
80000000: b0201073 csrw minstret,zero
|
||||
csrw minstreth, zero
|
||||
80000004: b8201073 csrw minstreth,zero
|
||||
|
||||
// Set up MTVEC - not expecting to use it though
|
||||
li x1, RV_ICCM_SADR
|
||||
80000008: ee0000b7 lui ra,0xee000
|
||||
csrw mtvec, x1
|
||||
8000000c: 30509073 csrw mtvec,ra
|
||||
|
||||
|
||||
// Enable Caches in MRAC
|
||||
li x1, 0x5f555555
|
||||
80000010: 5f5550b7 lui ra,0x5f555
|
||||
80000014: 55508093 addi ra,ra,1365 # 5f555555 <_start-0x20aaaaab>
|
||||
csrw 0x7c0, x1
|
||||
80000018: 7c009073 csrw 0x7c0,ra
|
||||
|
||||
// Load string from hw_data
|
||||
// and write to stdout address
|
||||
|
||||
li x3, STDOUT
|
||||
8000001c: d05801b7 lui gp,0xd0580
|
||||
la x4, hw_data
|
||||
80000020: 00004217 auipc tp,0x4
|
||||
80000024: fe020213 addi tp,tp,-32 # 80004000 <hw_data>
|
||||
|
||||
80000028 <loop>:
|
||||
|
||||
loop:
|
||||
lb x5, 0(x4)
|
||||
80000028: 00020283 lb t0,0(tp) # 0 <_start-0x80000000>
|
||||
sb x5, 0(x3)
|
||||
8000002c: 00518023 sb t0,0(gp) # d0580000 <STACK+0x50579f90>
|
||||
addi x4, x4, 1
|
||||
80000030: 0205 addi tp,tp,1
|
||||
bnez x5, loop
|
||||
80000032: fe029be3 bnez t0,80000028 <loop>
|
||||
|
||||
li x3, STDOUT
|
||||
80000036: d05801b7 lui gp,0xd0580
|
||||
la x4, hw_data
|
||||
8000003a: 00004217 auipc tp,0x4
|
||||
8000003e: fc620213 addi tp,tp,-58 # 80004000 <hw_data>
|
||||
|
||||
80000042 <loop2>:
|
||||
|
||||
loop2:
|
||||
lb x5, 0(x4)
|
||||
80000042: 00020283 lb t0,0(tp) # 0 <_start-0x80000000>
|
||||
sb x5, 0(x3)
|
||||
80000046: 00518023 sb t0,0(gp) # d0580000 <STACK+0x50579f90>
|
||||
addi x4, x4, 1
|
||||
8000004a: 0205 addi tp,tp,1
|
||||
bnez x5, loop2
|
||||
8000004c: fe029be3 bnez t0,80000042 <loop2>
|
||||
|
||||
80000050 <loop3>:
|
||||
|
||||
loop3:
|
||||
beq x0, x0, loop3
|
||||
80000050: 00000063 beqz zero,80000050 <loop3>
|
||||
|
||||
80000054 <_finish>:
|
||||
|
||||
// Write 0xff to STDOUT for TB to terminate test.
|
||||
_finish:
|
||||
li x3, STDOUT
|
||||
80000054: d05801b7 lui gp,0xd0580
|
||||
addi x5, x0, 0xff
|
||||
80000058: 0ff00293 li t0,255
|
||||
sb x5, 0(x3)
|
||||
8000005c: 00518023 sb t0,0(gp) # d0580000 <STACK+0x50579f90>
|
||||
beq x0, x0, _finish
|
||||
80000060: fe000ae3 beqz zero,80000054 <_finish>
|
||||
.rept 100
|
||||
nop
|
||||
.endr
|
||||
80000064: 0001 nop
|
||||
80000066: 0001 nop
|
||||
80000068: 0001 nop
|
||||
8000006a: 0001 nop
|
||||
8000006c: 0001 nop
|
||||
8000006e: 0001 nop
|
||||
80000070: 0001 nop
|
||||
80000072: 0001 nop
|
||||
80000074: 0001 nop
|
||||
80000076: 0001 nop
|
||||
80000078: 0001 nop
|
||||
8000007a: 0001 nop
|
||||
8000007c: 0001 nop
|
||||
8000007e: 0001 nop
|
||||
80000080: 0001 nop
|
||||
80000082: 0001 nop
|
||||
80000084: 0001 nop
|
||||
80000086: 0001 nop
|
||||
80000088: 0001 nop
|
||||
8000008a: 0001 nop
|
||||
8000008c: 0001 nop
|
||||
8000008e: 0001 nop
|
||||
80000090: 0001 nop
|
||||
80000092: 0001 nop
|
||||
80000094: 0001 nop
|
||||
80000096: 0001 nop
|
||||
80000098: 0001 nop
|
||||
8000009a: 0001 nop
|
||||
8000009c: 0001 nop
|
||||
8000009e: 0001 nop
|
||||
800000a0: 0001 nop
|
||||
800000a2: 0001 nop
|
||||
800000a4: 0001 nop
|
||||
800000a6: 0001 nop
|
||||
800000a8: 0001 nop
|
||||
800000aa: 0001 nop
|
||||
800000ac: 0001 nop
|
||||
800000ae: 0001 nop
|
||||
800000b0: 0001 nop
|
||||
800000b2: 0001 nop
|
||||
800000b4: 0001 nop
|
||||
800000b6: 0001 nop
|
||||
800000b8: 0001 nop
|
||||
800000ba: 0001 nop
|
||||
800000bc: 0001 nop
|
||||
800000be: 0001 nop
|
||||
800000c0: 0001 nop
|
||||
800000c2: 0001 nop
|
||||
800000c4: 0001 nop
|
||||
800000c6: 0001 nop
|
||||
800000c8: 0001 nop
|
||||
800000ca: 0001 nop
|
||||
800000cc: 0001 nop
|
||||
800000ce: 0001 nop
|
||||
800000d0: 0001 nop
|
||||
800000d2: 0001 nop
|
||||
800000d4: 0001 nop
|
||||
800000d6: 0001 nop
|
||||
800000d8: 0001 nop
|
||||
800000da: 0001 nop
|
||||
800000dc: 0001 nop
|
||||
800000de: 0001 nop
|
||||
800000e0: 0001 nop
|
||||
800000e2: 0001 nop
|
||||
800000e4: 0001 nop
|
||||
800000e6: 0001 nop
|
||||
800000e8: 0001 nop
|
||||
800000ea: 0001 nop
|
||||
800000ec: 0001 nop
|
||||
800000ee: 0001 nop
|
||||
800000f0: 0001 nop
|
||||
800000f2: 0001 nop
|
||||
800000f4: 0001 nop
|
||||
800000f6: 0001 nop
|
||||
800000f8: 0001 nop
|
||||
800000fa: 0001 nop
|
||||
800000fc: 0001 nop
|
||||
800000fe: 0001 nop
|
||||
80000100: 0001 nop
|
||||
80000102: 0001 nop
|
||||
80000104: 0001 nop
|
||||
80000106: 0001 nop
|
||||
80000108: 0001 nop
|
||||
8000010a: 0001 nop
|
||||
8000010c: 0001 nop
|
||||
8000010e: 0001 nop
|
||||
80000110: 0001 nop
|
||||
80000112: 0001 nop
|
||||
80000114: 0001 nop
|
||||
80000116: 0001 nop
|
||||
80000118: 0001 nop
|
||||
8000011a: 0001 nop
|
||||
8000011c: 0001 nop
|
||||
8000011e: 0001 nop
|
||||
80000120: 0001 nop
|
||||
80000122: 0001 nop
|
||||
80000124: 0001 nop
|
||||
80000126: 0001 nop
|
||||
80000128: 0001 nop
|
||||
8000012a: 0001 nop
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
|
||||
Memory Configuration
|
||||
|
||||
Name Origin Length Attributes
|
||||
*default* 0x0000000000000000 0xffffffffffffffff
|
||||
|
||||
Linker script and memory map
|
||||
|
||||
LOAD /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a
|
||||
LOAD /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
LOAD /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a
|
||||
START GROUP
|
||||
LOAD /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/lib/libc.a
|
||||
LOAD /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/../../../../riscv32-unknown-elf/lib/libgloss.a
|
||||
END GROUP
|
||||
LOAD /opt/riscv/lib/gcc/riscv32-unknown-elf/11.1.0/libgcc.a
|
||||
0x0000000080000000 . = 0x80000000
|
||||
|
||||
.text_init
|
||||
*(.text_init*)
|
||||
|
||||
.text 0x0000000080000000 0x12c
|
||||
*(.text*)
|
||||
.text 0x0000000080000000 0x12c /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
0x0000000080000000 _start
|
||||
0x000000008000012c _end = .
|
||||
0x0000000080004000 . = 0x80004000
|
||||
|
||||
.data 0x0000000080004000 0x6a
|
||||
*(.*data)
|
||||
.data 0x0000000080004000 0x6a /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
0x0000000080004000 hw_data
|
||||
*(.rodata*)
|
||||
0x0000000080006070 STACK = (ALIGN (0x10) + 0x2000)
|
||||
|
||||
.bss 0x000000008000406a 0x0
|
||||
*(.bss)
|
||||
.bss 0x000000008000406a 0x0 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
0x00000000d0580000 . = 0xd0580000
|
||||
|
||||
.data.io
|
||||
*(.data.io)
|
||||
OUTPUT(/home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.bin elf32-littleriscv)
|
||||
|
||||
.riscv.attributes
|
||||
0x0000000000000000 0x28
|
||||
.riscv.attributes
|
||||
0x0000000000000000 0x28 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
|
||||
.debug_line 0x0000000000000000 0xc1
|
||||
.debug_line 0x0000000000000000 0xc1 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
|
||||
.debug_info 0x0000000000000000 0x26
|
||||
.debug_info 0x0000000000000000 0x26 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
|
||||
.debug_abbrev 0x0000000000000000 0x14
|
||||
.debug_abbrev 0x0000000000000000 0x14 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
|
||||
.debug_aranges 0x0000000000000000 0x20
|
||||
.debug_aranges
|
||||
0x0000000000000000 0x20 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
|
||||
.debug_str 0x0000000000000000 0x50
|
||||
.debug_str 0x0000000000000000 0x50 /home/colin/develop/AbstractAccelerator/Cores-SweRV-EL2/demo/build/jtag.o
|
||||
Binary file not shown.
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
This is an automatically generated file by colin on Wed Mar 23 01:03:51 PM UTC 2022
|
||||
|
||||
cmd: swerv -target=default -set build_axi4
|
||||
|
||||
*/
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80000000;
|
||||
.text.init . : { *(.text.init) }
|
||||
|
||||
.text . : { *(.text) }
|
||||
_end = .;
|
||||
. = 0xd0580000;
|
||||
.data.io . : { *(.data.io) }
|
||||
. = 0xf0040000 ;
|
||||
.data : ALIGN(0x800) { *(.*data) *(.rodata*)}
|
||||
.bss : {BSS_START = .; *(.*bss)}
|
||||
BSS_END = .;
|
||||
STACK = ALIGN(16) + 0x1000;
|
||||
|
||||
. = 0xfffffff8; .data.ctl : { LONG(0xf0040000); LONG(STACK) }
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
// This is an automatically generated file by colin on Wed Mar 23 01:03:51 PM UTC 2022
|
||||
//
|
||||
// cmd: swerv -target=default -set build_axi4
|
||||
//
|
||||
|
||||
`include "common_defines.vh"
|
||||
`undef RV_ASSERT_ON
|
||||
`undef TEC_RV_ICG
|
||||
`define RV_PHYSICAL 1
|
||||
|
|
@ -0,0 +1,777 @@
|
|||
# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
# This is an automatically generated file by colin on Wed Mar 23 01:03:51 PM UTC 2022
|
||||
#
|
||||
# cmd: swerv -target=default -set build_axi4
|
||||
#
|
||||
# To use this in a perf script, use 'require $RV_ROOT/configs/config.pl'
|
||||
# Reference the hash via $config{name}..
|
||||
|
||||
|
||||
%config = (
|
||||
'csr' => {
|
||||
'pmpaddr6' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicawics' => {
|
||||
'mask' => '0x0130fffc',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'number' => '0x7c8',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'debug' => 'true'
|
||||
},
|
||||
'dicago' => {
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'mask' => '0x0',
|
||||
'debug' => 'true',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7cb'
|
||||
},
|
||||
'dicad1' => {
|
||||
'debug' => 'true',
|
||||
'number' => '0x7ca',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'mask' => '0x3'
|
||||
},
|
||||
'pmpcfg0' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mcgc' => {
|
||||
'reset' => '0x200',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7f8',
|
||||
'poke_mask' => '0x000003ff',
|
||||
'mask' => '0x000003ff'
|
||||
},
|
||||
'mhpmcounter3h' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr2' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr14' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mfdhs' => {
|
||||
'number' => '0x7cf',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Force Debug Halt Status',
|
||||
'mask' => '0x00000003'
|
||||
},
|
||||
'pmpaddr8' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mimpid' => {
|
||||
'reset' => '0x4',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'pmpaddr9' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mfdc' => {
|
||||
'mask' => '0x00071fff',
|
||||
'reset' => '0x00070040',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7f9'
|
||||
},
|
||||
'pmpcfg2' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr4' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter3' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mrac' => {
|
||||
'comment' => 'Memory region io and cache control.',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff',
|
||||
'shared' => 'true',
|
||||
'number' => '0x7c0'
|
||||
},
|
||||
'mpmc' => {
|
||||
'mask' => '0x2',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x2',
|
||||
'number' => '0x7c6'
|
||||
},
|
||||
'mhpmevent4' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'marchid' => {
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x00000010',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'time' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmevent3' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mitcnt0' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7d2'
|
||||
},
|
||||
'mhartid' => {
|
||||
'poke_mask' => '0xfffffff0',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'pmpaddr5' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'meicurpl' => {
|
||||
'number' => '0xbcc',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'External interrupt current priority level.',
|
||||
'mask' => '0xf'
|
||||
},
|
||||
'dcsr' => {
|
||||
'mask' => '0x00008c04',
|
||||
'reset' => '0x40000003',
|
||||
'exists' => 'true',
|
||||
'debug' => 'true',
|
||||
'poke_mask' => '0x00008dcc'
|
||||
},
|
||||
'mcpc' => {
|
||||
'comment' => 'Core pause',
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c2'
|
||||
},
|
||||
'mitbnd0' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d3'
|
||||
},
|
||||
'mitctl1' => {
|
||||
'mask' => '0x0000000f',
|
||||
'number' => '0x7d7',
|
||||
'reset' => '0x1',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mdccmect' => {
|
||||
'number' => '0x7f2',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mcountinhibit' => {
|
||||
'mask' => '0x7d',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'commnet' => 'Performance counter inhibit. One bit per counter.',
|
||||
'poke_mask' => '0x7d'
|
||||
},
|
||||
'mfdht' => {
|
||||
'comment' => 'Force Debug Halt Threshold',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'shared' => 'true',
|
||||
'mask' => '0x0000003f',
|
||||
'number' => '0x7ce'
|
||||
},
|
||||
'pmpaddr7' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter6h' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'tselect' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x3'
|
||||
},
|
||||
'mhpmcounter5h' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mhpmcounter4' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr10' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter6' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mhpmevent6' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'misa' => {
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x40001104',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mhpmcounter4h' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mitbnd1' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d6'
|
||||
},
|
||||
'mitctl0' => {
|
||||
'number' => '0x7d4',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x1',
|
||||
'mask' => '0x00000007'
|
||||
},
|
||||
'miccmect' => {
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7f1'
|
||||
},
|
||||
'mhpmcounter5' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'cycle' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr0' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr15' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr13' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mitcnt1' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d5'
|
||||
},
|
||||
'mie' => {
|
||||
'mask' => '0x70000888',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mhpmevent5' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mcounteren' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mip' => {
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'poke_mask' => '0x70000888',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'pmpaddr1' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr12' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'meipt' => {
|
||||
'mask' => '0xf',
|
||||
'comment' => 'External interrupt priority threshold.',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0xbc9'
|
||||
},
|
||||
'instret' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'meicidpl' => {
|
||||
'comment' => 'External interrupt claim id priority level.',
|
||||
'mask' => '0xf',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'number' => '0xbcb'
|
||||
},
|
||||
'mstatus' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x1800',
|
||||
'mask' => '0x88'
|
||||
},
|
||||
'pmpcfg3' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicad0' => {
|
||||
'mask' => '0xffffffff',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'number' => '0x7c9',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'debug' => 'true'
|
||||
},
|
||||
'pmpcfg1' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mscause' => {
|
||||
'number' => '0x7ff',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0x0000000f'
|
||||
},
|
||||
'mvendorid' => {
|
||||
'reset' => '0x45',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'micect' => {
|
||||
'number' => '0x7f0',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr11' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr3' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dmst' => {
|
||||
'comment' => 'Memory synch trigger: Flush caches in debug mode.',
|
||||
'mask' => '0x0',
|
||||
'debug' => 'true',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7c4'
|
||||
}
|
||||
},
|
||||
'numiregs' => '32',
|
||||
'testbench' => {
|
||||
'RV_TOP' => '`TOP.rvtop',
|
||||
'build_axi_native' => 1,
|
||||
'CPU_TOP' => '`RV_TOP.swerv',
|
||||
'sterr_rollback' => '0',
|
||||
'SDVT_AHB' => '0',
|
||||
'assert_on' => '',
|
||||
'clock_period' => '100',
|
||||
'ext_datawidth' => '64',
|
||||
'lderr_rollback' => '1',
|
||||
'build_axi4' => 1,
|
||||
'TOP' => 'tb_top',
|
||||
'ext_addrwidth' => '32'
|
||||
},
|
||||
'protection' => {
|
||||
'inst_access_mask1' => '0xffffffff',
|
||||
'inst_access_mask3' => '0xffffffff',
|
||||
'data_access_enable4' => '0x0',
|
||||
'data_access_mask3' => '0xffffffff',
|
||||
'inst_access_enable4' => '0x0',
|
||||
'data_access_mask1' => '0xffffffff',
|
||||
'inst_access_addr3' => '0x00000000',
|
||||
'inst_access_enable7' => '0x0',
|
||||
'inst_access_addr1' => '0x00000000',
|
||||
'data_access_addr1' => '0x00000000',
|
||||
'data_access_addr3' => '0x00000000',
|
||||
'data_access_enable7' => '0x0',
|
||||
'inst_access_enable0' => '0x0',
|
||||
'data_access_addr5' => '0x00000000',
|
||||
'inst_access_addr0' => '0x00000000',
|
||||
'inst_access_addr5' => '0x00000000',
|
||||
'data_access_addr0' => '0x00000000',
|
||||
'data_access_enable0' => '0x0',
|
||||
'data_access_mask5' => '0xffffffff',
|
||||
'inst_access_mask0' => '0xffffffff',
|
||||
'data_access_enable6' => '0x0',
|
||||
'data_access_enable2' => '0x0',
|
||||
'inst_access_enable1' => '0x0',
|
||||
'inst_access_enable6' => '0x0',
|
||||
'data_access_enable1' => '0x0',
|
||||
'inst_access_enable2' => '0x0',
|
||||
'inst_access_mask5' => '0xffffffff',
|
||||
'data_access_mask0' => '0xffffffff',
|
||||
'inst_access_mask6' => '0xffffffff',
|
||||
'inst_access_addr4' => '0x00000000',
|
||||
'data_access_addr7' => '0x00000000',
|
||||
'inst_access_addr7' => '0x00000000',
|
||||
'data_access_addr4' => '0x00000000',
|
||||
'data_access_mask6' => '0xffffffff',
|
||||
'data_access_enable5' => '0x0',
|
||||
'data_access_mask7' => '0xffffffff',
|
||||
'inst_access_enable3' => '0x0',
|
||||
'inst_access_addr6' => '0x00000000',
|
||||
'inst_access_mask4' => '0xffffffff',
|
||||
'data_access_mask4' => '0xffffffff',
|
||||
'data_access_addr6' => '0x00000000',
|
||||
'inst_access_mask7' => '0xffffffff',
|
||||
'inst_access_enable5' => '0x0',
|
||||
'data_access_enable3' => '0x0',
|
||||
'inst_access_addr2' => '0x00000000',
|
||||
'data_access_addr2' => '0x00000000',
|
||||
'inst_access_mask2' => '0xffffffff',
|
||||
'data_access_mask2' => '0xffffffff'
|
||||
},
|
||||
'iccm' => {
|
||||
'iccm_bank_index_lo' => 5,
|
||||
'iccm_data_cell' => 'ram_1024x39',
|
||||
'iccm_sadr' => '0xee000000',
|
||||
'iccm_num_banks_8' => '',
|
||||
'iccm_size' => 32,
|
||||
'iccm_bank_bits' => 3,
|
||||
'iccm_rows' => '1024',
|
||||
'iccm_eadr' => '0xee007fff',
|
||||
'iccm_size_32' => '',
|
||||
'iccm_index_bits' => 10,
|
||||
'iccm_bits' => 15,
|
||||
'iccm_num_banks' => '8',
|
||||
'iccm_reserved' => '0x1000',
|
||||
'iccm_region' => '0xe',
|
||||
'iccm_offset' => '0xe000000',
|
||||
'iccm_bank_hi' => 4
|
||||
},
|
||||
'target' => 'default',
|
||||
'num_mmode_perf_regs' => '4',
|
||||
'retstack' => {
|
||||
'ret_stack_size' => '4'
|
||||
},
|
||||
'memmap' => {
|
||||
'unused_region4' => '0x40000000',
|
||||
'unused_region7' => '0x10000000',
|
||||
'unused_region1' => '0x70000000',
|
||||
'consoleio' => '0xd0580000',
|
||||
'external_data' => '0xc0580000',
|
||||
'serialio' => '0xd0580000',
|
||||
'unused_region8' => '0x00000000',
|
||||
'debug_sb_mem' => '0xa0580000',
|
||||
'unused_region6' => '0x20000000',
|
||||
'external_data_1' => '0xb0000000',
|
||||
'unused_region2' => '0x60000000',
|
||||
'unused_region5' => '0x30000000',
|
||||
'unused_region0' => '0x90000000',
|
||||
'unused_region3' => '0x50000000'
|
||||
},
|
||||
'xlen' => 32,
|
||||
'harts' => 1,
|
||||
'perf_events' => [
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
30,
|
||||
31,
|
||||
32,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
37,
|
||||
38,
|
||||
39,
|
||||
40,
|
||||
41,
|
||||
42,
|
||||
43,
|
||||
44,
|
||||
45,
|
||||
46,
|
||||
47,
|
||||
48,
|
||||
49,
|
||||
50,
|
||||
54,
|
||||
55,
|
||||
56,
|
||||
512,
|
||||
513,
|
||||
514,
|
||||
515,
|
||||
516
|
||||
],
|
||||
'btb' => {
|
||||
'btb_array_depth' => 16,
|
||||
'btb_index1_lo' => '2',
|
||||
'btb_fold2_index_hash' => 0,
|
||||
'btb_index3_lo' => 10,
|
||||
'btb_toffset_size' => '12',
|
||||
'btb_index2_lo' => 6,
|
||||
'btb_btag_size' => 9,
|
||||
'btb_enable' => '1',
|
||||
'btb_addr_lo' => '2',
|
||||
'btb_index3_hi' => 13,
|
||||
'btb_index2_hi' => 9,
|
||||
'btb_btag_fold' => 1,
|
||||
'btb_size' => 32,
|
||||
'btb_addr_hi' => 5,
|
||||
'btb_index1_hi' => 5
|
||||
},
|
||||
'physical' => '1',
|
||||
'tec_rv_icg' => 'clockhdr',
|
||||
'bht' => {
|
||||
'bht_addr_hi' => 7,
|
||||
'bht_size' => 128,
|
||||
'bht_ghr_size' => 6,
|
||||
'bht_array_depth' => 64,
|
||||
'bht_ghr_hash_1' => 1,
|
||||
'bht_addr_lo' => '2',
|
||||
'bht_hash_string' => '{ghr[5:4], hashin[5:2]^ghr[4-1:0]} // cf1',
|
||||
'bht_ghr_range' => '5:0'
|
||||
},
|
||||
'dccm' => {
|
||||
'dccm_rows' => '1024',
|
||||
'dccm_sadr' => '0xf0040000',
|
||||
'dccm_data_cell' => 'ram_1024x39',
|
||||
'dccm_bank_bits' => 3,
|
||||
'dccm_num_banks_8' => '',
|
||||
'dccm_size' => 32,
|
||||
'dccm_enable' => '1',
|
||||
'dccm_fdata_width' => 39,
|
||||
'dccm_offset' => '0x40000',
|
||||
'dccm_reserved' => '0x1400',
|
||||
'dccm_data_width' => 32,
|
||||
'dccm_ecc_width' => 7,
|
||||
'dccm_region' => '0xf',
|
||||
'dccm_bits' => 15,
|
||||
'lsu_sb_bits' => 15,
|
||||
'dccm_index_bits' => 10,
|
||||
'dccm_width_bits' => 2,
|
||||
'dccm_num_banks' => '8',
|
||||
'dccm_eadr' => '0xf0047fff',
|
||||
'dccm_byte_width' => '4',
|
||||
'dccm_size_32' => ''
|
||||
},
|
||||
'config_key' => '32\'hdeadbeef',
|
||||
'regwidth' => '32',
|
||||
'bus' => {
|
||||
'sb_bus_id' => '1',
|
||||
'sb_bus_prty' => '2',
|
||||
'sb_bus_tag' => '1',
|
||||
'bus_prty_default' => '3',
|
||||
'lsu_bus_id' => '1',
|
||||
'lsu_bus_prty' => '2',
|
||||
'lsu_bus_tag' => 3,
|
||||
'ifu_bus_id' => '1',
|
||||
'dma_bus_tag' => '1',
|
||||
'ifu_bus_prty' => '2',
|
||||
'ifu_bus_tag' => '3',
|
||||
'dma_bus_id' => '1',
|
||||
'dma_bus_prty' => '2'
|
||||
},
|
||||
'nmi_vec' => '0x11110000',
|
||||
'icache' => {
|
||||
'icache_tag_bypass_enable' => '1',
|
||||
'icache_banks_way' => 2,
|
||||
'icache_data_index_lo' => 4,
|
||||
'icache_tag_num_bypass_width' => 2,
|
||||
'icache_tag_lo' => 13,
|
||||
'icache_size' => 16,
|
||||
'icache_num_lines_bank' => '64',
|
||||
'icache_bypass_enable' => '1',
|
||||
'icache_data_cell' => 'ram_512x68',
|
||||
'icache_bank_hi' => 3,
|
||||
'icache_bank_lo' => 3,
|
||||
'icache_data_width' => 64,
|
||||
'icache_tag_cell' => 'ram_128x21',
|
||||
'icache_status_bits' => 1,
|
||||
'icache_tag_depth' => '128',
|
||||
'icache_bank_bits' => 1,
|
||||
'icache_num_lines_way' => '128',
|
||||
'icache_bank_width' => 8,
|
||||
'icache_num_bypass' => '2',
|
||||
'icache_ln_sz' => 64,
|
||||
'icache_waypack' => '1',
|
||||
'icache_num_bypass_width' => 2,
|
||||
'icache_tag_index_lo' => '6',
|
||||
'icache_ecc' => '0',
|
||||
'icache_num_lines' => 256,
|
||||
'icache_data_depth' => '512',
|
||||
'icache_enable' => 1,
|
||||
'icache_num_ways' => 2,
|
||||
'icache_num_beats' => 8,
|
||||
'icache_beat_bits' => 3,
|
||||
'icache_fdata_width' => 68,
|
||||
'icache_tag_num_bypass' => '2',
|
||||
'icache_2banks' => '1',
|
||||
'icache_index_hi' => 12,
|
||||
'icache_scnd_last' => 6,
|
||||
'icache_beat_addr_hi' => 5
|
||||
},
|
||||
'pic' => {
|
||||
'pic_meigwclr_mask' => '0x0',
|
||||
'pic_meip_mask' => '0x0',
|
||||
'pic_meipl_mask' => '0xf',
|
||||
'pic_total_int_plus1' => 9,
|
||||
'pic_meipl_count' => 8,
|
||||
'pic_meigwclr_count' => 8,
|
||||
'pic_meie_offset' => '0x2000',
|
||||
'pic_bits' => 15,
|
||||
'pic_mpiccfg_mask' => '0x1',
|
||||
'pic_mpiccfg_offset' => '0x3000',
|
||||
'pic_offset' => '0xc0000',
|
||||
'pic_mpiccfg_count' => 1,
|
||||
'pic_meie_count' => 8,
|
||||
'pic_meipt_offset' => '0x3004',
|
||||
'pic_meigwclr_offset' => '0x5000',
|
||||
'pic_size' => 32,
|
||||
'pic_meigwctrl_count' => 8,
|
||||
'pic_meip_offset' => '0x1000',
|
||||
'pic_int_words' => 1,
|
||||
'pic_meigwctrl_offset' => '0x4000',
|
||||
'pic_meipt_count' => 8,
|
||||
'pic_region' => '0xf',
|
||||
'pic_total_int' => 8,
|
||||
'pic_meip_count' => 1,
|
||||
'pic_meipt_mask' => '0x0',
|
||||
'pic_meie_mask' => '0x1',
|
||||
'pic_meipl_offset' => '0x0000',
|
||||
'pic_base_addr' => '0xf00c0000',
|
||||
'pic_meigwctrl_mask' => '0x3'
|
||||
},
|
||||
'even_odd_trigger_chains' => 'true',
|
||||
'triggers' => [
|
||||
{
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'poke_mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'poke_mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
}
|
||||
],
|
||||
'reset_vec' => '0x80000000',
|
||||
'max_mmode_perf_event' => '516',
|
||||
'core' => {
|
||||
'fpga_optimize' => 1,
|
||||
'lsu_num_nbload_width' => '2',
|
||||
'icache_only' => 1,
|
||||
'bitmanip_zbf' => 0,
|
||||
'bitmanip_zbb' => 1,
|
||||
'lsu_stbuf_depth' => '4',
|
||||
'timer_legal_en' => '1',
|
||||
'no_iccm_no_icache' => 'derived',
|
||||
'fast_interrupt_redirect' => '1',
|
||||
'lsu2dma' => 0,
|
||||
'bitmanip_zbe' => 0,
|
||||
'iccm_only' => 'derived',
|
||||
'iccm_icache' => 'derived',
|
||||
'div_new' => 1,
|
||||
'bitmanip_zba' => 1,
|
||||
'dma_buf_depth' => '5',
|
||||
'bitmanip_zbp' => 0,
|
||||
'bitmanip_zbr' => 0,
|
||||
'lsu_num_nbload' => '4',
|
||||
'div_bit' => '4',
|
||||
'bitmanip_zbs' => 1,
|
||||
'bitmanip_zbc' => 1
|
||||
}
|
||||
);
|
||||
1;
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }
|
||||
always_comb begin
|
||||
case (address[14:0])
|
||||
15'b011000000000000 : mask[3:0] = 4'b0100;
|
||||
15'b100000000000100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000001000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000001100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000010000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000010100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000011000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000011100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000100000 : mask[3:0] = 4'b1000;
|
||||
15'b010000000000100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000001000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000001100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000010000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000010100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000011000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000011100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000100000 : mask[3:0] = 4'b0100;
|
||||
15'b000000000000100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000001000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000001100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000010000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000010100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000011000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000011100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000100000 : mask[3:0] = 4'b0010;
|
||||
default : mask[3:0] = 4'b0001;
|
||||
endcase
|
||||
end
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
@00000000
|
||||
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
|
||||
B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
|
||||
17 42 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
|
||||
05 02 E3 9B 02 FE B7 01 58 D0 17 42 00 00 13 02
|
||||
62 FC 83 02 02 00 23 80 51 00 05 02 E3 9B 02 FE
|
||||
63 00 00 00 B7 01 58 D0 93 02 F0 0F 23 80 51 00
|
||||
E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00
|
||||
@00004000
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 43
|
||||
6F 6C 69 6E 2E 6C 69 61 6E 67 20 45 4C 32 40 57
|
||||
44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 0A 00
|
||||
|
|
@ -0,0 +1,561 @@
|
|||
{
|
||||
"enable_zbe" : 0,
|
||||
"mmode_perf_events" : [
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
30,
|
||||
31,
|
||||
32,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
37,
|
||||
38,
|
||||
39,
|
||||
40,
|
||||
41,
|
||||
42,
|
||||
43,
|
||||
44,
|
||||
45,
|
||||
46,
|
||||
47,
|
||||
48,
|
||||
49,
|
||||
50,
|
||||
54,
|
||||
55,
|
||||
56,
|
||||
512,
|
||||
513,
|
||||
514,
|
||||
515,
|
||||
516
|
||||
],
|
||||
"fast_interrupt_redirect" : "1",
|
||||
"csr" : {
|
||||
"pmpaddr6" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicawics" : {
|
||||
"mask" : "0x0130fffc",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"number" : "0x7c8",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"debug" : "true"
|
||||
},
|
||||
"dicago" : {
|
||||
"comment" : "Cache diagnostics.",
|
||||
"mask" : "0x0",
|
||||
"debug" : "true",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7cb"
|
||||
},
|
||||
"dicad1" : {
|
||||
"debug" : "true",
|
||||
"number" : "0x7ca",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"mask" : "0x3"
|
||||
},
|
||||
"pmpcfg0" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mcgc" : {
|
||||
"reset" : "0x200",
|
||||
"exists" : "true",
|
||||
"number" : "0x7f8",
|
||||
"poke_mask" : "0x000003ff",
|
||||
"mask" : "0x000003ff"
|
||||
},
|
||||
"mhpmcounter3h" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr2" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr14" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mfdhs" : {
|
||||
"number" : "0x7cf",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Force Debug Halt Status",
|
||||
"mask" : "0x00000003"
|
||||
},
|
||||
"pmpaddr8" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mimpid" : {
|
||||
"reset" : "0x4",
|
||||
"exists" : "true",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"pmpaddr9" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mfdc" : {
|
||||
"mask" : "0x00071fff",
|
||||
"reset" : "0x00070040",
|
||||
"exists" : "true",
|
||||
"number" : "0x7f9"
|
||||
},
|
||||
"pmpcfg2" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr4" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter3" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mrac" : {
|
||||
"comment" : "Memory region io and cache control.",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff",
|
||||
"shared" : "true",
|
||||
"number" : "0x7c0"
|
||||
},
|
||||
"mpmc" : {
|
||||
"mask" : "0x2",
|
||||
"exists" : "true",
|
||||
"reset" : "0x2",
|
||||
"number" : "0x7c6"
|
||||
},
|
||||
"mhpmevent4" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"marchid" : {
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x00000010",
|
||||
"exists" : "true"
|
||||
},
|
||||
"time" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmevent3" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mitcnt0" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7d2"
|
||||
},
|
||||
"mhartid" : {
|
||||
"poke_mask" : "0xfffffff0",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"pmpaddr5" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"meicurpl" : {
|
||||
"number" : "0xbcc",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "External interrupt current priority level.",
|
||||
"mask" : "0xf"
|
||||
},
|
||||
"dcsr" : {
|
||||
"mask" : "0x00008c04",
|
||||
"reset" : "0x40000003",
|
||||
"exists" : "true",
|
||||
"debug" : "true",
|
||||
"poke_mask" : "0x00008dcc"
|
||||
},
|
||||
"mcpc" : {
|
||||
"comment" : "Core pause",
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"number" : "0x7c2"
|
||||
},
|
||||
"mitbnd0" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d3"
|
||||
},
|
||||
"mitctl1" : {
|
||||
"mask" : "0x0000000f",
|
||||
"number" : "0x7d7",
|
||||
"reset" : "0x1",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mdccmect" : {
|
||||
"number" : "0x7f2",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mcountinhibit" : {
|
||||
"mask" : "0x7d",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"commnet" : "Performance counter inhibit. One bit per counter.",
|
||||
"poke_mask" : "0x7d"
|
||||
},
|
||||
"mfdht" : {
|
||||
"comment" : "Force Debug Halt Threshold",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"shared" : "true",
|
||||
"mask" : "0x0000003f",
|
||||
"number" : "0x7ce"
|
||||
},
|
||||
"pmpaddr7" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter6h" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"tselect" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"mask" : "0x3"
|
||||
},
|
||||
"mhpmcounter5h" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mhpmcounter4" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr10" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter6" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mhpmevent6" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"misa" : {
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x40001104",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mhpmcounter4h" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mitbnd1" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d6"
|
||||
},
|
||||
"mitctl0" : {
|
||||
"number" : "0x7d4",
|
||||
"exists" : "true",
|
||||
"reset" : "0x1",
|
||||
"mask" : "0x00000007"
|
||||
},
|
||||
"miccmect" : {
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7f1"
|
||||
},
|
||||
"mhpmcounter5" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"cycle" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr0" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr15" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr13" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mitcnt1" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d5"
|
||||
},
|
||||
"mie" : {
|
||||
"mask" : "0x70000888",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mhpmevent5" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mcounteren" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mip" : {
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"poke_mask" : "0x70000888",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"pmpaddr1" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr12" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"meipt" : {
|
||||
"mask" : "0xf",
|
||||
"comment" : "External interrupt priority threshold.",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0xbc9"
|
||||
},
|
||||
"instret" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"meicidpl" : {
|
||||
"comment" : "External interrupt claim id priority level.",
|
||||
"mask" : "0xf",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"number" : "0xbcb"
|
||||
},
|
||||
"mstatus" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x1800",
|
||||
"mask" : "0x88"
|
||||
},
|
||||
"pmpcfg3" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicad0" : {
|
||||
"mask" : "0xffffffff",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"number" : "0x7c9",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"debug" : "true"
|
||||
},
|
||||
"pmpcfg1" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mscause" : {
|
||||
"number" : "0x7ff",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0x0000000f"
|
||||
},
|
||||
"mvendorid" : {
|
||||
"reset" : "0x45",
|
||||
"exists" : "true",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"micect" : {
|
||||
"number" : "0x7f0",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr11" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr3" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dmst" : {
|
||||
"comment" : "Memory synch trigger: Flush caches in debug mode.",
|
||||
"mask" : "0x0",
|
||||
"debug" : "true",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7c4"
|
||||
}
|
||||
},
|
||||
"memory_mapped_registers" : {
|
||||
"registers" : {
|
||||
"meie" : {
|
||||
"count" : 8,
|
||||
"address" : "0xf00c2004",
|
||||
"mask" : "0x1"
|
||||
},
|
||||
"meigwctrl" : {
|
||||
"address" : "0xf00c4004",
|
||||
"count" : 8,
|
||||
"mask" : "0x3"
|
||||
},
|
||||
"meip" : {
|
||||
"mask" : "0x0",
|
||||
"count" : 1,
|
||||
"address" : "0xf00c1000"
|
||||
},
|
||||
"meigwclr" : {
|
||||
"count" : 8,
|
||||
"address" : "0xf00c5004",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"mpiccfg" : {
|
||||
"mask" : "0x1",
|
||||
"address" : "0xf00c3000",
|
||||
"count" : 1
|
||||
},
|
||||
"meipl" : {
|
||||
"count" : 8,
|
||||
"address" : "0xf00c0004",
|
||||
"mask" : "0xf"
|
||||
}
|
||||
},
|
||||
"size" : "0x8000",
|
||||
"address" : "0xf00c0000",
|
||||
"default_mask" : 0
|
||||
},
|
||||
"enable_zbr" : 0,
|
||||
"xlen" : 32,
|
||||
"memmap" : {
|
||||
"serialio" : "0xd0580000",
|
||||
"consoleio" : "0xd0580000"
|
||||
},
|
||||
"store_error_rollback" : "0",
|
||||
"effective_address_compatible_with_base" : "true",
|
||||
"harts" : 1,
|
||||
"load_error_rollback" : "1",
|
||||
"enable_zbp" : 0,
|
||||
"num_mmode_perf_regs" : "4",
|
||||
"enable_zbf" : 0,
|
||||
"enable_zbb" : 1,
|
||||
"nmi_vec" : "0x11110000",
|
||||
"dccm" : {
|
||||
"offset" : "0x40000",
|
||||
"region" : "0xf",
|
||||
"size" : "0x8000"
|
||||
},
|
||||
"enable_zbs" : 1,
|
||||
"reset_vec" : "0x80000000",
|
||||
"enable_zba" : 1,
|
||||
"max_mmode_perf_event" : "516",
|
||||
"triggers" : [
|
||||
{
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"poke_mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"poke_mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
}
|
||||
],
|
||||
"even_odd_trigger_chains" : "true",
|
||||
"amo_illegal_outside_dccm" : "true",
|
||||
"enable_zbc" : 1
|
||||
}
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
build/
|
||||
obj_dir/
|
||||
gen/
|
||||
|
|
@ -8,22 +8,22 @@
|
|||
set -ex
|
||||
|
||||
PWD=$(pwd)
|
||||
SOC=$PWD/../../soc
|
||||
SOC=$PWD/../soc
|
||||
design=${1%/}
|
||||
|
||||
YOSYS_COARSE=true
|
||||
YOSYS_GLOBRST=false
|
||||
YOSYS_SPLITNETS=false
|
||||
TOP="soc_top"
|
||||
RTL=$(cat ../../soc/soc_top.mk)
|
||||
RTL=$(cat ../soc/soc_top.mk)
|
||||
|
||||
rtl_files=""
|
||||
|
||||
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
|
||||
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
|
||||
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
|
||||
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
|
||||
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
|
||||
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/build/el2_pdef.vh "
|
||||
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/build/common_defines.vh "
|
||||
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/build/pd_defines.vh "
|
||||
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/build/el2_param.vh "
|
||||
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/build/pic_map_auto.h "
|
||||
|
||||
for src in $RTL; do
|
||||
rtl_files="$rtl_files $SOC/$src"
|
||||
|
|
@ -44,7 +44,7 @@ sv2v -Ibuild $filelist > gen/soc_top.v
|
|||
{
|
||||
# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
|
||||
# for file in $rtl_files; do
|
||||
# echo "read_verilog -sv -I../../design/include $file"
|
||||
# echo "read_verilog -sv -I../design/include $file"
|
||||
# done
|
||||
echo "read_verilog gen/soc_top.v"
|
||||
|
||||
Loading…
Reference in New Issue