Commit Graph

9 Commits

Author SHA1 Message Date
Joseph Rahmeh ebfb8abf88 Branch 1.3 2020-11-17 11:14:35 -08:00
Joseph Rahmeh 2d26189faf Branch 1.3 2020-11-17 10:25:18 -08:00
Olof Kindgren 6815b77864 Fix typo in swerv.config causing wrong unsets to be printed
This is only for the summary of options. No functional change
2020-09-25 12:04:05 +02:00
Olof Kindgren 958d280546 Explicitly use python3 everywhere 2020-09-24 16:18:27 +02:00
Ajay Nath e1301d4d47 Added fpga_optimize help note top swerv.config 2020-03-30 17:55:40 -04:00
Joseph Rahmeh 179469ea5b Release 1.2 2020-03-27 13:38:09 -07:00
Joseph Rahmeh 1d2db09a2b Release 1.1 2020-03-04 15:36:01 -08:00
Olof Kindgren a08b395d8c Add FuseSoC support for SweRV EL2
This adds an initial FuseSoC core description file for SweRV EL2.

In addition to the core file there is also a python wrapper for
the core configuration (configs/swerv_config_gen.py) that is used
as a FuseSoC generator. There is also a tcl file (tools/vivado.tcl)
with Vivado-specific options that FuseSoC will pick up automatically
when Vivado is used.

It has been successfully tested in a modified SweRVolf SoC to boot
Zephyr OS in a Verilator simulation and on the Nexys A7 FPGA board.

TODO:

- Add target for running the bundled SweRV EL2 testbench
- Add Model/Questasim support
2020-01-31 10:36:53 +01:00
Joseph Rahmeh 7a48835c4e Initial checkin. 2020-01-22 14:22:50 -08:00