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  • f9eccf0f1b Add Verilator gen dot graph. master colin.liang 2022-11-03 17:44:52 +0800
  • e8224a4211 Refine synth.sh. colin 2022-03-23 14:01:00 +0000
  • e98bbf2deb Move demo/build to demo. colin 2022-03-23 13:08:16 +0000
  • 94c3d5f8ad Splite ram and rom to bank=8. colin 2022-03-23 13:00:34 +0000
  • dc1509b921 Add temp fpga file : synth.sh colin 2022-03-09 14:44:11 +0000
  • 9950499ac5 Delete no use files in toos. colin 2022-03-08 09:24:28 +0000
  • d86fef92e2 Enable gdb by openocd. colin 2022-03-08 09:18:19 +0000
  • ddf80fde8d Add jtag colin 2022-03-07 13:08:10 +0000
  • 7045b803ca
         Merge pull request #26 from dawidzim/update_make_for_riviera Ajay Nath 2021-05-21 11:21:03 -0400
  • 92ec09ddad remove -err VCP2694 Dawid Zimonczyk 2021-05-21 11:33:28 +0200
  • 59a46cea64 Updated README.md file. Joseph Rahmeh 2021-04-19 16:52:33 -0700
  • 5d11e392bd Updated PRM for version 1.4. Joseph Rahmeh 2021-04-19 13:57:57 -0700
  • 5e9c9361e4 Removed dead code. Joseph Rahmeh 2021-04-19 13:04:49 -0700
  • fb3354352b Branch 1.4 Joseph Rahmeh 2021-04-19 07:56:12 -0700
  • 9260b5567c
         Merge pull request #20 from olofk/config_gen Zvonimir Bandic 2021-01-15 10:26:44 -0800
  • 5672ff31b5 Update FuseSoC SweRV config generator Olof Kindgren 2021-01-15 15:13:01 +0100
  • ae8be27b34
         Merge pull request #17 from danielmlynek/riviera_support_fixes Ajay Nath 2020-11-20 14:44:26 -0500
  • 9755d8f94a Fixes in riviera support pushed into 1.3 Daniel Mlynek 2020-11-20 16:38:02 +0100
  • ebfb8abf88 Branch 1.3 Joseph Rahmeh 2020-11-17 11:14:35 -0800
  • 14b63d877f Branch 1.3 Joseph Rahmeh 2020-11-17 11:00:40 -0800
  • 068356d5da Branch 1.3 Joseph Rahmeh 2020-11-17 10:58:44 -0800
  • 2d26189faf Branch 1.3 Joseph Rahmeh 2020-11-17 10:25:18 -0800
  • 7570549cf7
         Merge pull request #10 from olofk/unsets_typo Ajay Nath 2020-09-25 08:38:40 -0400
  • 6815b77864 Fix typo in swerv.config causing wrong unsets to be printed Olof Kindgren 2020-09-25 12:04:02 +0200
  • e4a822bd50
         Merge pull request #9 from olofk/mem_lib_fix Ajay Nath 2020-09-24 20:14:24 -0400
  • 958d280546 Explicitly use python3 everywhere Olof Kindgren 2020-09-24 16:18:27 +0200
  • 025a720e35 Fix non-blocking assignment in mem_lib.sv Olof Kindgren 2020-09-24 16:16:03 +0200
  • 4c5674ca35
         Merge pull request #3 from olofk/corefixes jrahmeh 2020-08-19 10:07:45 -0500
  • b36d3bbff9 Fix toplevel in FuseSoC core file Olof Kindgren 2020-05-27 14:30:11 +0000
  • a5a72bf84f Fixed file names. Joseph Rahmeh 2020-05-15 07:33:45 -0700
  • c8b9057c8b Added hex data for sample programs. Joseph Rahmeh 2020-05-15 06:32:19 -0700
  • e1301d4d47 Added fpga_optimize help note top swerv.config Ajay Nath 2020-03-30 17:55:40 -0400
  • 188f57f72c
         Removed duplicate header jrahmeh 2020-03-30 16:08:40 -0500
  • e494ab6c9b Release 1.2 Joseph Rahmeh 2020-03-30 14:00:19 -0700
  • 062c27e9cb Updated PRM fo release 1.2 Joseph Rahmeh 2020-03-30 07:24:39 -0700
  • 179469ea5b Release 1.2 Joseph Rahmeh 2020-03-27 13:38:09 -0700
  • dfc027b4a5 Release 1.1 Joseph Rahmeh 2020-03-05 13:47:00 -0800
  • 5b42a1038a Renamed PRM file. Joseph Rahmeh 2020-03-05 12:53:19 -0800
  • 1aec19e556 Release 1.1 Joseph Rahmeh 2020-03-04 18:39:07 -0800
  • baedad0741 Added new files for release 1.1 Joseph Rahmeh 2020-03-04 18:37:08 -0800
  • 1d2db09a2b Release 1.1 Joseph Rahmeh 2020-03-04 15:36:01 -0800
  • a49b298b4a
         Merge pull request #2 from chipsalliance/fusesoc aprnath 2020-03-03 14:26:30 -0500
  • a08b395d8c Add FuseSoC support for SweRV EL2 Olof Kindgren 2020-01-31 10:31:19 +0100
  • cd8ec04439 Added .gitignore. Joseph Rahmeh 2020-01-24 06:57:16 -0800
  • 1cf874e09d Update RISC-V SweRV EL2 PRM.pdf tmw-wdc 2020-01-23 16:42:59 -0800
  • 7a48835c4e Initial checkin. Joseph Rahmeh 2020-01-22 14:22:50 -0800
  • 83c5a4f97a
         Update README.md jrahmeh 2020-01-09 16:16:59 -0600
  • 25593b49dc
         Initial commit jrahmeh 2020-01-09 16:16:40 -0600