15 lines
556 B
Markdown
15 lines
556 B
Markdown
# EL2 SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
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## Release Notes
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* Several bug fixes in debug module
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* Added new `dbg_rst_l` input for system wide reset to debug module. If debug module operation during core reset is not needed, this can be connected to `rst_l`.
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* Trace port width adjusted
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* Demo testbench has a synthesizable bridge to allow accessing the ICCM with load/stores via the DMA port. (*This only works with the AXI4 build*)
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# EL2 SweRV RISC-V Core<sup>TM</sup> 1.0 from Western Digital
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## Release Notes
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Initial release
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