2018-10-19 04:33:40 +08:00
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ifndef RISCV_TOOLS_PREFIX
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RISCV_TOOLS_PREFIX = /opt/riscv32ic/bin/riscv32-unknown-elf-
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endif
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CXX = $(RISCV_TOOLS_PREFIX)g++ -march=rv32i
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CC = $(RISCV_TOOLS_PREFIX)gcc -march=rv32i
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AS = $(RISCV_TOOLS_PREFIX)gcc -march=rv32i
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CXXFLAGS = -MD -Os -Wall -std=c++11
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CCFLAGS = -MD -Os -Wall
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#LDFLAGS = -Wl,--gc-sections,--no-relax
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LDFLAGS = -Wl,--gc-sections
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LDLIBS =
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test: testbench.vvp firmware32.hex
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vvp -l testbench.log -N testbench.vvp
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testbench.vvp: testbench.v ../../picorv32.v firmware_dbg.v
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2018-10-19 04:51:40 +08:00
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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2018-10-19 04:33:40 +08:00
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chmod -x testbench.vvp
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firmware32.hex: firmware.elf hex8tohex32.py
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
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python3 hex8tohex32.py firmware.tmp > firmware32.hex
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firmware_dbg.v: firmware.map
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python3 map2debug.py
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start.o: start.S
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$(CC) -c -nostdlib start.S $(LDLIBS)
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firmware.elf: firmware.o syscalls.o start.o
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$(CC) $(LDFLAGS),-Map=firmware.map -o $@ $^ -T sections.lds $(LDLIBS)
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chmod -x firmware.elf
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clean:
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rm -f *.o *.d *.tmp start.elf
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rm -f firmware.elf firmware.hex firmware32.hex
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rm -f testbench.vvp testbench.vcd
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-include *.d
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.PHONY: test clean
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