2015-06-09 18:45:45 +08:00
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read_verilog soc_top.v
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read_verilog ../../picorv32.v
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read_xdc synth_soc.xdc
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2015-06-10 22:48:06 +08:00
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synth_design -part xc7a35t-cpg236-1 -top soc_top
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2015-06-09 18:45:45 +08:00
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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write_verilog -force synth_soc.v
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2015-06-10 22:48:06 +08:00
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write_bitstream -force synth_soc.bit
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# write_mem_info -force synth_soc.mmi
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2015-06-09 18:45:45 +08:00
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