picorv32/scripts/vivado/synth_area.tcl

read_verilog ../../picorv32.v
read_xdc synth_area.xdc

synth_design -part xc7k70t-fbg676 -top picorv32_axi
opt_design -resynth_seq_area

report_utilization
report_timing
Makefile for Vivado scripts 2015-06-09 18:45:45 +08:00			`read_verilog ../../picorv32.v`
			`read_xdc synth_area.xdc`

Vivado 2015.2 area evaluation 2015-07-02 04:18:20 +08:00			`synth_design -part xc7k70t-fbg676 -top picorv32_axi`
Added resource utilization to xilinx eval 2015-06-28 19:49:36 +08:00			`opt_design -resynth_seq_area`
Makefile for Vivado scripts 2015-06-09 18:45:45 +08:00
			`report_utilization`
Enabled report_timing in vivado synth_area scripts 2015-07-08 16:16:10 +08:00			`report_timing`