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synth_area_large and synth_area_regular

This commit is contained in:
Tom Verbeure 2016-08-30 22:36:06 -07:00
parent 36152a5688
commit 209456a6c8
6 changed files with 15 additions and 22 deletions
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3
scripts/quartus/Makefile
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@ -57,5 +57,6 @@ table.txt:
clean: clean:
rm -rf firmware.bin firmware.elf firmware.hex firmware.map synth_*.log rm -rf firmware.bin firmware.elf firmware.hex firmware.map synth_*.log
rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/ rm -rf synth_system.v table.txt tab_*/
rm -rf synth_area_*_build

6
scripts/quartus/synth_area_large.qsf Normal file
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@ -0,0 +1,6 @@
set_global_assignment -name DEVICE ep4ce40f29c7
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TOP_LEVEL_ENTITY top_large
set_global_assignment -name VERILOG_FILE ../synth_area_top.v
set_global_assignment -name VERILOG_FILE ../../../picorv32.v
set_global_assignment -name SDC_FILE ../synth_area.sdc

10
scripts/quartus/synth_area_large.tcl
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@ -1,10 +0,0 @@
read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top top_large
opt_design -sweep -propconst -resynth_seq_area
opt_design -directive ExploreSequentialArea
report_utilization
report_timing

6
scripts/quartus/synth_area_regular.qsf Normal file
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@ -0,0 +1,6 @@
set_global_assignment -name DEVICE ep4ce40f29c7
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TOP_LEVEL_ENTITY top_regular
set_global_assignment -name VERILOG_FILE ../synth_area_top.v
set_global_assignment -name VERILOG_FILE ../../../picorv32.v
set_global_assignment -name SDC_FILE ../synth_area.sdc

10
scripts/quartus/synth_area_regular.tcl
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@ -1,10 +0,0 @@
read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top top_regular
opt_design -sweep -propconst -resynth_seq_area
opt_design -directive ExploreSequentialArea
report_utilization
report_timing

2
scripts/quartus/synth_area_small.qsf
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@ -1,4 +1,4 @@
set_global_assignment -name DEVICE ep4ce30f23c7 set_global_assignment -name DEVICE ep4ce40f29c7
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TOP_LEVEL_ENTITY top_small set_global_assignment -name TOP_LEVEL_ENTITY top_small
set_global_assignment -name VERILOG_FILE ../synth_area_top.v set_global_assignment -name VERILOG_FILE ../synth_area_top.v