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Add console.log output.

This commit is contained in:
colin.liang 2023-01-13 15:44:41 +08:00
parent e345620054
commit 287e1416ea
2 changed files with 14 additions and 4 deletions
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10
Makefile
View File

@ -22,8 +22,14 @@ CFLAGS = -MD -O3 -mabi=ilp32 -march=rv32im -DTIME -DRISCV
GIT_ENV = true GIT_ENV = true
test_verilator: build/testbench_verilator build/firmware.hex build/dhry.hex test_verilator: build/testbench_verilator build/firmware.hex build/dhry.hex
./build/testbench_verilator build/firmware.hex cd build && ./testbench_verilator firmware.hex
./build/testbench_verilator build/dhry.hex cd build && ./testbench_verilator dhry.hex
firmware: build/testbench_verilator
cd build && ./testbench_verilator firmware.hex
dhry: build/firmware.hex build/dhry.hex
cd build && ./testbench_verilator dhry.hex
build/testbench_verilator: testbench_wb.v picorv32.v testbench.cc build/testbench_verilator: testbench_wb.v picorv32.v testbench.cc
$(VERILATOR) --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench_wb.v picorv32.v testbench.cc \ $(VERILATOR) --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench_wb.v picorv32.v testbench.cc \

8
testbench_wb.v
View File

@ -142,6 +142,11 @@ module picorv32_wb #(
assign mem_ready = 1; assign mem_ready = 1;
integer fconsole;
initial begin
fconsole = $fopen("console.log", "w");
end
always @(posedge clk) begin always @(posedge clk) begin
mem_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx; mem_rdata[7:0] <= mem_la_read ? memory[mem_la_addr+0] : 'bx;
mem_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx; mem_rdata[15:8] <= mem_la_read ? memory[mem_la_addr+1] : 'bx;
@ -150,8 +155,7 @@ module picorv32_wb #(
if (mem_la_write) begin if (mem_la_write) begin
case (mem_la_addr) case (mem_la_addr)
32'h1000_0000: begin 32'h1000_0000: begin
$write("%c", mem_la_wdata); $fwrite(fconsole, "%c", mem_la_wdata);
$fflush();
end end
32'h2000_0000: begin 32'h2000_0000: begin
if (mem_la_wdata[31:0] == 123456789) exit = 1; if (mem_la_wdata[31:0] == 123456789) exit = 1;