Towards compressed ISA support
This commit is contained in:
		
							parent
							
								
									061b96be55
								
							
						
					
					
						commit
						3aed9f7c65
					
				
							
								
								
									
										13
									
								
								picorv32.v
								
								
								
								
							
							
						
						
									
										13
									
								
								picorv32.v
								
								
								
								
							|  | @ -277,10 +277,18 @@ module picorv32 #( | ||||||
| 								mem_rdata_q[14:12] <= 3'b 010; | 								mem_rdata_q[14:12] <= 3'b 010; | ||||||
| 							end | 							end | ||||||
| 							3'b100: begin | 							3'b100: begin | ||||||
|  | 								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR | ||||||
|  | 									mem_rdata_q[14:12] <= 3'b000; | ||||||
|  | 									mem_rdata_q[31:20] <= 12'b0; | ||||||
|  | 								end | ||||||
| 								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV | 								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV | ||||||
| 									mem_rdata_q[14:12] <= 3'b000; | 									mem_rdata_q[14:12] <= 3'b000; | ||||||
| 									mem_rdata_q[31:25] <= 7'b0000000; | 									mem_rdata_q[31:25] <= 7'b0000000; | ||||||
| 								end | 								end | ||||||
|  | 								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR | ||||||
|  | 									mem_rdata_q[14:12] <= 3'b000; | ||||||
|  | 									mem_rdata_q[31:20] <= 12'b0; | ||||||
|  | 								end | ||||||
| 							end | 							end | ||||||
| 							3'b110: begin // C.SWSP | 							3'b110: begin // C.SWSP | ||||||
| 								{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; | 								{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; | ||||||
|  | @ -574,6 +582,11 @@ module picorv32 #( | ||||||
| 									decoded_rs1 <= 0; | 									decoded_rs1 <= 0; | ||||||
| 									decoded_rs2 <= mem_rdata_latched[6:2]; | 									decoded_rs2 <= mem_rdata_latched[6:2]; | ||||||
| 								end | 								end | ||||||
|  | 								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR | ||||||
|  | 									instr_jalr <= 1; | ||||||
|  | 									decoded_rd <= 1; | ||||||
|  | 									decoded_rs1 <= mem_rdata_latched[11:7]; | ||||||
|  | 								end | ||||||
| 							end | 							end | ||||||
| 							3'b110: begin // C.SWSP | 							3'b110: begin // C.SWSP | ||||||
| 								is_sb_sh_sw <= 1; | 								is_sb_sh_sw <= 1; | ||||||
|  |  | ||||||
		Loading…
	
		Reference in New Issue