PicoSoC QSPI DDR progress
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Clifford Wolf
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7639e6ebac
commit
51436b1c50
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@ -55,7 +55,7 @@ GPIO pins mapped to the 32 bit word at address 0x03000000.
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| 30:23 | Reserved (read 0) |
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| 22 | DDR Enable bit (reset=0) |
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| 21 | QSPI Enable bit (reset=0) |
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| 20 | Continous Read Enable bit (reset=0) |
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| 20 | XIP Enable bit (reset=0) |
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| 19:16 | Number of QSPI dummy cycles (reset=0) |
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| 15:12 | Reserved (read 0) |
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| 11:8 | IO Output enable bits in bit bang mode |
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@ -64,3 +64,13 @@ GPIO pins mapped to the 32 bit word at address 0x03000000.
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| 4 | Serial clock line in bit bang mode |
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| 3:0 | IO data bits in bit bang mode |
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The following settings for XIP/DDR/QSPI modes are valid:
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| XIP | DDR | QSPI | Read Command Byte | Mode Byte |
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| :-: | :-: | :--: | :-------------------- | :-------: |
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| 0 | 0 | 0 | 03h Read | N/A |
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| 0 | 0 | 1 | EBh Quad I/O Read | FFh |
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| 1 | 0 | 1 | EBh Quad I/O Read | A5h / FFh |
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| 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh |
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| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h / FFh |
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@ -222,7 +222,9 @@ void cmd_benchmark()
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void main()
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{
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reg_uart_clkdiv = 104;
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set_quad_spi_flag();
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// reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00600000;
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while (getchar_prompt("Press ENTER to continue..\n") != '\r') { /* wait */ }
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@ -266,9 +268,11 @@ void main()
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print("\n");
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print(" [1] Read SPI Flash ID\n");
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print(" [2] Read SPI Config Regs\n");
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print(" [3] Enable/disable DDR\n");
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print(" [4] Enable/disable QSPI\n");
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print(" [5] Enable/disable XIP\n");
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print(" [3] Switch to QSPI DDR XIP mode\n");
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print(" [4] Switch to QSPI DDR mode\n");
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print(" [5] Switch to QSPI XIP mode\n");
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print(" [6] Switch to QSPI mode\n");
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print(" [7] Switch to default mode\n");
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print(" [0] Run simplistic benchmark\n");
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print("\n");
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@ -289,13 +293,19 @@ void main()
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cmd_read_flash_regs();
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break;
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case '3':
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reg_spictrl ^= 1 << 22;
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reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00700000;
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break;
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case '4':
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reg_spictrl ^= 1 << 21;
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reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00600000;
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break;
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case '5':
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reg_spictrl ^= 1 << 20;
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reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00300000;
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break;
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case '6':
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reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00200000;
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break;
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case '7':
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reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00000000;
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break;
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case '0':
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cmd_benchmark();
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@ -27,7 +27,10 @@ module testbench;
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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repeat (200000) @(posedge clk);
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repeat (6) begin
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repeat (50000) @(posedge clk);
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$display("+50000 cycles");
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end
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$finish;
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end
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@ -143,6 +143,18 @@ module spimemio (
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wire xfer_io2_do;
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wire xfer_io3_do;
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reg xfer_io0_90;
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reg xfer_io1_90;
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reg xfer_io2_90;
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reg xfer_io3_90;
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always @(negedge clk) begin
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xfer_io0_90 <= xfer_io0_do;
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xfer_io1_90 <= xfer_io1_do;
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xfer_io2_90 <= xfer_io2_do;
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xfer_io3_90 <= xfer_io3_do;
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end
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assign flash_csb = config_en ? xfer_csb : config_csb;
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assign flash_clk = config_en ? xfer_clk : config_clk;
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@ -151,10 +163,10 @@ module spimemio (
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assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];
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assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];
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assign flash_io0_do = config_en ? xfer_io0_do : config_do[0];
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assign flash_io1_do = config_en ? xfer_io1_do : config_do[1];
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assign flash_io2_do = config_en ? xfer_io2_do : config_do[2];
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assign flash_io3_do = config_en ? xfer_io3_do : config_do[3];
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assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
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assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
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assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
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assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
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spimemio_xfer xfer (
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.clk (clk ),
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@ -1,8 +1,10 @@
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.section .text
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start:
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# zero-initialize register file
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addi x1, zero, 0
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addi x2, zero, 0
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# x2 (sp) is initialized by reset
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addi x3, zero, 0
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addi x4, zero, 0
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addi x5, zero, 0
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@ -33,9 +35,14 @@ addi x29, zero, 0
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addi x30, zero, 0
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addi x31, zero, 0
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li sp, 4*256
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call main
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# zero initialize scratchpad memory
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setmemloop:
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sw zero, 0(x1)
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addi x1, x1, 4
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blt x1, sp, setmemloop
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# call main
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call main
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loop:
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j loop
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