PicoSoC QSPI DDR progress

picosoc/README.md

@@ -55,7 +55,7 @@ GPIO pins mapped to the 32 bit word at address 0x03000000.
 |  30:23 | Reserved (read 0)                                         |
 |     22 | DDR Enable bit (reset=0)                                  |
 |     21 | QSPI Enable bit (reset=0)                                 |
-|     20 | Continous Read Enable bit (reset=0)                       |
+|     20 | XIP Enable bit (reset=0)                                  |
 |  19:16 | Number of QSPI dummy cycles (reset=0)                     |
 |  15:12 | Reserved (read 0)                                         |
 |   11:8 | IO Output enable bits in bit bang mode                    |
@@ -64,3 +64,13 @@ GPIO pins mapped to the 32 bit word at address 0x03000000.
 |      4 | Serial clock line in bit bang mode                        |
 |    3:0 | IO data bits in bit bang mode                             |
 
+The following settings for XIP/DDR/QSPI modes are valid:
+
+| XIP | DDR | QSPI | Read Command Byte     | Mode Byte |
+| :-: | :-: | :--: | :-------------------- | :-------: |
+|   0 |   0 |    0 | 03h Read              | N/A       |
+|   0 |   0 |    1 | EBh Quad I/O Read     | FFh       |
+|   1 |   0 |    1 | EBh Quad I/O Read     | A5h / FFh |
+|   0 |   1 |    1 | EDh DDR Quad I/O Read | FFh       |
+|   1 |   1 |    1 | EDh DDR Quad I/O Read | A5h / FFh |
+

picosoc/firmware.c

@@ -222,7 +222,9 @@ void cmd_benchmark()
 void main()
 {
 	reg_uart_clkdiv = 104;
+
 	set_quad_spi_flag();
+	// reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00600000;
 
 	while (getchar_prompt("Press ENTER to continue..\n") != '\r') { /* wait */ }
 
@@ -266,9 +268,11 @@ void main()
 		print("\n");
 		print("   [1] Read SPI Flash ID\n");
 		print("   [2] Read SPI Config Regs\n");
-		print("   [3] Enable/disable DDR\n");
+		print("   [3] Switch to QSPI DDR XIP mode\n");
-		print("   [4] Enable/disable QSPI\n");
+		print("   [4] Switch to QSPI DDR mode\n");
-		print("   [5] Enable/disable XIP\n");
+		print("   [5] Switch to QSPI XIP mode\n");
+		print("   [6] Switch to QSPI mode\n");
+		print("   [7] Switch to default mode\n");
 		print("   [0] Run simplistic benchmark\n");
 		print("\n");
 
@@ -289,13 +293,19 @@ void main()
 				cmd_read_flash_regs();
 				break;
 			case '3':
-				reg_spictrl ^= 1 << 22;
+				reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00700000;
 				break;
 			case '4':
-				reg_spictrl ^= 1 << 21;
+				reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00600000;
 				break;
 			case '5':
-				reg_spictrl ^= 1 << 20;
+				reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00300000;
+				break;
+			case '6':
+				reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00200000;
+				break;
+			case '7':
+				reg_spictrl = (reg_spictrl & ~0x00700000) | 0x00000000;
 				break;
 			case '0':
 				cmd_benchmark();

picosoc/hx8kdemo_tb.v

@@ -27,7 +27,10 @@ module testbench;
 		$dumpfile("testbench.vcd");
 		$dumpvars(0, testbench);
 
-		repeat (200000) @(posedge clk);
+		repeat (6) begin
+			repeat (50000) @(posedge clk);
+			$display("+50000 cycles");
+		end
 		$finish;
 	end
 

picosoc/spimemio.v

@@ -143,6 +143,18 @@ module spimemio (
 	wire xfer_io2_do;
 	wire xfer_io3_do;
 
+	reg xfer_io0_90;
+	reg xfer_io1_90;
+	reg xfer_io2_90;
+	reg xfer_io3_90;
+
+	always @(negedge clk) begin
+		xfer_io0_90 <= xfer_io0_do;
+		xfer_io1_90 <= xfer_io1_do;
+		xfer_io2_90 <= xfer_io2_do;
+		xfer_io3_90 <= xfer_io3_do;
+	end
+
 	assign flash_csb = config_en ? xfer_csb : config_csb;
 	assign flash_clk = config_en ? xfer_clk : config_clk;
 
@@ -151,10 +163,10 @@ module spimemio (
 	assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];
 	assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];
 
-	assign flash_io0_do = config_en ? xfer_io0_do : config_do[0];
+	assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
-	assign flash_io1_do = config_en ? xfer_io1_do : config_do[1];
+	assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
-	assign flash_io2_do = config_en ? xfer_io2_do : config_do[2];
+	assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
-	assign flash_io3_do = config_en ? xfer_io3_do : config_do[3];
+	assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
 
 	spimemio_xfer xfer (
 		.clk          (clk         ),

picosoc/start.s

@@ -1,8 +1,10 @@
 .section .text
 
 start:
+
+# zero-initialize register file
 addi x1, zero, 0
-addi x2, zero, 0
+# x2 (sp) is initialized by reset
 addi x3, zero, 0
 addi x4, zero, 0
 addi x5, zero, 0
@@ -33,9 +35,14 @@ addi x29, zero, 0
 addi x30, zero, 0
 addi x31, zero, 0
 
-li sp, 4*256
+# zero initialize scratchpad memory
-call main
+setmemloop:
+sw zero, 0(x1)
+addi x1, x1, 4
+blt x1, sp, setmemloop
 
+# call main
+call main
 loop:
 j loop