format code.
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27
picorv32.v
27
picorv32.v
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@ -357,27 +357,10 @@ module picorv32 #(
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reg instr_lui, instr_auipc, instr_jal, instr_jalr;
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reg instr_lui, instr_auipc, instr_jal, instr_jalr;
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reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
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reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
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reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
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reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
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reg
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reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori;
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instr_addi,
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reg instr_andi, instr_slli, instr_srli, instr_srai;
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instr_slti,
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reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu;
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instr_sltiu,
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reg instr_xor, instr_srl, instr_sra, instr_or, instr_and;
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instr_xori,
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instr_ori,
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instr_andi,
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instr_slli,
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instr_srli,
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instr_srai;
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reg
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instr_add,
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instr_sub,
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instr_sll,
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instr_slt,
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instr_sltu,
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instr_xor,
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instr_srl,
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instr_sra,
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instr_or,
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instr_and;
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reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
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reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
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reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
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reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
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wire instr_trap;
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wire instr_trap;
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@ -914,7 +897,7 @@ module picorv32 #(
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set_mem_do_wdata = 0;
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set_mem_do_wdata = 0;
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alu_out_0_q <= alu_out_0;
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alu_out_0_q <= alu_out_0;
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alu_out_q <= alu_out;
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alu_out_q <= alu_out;
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if (launch_next_insn) begin
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if (launch_next_insn) begin
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dbg_rs1val <= 'bx;
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dbg_rs1val <= 'bx;
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