Break out AXI4 memory to a separate module
This commit also adds support for setting the AXI_TEST and VERBOSE defines as plusargs or parameters
This commit is contained in:
Olof Kindgren
parent
c4c477180e
commit
8343315aa7
18
Makefile
18
Makefile
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@ -27,24 +27,20 @@ check.smt2: picorv32.v
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test_sp: testbench_sp.exe firmware/firmware.hex
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vvp -N testbench_sp.exe
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test_axi: testbench_axi.exe firmware/firmware.hex
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vvp -N testbench_axi.exe
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test_axi: testbench.exe firmware/firmware.hex
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vvp -N testbench.exe +axi_test
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test_synth: testbench_synth.exe firmware/firmware.hex
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vvp -N testbench_synth.exe
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testbench.exe: testbench.v picorv32.v
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iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v picorv32.v
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testbench.exe: testbench.v axi4_memory.v picorv32.v
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iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v axi4_memory.v picorv32.v
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chmod -x testbench.exe
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testbench_sp.exe: testbench.v picorv32.v
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iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v picorv32.v
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testbench_sp.exe: testbench.v axi4_memory.v picorv32.v
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iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v axi4_memory.v picorv32.v
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chmod -x testbench_sp.exe
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testbench_axi.exe: testbench.v picorv32.v
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iverilog -o testbench_axi.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DAXI_TEST testbench.v picorv32.v
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chmod -x testbench_axi.exe
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testbench_synth.exe: testbench.v synth.v
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iverilog -o testbench_synth.exe testbench.v synth.v
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chmod -x testbench_synth.exe
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@ -81,7 +77,7 @@ toc:
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clean:
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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testbench.exe testbench_sp.exe testbench_axi.exe testbench_synth.exe testbench.vcd
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testbench.exe testbench_sp.exe testbench_synth.exe testbench.vcd
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.PHONY: test view test_sp test_axi test_synth toc clean
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@ -0,0 +1,193 @@
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// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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module axi4_memory #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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) (
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input clk,
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input mem_axi_awvalid,
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output reg mem_axi_awready = 0,
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input [31:0] mem_axi_awaddr,
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input [ 2:0] mem_axi_awprot,
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input mem_axi_wvalid,
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output reg mem_axi_wready = 0,
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input [31:0] mem_axi_wdata,
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input [ 3:0] mem_axi_wstrb,
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output reg mem_axi_bvalid = 0,
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input mem_axi_bready,
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input mem_axi_arvalid,
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output reg mem_axi_arready = 0,
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input [31:0] mem_axi_araddr,
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input [ 2:0] mem_axi_arprot,
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output mem_axi_rvalid = 0,
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input mem_axi_rready,
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output reg [31:0] mem_axi_rdata
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);
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reg [31:0] memory [0:64*1024/4-1] /* verilator public */;
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reg verbose;
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initial verbose = $test$plusargs("verbose") || VERBOSE;
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reg axi_test;
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initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
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reg [63:0] xorshift64_state = 64'd88172645463325252;
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg [2:0] fast_axi_transaction = ~0;
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reg [4:0] async_axi_transaction = ~0;
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reg [4:0] delay_axi_transaction = 0;
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always @(posedge clk) begin
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if (axi_test) begin
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xorshift64_next;
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{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
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end
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end
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reg latched_raddr_en = 0;
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reg latched_waddr_en = 0;
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reg latched_wdata_en = 0;
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reg fast_raddr = 0;
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reg fast_waddr = 0;
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reg fast_wdata = 0;
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reg [31:0] latched_raddr;
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reg [31:0] latched_waddr;
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reg [31:0] latched_wdata;
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reg [ 3:0] latched_wstrb;
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reg latched_rinsn;
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task handle_axi_arvalid; begin
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mem_axi_arready <= 1;
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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fast_raddr <= 1;
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end endtask
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task handle_axi_awvalid; begin
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mem_axi_awready <= 1;
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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fast_waddr <= 1;
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end endtask
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task handle_axi_wvalid; begin
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mem_axi_wready <= 1;
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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fast_wdata <= 1;
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end endtask
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task handle_axi_rvalid; begin
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if(verbose)
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$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
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if (latched_raddr < 64*1024) begin
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mem_axi_rdata <= memory[latched_raddr >> 2];
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mem_axi_rvalid <= 1;
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latched_raddr_en = 0;
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end else begin
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$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
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$finish;
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end
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end endtask
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task handle_axi_bvalid; begin
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if (verbose)
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
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if (latched_waddr < 64*1024) begin
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if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
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if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
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if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
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if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
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end else
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if (latched_waddr == 32'h1000_0000) begin
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if (verbose) begin
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if (32 <= latched_wdata && latched_wdata < 128)
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$display("OUT: '%c'", latched_wdata[7:0]);
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else
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$display("OUT: %3d", latched_wdata);
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end else begin
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$write("%c", latched_wdata[7:0]);
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`ifndef VERILATOR
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$fflush();
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`endif
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end
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end else begin
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$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
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$finish;
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end
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mem_axi_bvalid <= 1;
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latched_waddr_en = 0;
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latched_wdata_en = 0;
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end endtask
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always @(negedge clk) begin
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid;
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid;
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if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid;
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end
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always @(posedge clk) begin
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mem_axi_arready <= 0;
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mem_axi_awready <= 0;
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mem_axi_wready <= 0;
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fast_raddr <= 0;
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fast_waddr <= 0;
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fast_wdata <= 0;
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if (mem_axi_rvalid && mem_axi_rready) begin
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mem_axi_rvalid <= 0;
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end
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if (mem_axi_bvalid && mem_axi_bready) begin
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mem_axi_bvalid <= 0;
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end
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if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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end
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if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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end
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if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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end
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid;
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid;
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if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
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end
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endmodule
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202
testbench.v
202
testbench.v
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@ -8,7 +8,10 @@
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`timescale 1 ns / 1 ps
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// `define VERBOSE
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module testbench;
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module testbench #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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);
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reg clk = 1;
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reg resetn = 0;
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@ -29,26 +32,54 @@ module testbench;
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end
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wire mem_axi_awvalid;
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reg mem_axi_awready = 0;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [ 2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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reg mem_axi_wready = 0;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [ 3:0] mem_axi_wstrb;
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reg mem_axi_bvalid = 0;
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wire mem_axi_bready;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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reg mem_axi_arready = 0;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [ 2:0] mem_axi_arprot;
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reg mem_axi_rvalid = 0;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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reg [31:0] mem_axi_rdata;
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wire [31:0] mem_axi_rdata;
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axi4_memory #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) mem (
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.clk (clk ),
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.mem_axi_awvalid (mem_axi_awvalid ),
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.mem_axi_awready (mem_axi_awready ),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid (mem_axi_arvalid ),
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.mem_axi_arready (mem_axi_arready ),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata )
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);
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picorv32_axi #(
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`ifdef SP_TEST
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@ -80,160 +111,7 @@ module testbench;
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.irq (irq )
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);
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reg [31:0] memory [0:64*1024/4-1];
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initial $readmemh("firmware/firmware.hex", memory);
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reg [63:0] xorshift64_state = 64'd88172645463325252;
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg [2:0] fast_axi_transaction = ~0;
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reg [4:0] async_axi_transaction = ~0;
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reg [4:0] delay_axi_transaction = 0;
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`ifdef AXI_TEST
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always @(posedge clk) begin
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xorshift64_next;
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{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
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end
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`endif
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reg latched_raddr_en = 0;
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reg latched_waddr_en = 0;
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reg latched_wdata_en = 0;
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reg fast_raddr = 0;
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reg fast_waddr = 0;
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reg fast_wdata = 0;
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reg [31:0] latched_raddr;
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reg [31:0] latched_waddr;
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reg [31:0] latched_wdata;
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reg [ 3:0] latched_wstrb;
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reg latched_rinsn;
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task handle_axi_arvalid; begin
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mem_axi_arready <= 1;
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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fast_raddr <= 1;
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end endtask
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task handle_axi_awvalid; begin
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mem_axi_awready <= 1;
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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fast_waddr <= 1;
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end endtask
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task handle_axi_wvalid; begin
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mem_axi_wready <= 1;
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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fast_wdata <= 1;
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end endtask
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task handle_axi_rvalid; begin
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`ifdef VERBOSE
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$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
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`endif
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if (latched_raddr < 64*1024) begin
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mem_axi_rdata <= memory[latched_raddr >> 2];
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mem_axi_rvalid <= 1;
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latched_raddr_en = 0;
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end else begin
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$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
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$finish;
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end
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end endtask
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task handle_axi_bvalid; begin
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`ifdef VERBOSE
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
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`endif
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if (latched_waddr < 64*1024) begin
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if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
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if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
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if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
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if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
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end else
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if (latched_waddr == 32'h1000_0000) begin
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`ifdef VERBOSE
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if (32 <= latched_wdata && latched_wdata < 128)
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$display("OUT: '%c'", latched_wdata);
|
||||
else
|
||||
$display("OUT: %3d", latched_wdata);
|
||||
`else
|
||||
$write("%c", latched_wdata);
|
||||
$fflush();
|
||||
`endif
|
||||
end else begin
|
||||
$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
|
||||
$finish;
|
||||
end
|
||||
mem_axi_bvalid <= 1;
|
||||
latched_waddr_en = 0;
|
||||
latched_wdata_en = 0;
|
||||
end endtask
|
||||
|
||||
always @(negedge clk) begin
|
||||
if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid;
|
||||
if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid;
|
||||
if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid;
|
||||
if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid;
|
||||
if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
mem_axi_arready <= 0;
|
||||
mem_axi_awready <= 0;
|
||||
mem_axi_wready <= 0;
|
||||
|
||||
fast_raddr <= 0;
|
||||
fast_waddr <= 0;
|
||||
fast_wdata <= 0;
|
||||
|
||||
if (mem_axi_rvalid && mem_axi_rready) begin
|
||||
mem_axi_rvalid <= 0;
|
||||
end
|
||||
|
||||
if (mem_axi_bvalid && mem_axi_bready) begin
|
||||
mem_axi_bvalid <= 0;
|
||||
end
|
||||
|
||||
if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin
|
||||
latched_raddr = mem_axi_araddr;
|
||||
latched_rinsn = mem_axi_arprot[2];
|
||||
latched_raddr_en = 1;
|
||||
end
|
||||
|
||||
if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin
|
||||
latched_waddr = mem_axi_awaddr;
|
||||
latched_waddr_en = 1;
|
||||
end
|
||||
|
||||
if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin
|
||||
latched_wdata = mem_axi_wdata;
|
||||
latched_wstrb = mem_axi_wstrb;
|
||||
latched_wdata_en = 1;
|
||||
end
|
||||
|
||||
if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid;
|
||||
if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid;
|
||||
if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid;
|
||||
|
||||
if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
|
||||
if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
|
||||
end
|
||||
initial $readmemh("firmware/firmware.hex", mem.memory);
|
||||
|
||||
initial begin
|
||||
if ($test$plusargs("vcd")) begin
|
||||
|
|
|
|||
Loading…
Reference in New Issue