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Remote ENABLE_REGS_DUALPORT and init reg zero.

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colin.liang 2023-01-12 16:09:10 +08:00
parent 8b3d3390f5
commit af85947a58
1 changed files with 51 additions and 83 deletions
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134
picorv32.v
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@ -52,7 +52,6 @@
module picorv32 #( module picorv32 #(
parameter [ 0:0] ENABLE_REGS_16_31 = 1, parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0, parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1, parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0, parameter [ 0:0] BARREL_SHIFTER = 0,
@ -66,7 +65,6 @@ module picorv32 #(
parameter [ 0:0] ENABLE_IRQ_QREGS = 1, parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1, parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0, parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
@ -153,14 +151,6 @@ module picorv32 #(
`ifndef PICORV32_REGS `ifndef PICORV32_REGS
reg [31:0] cpuregs [0:regfile_size-1]; reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif `endif
task empty_statement; task empty_statement;
@ -964,31 +954,22 @@ module picorv32 #(
always @* begin always @* begin
decoded_rs = 'bx; decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS `ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else `else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif `endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end end
`else `else
wire[31:0] cpuregs_rdata1; wire[31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2; wire[31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd; wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; wire [5:0] cpuregs_raddr1 = decoded_rs1;
wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; wire [5:0] cpuregs_raddr2 = decoded_rs2;
`PICORV32_REGS cpuregs ( `PICORV32_REGS cpuregs (
.clk(clk), .clk(clk),
@ -1003,14 +984,8 @@ module picorv32 #(
always @* begin always @* begin
decoded_rs = 'bx; decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end end
`endif `endif
@ -1193,31 +1168,27 @@ module picorv32 #(
reg_op1 <= cpuregs_rs1; reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1; dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin pcpi_valid <= 1;
pcpi_valid <= 1; `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) reg_sh <= cpuregs_rs2;
reg_sh <= cpuregs_rs2; reg_op2 <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2; dbg_rs2val <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2; dbg_rs2val_valid <= 1;
dbg_rs2val_valid <= 1; if (pcpi_int_ready) begin
if (pcpi_int_ready) begin mem_do_rinst <= 1;
mem_do_rinst <= 1; pcpi_valid <= 0;
pcpi_valid <= 0; reg_out <= pcpi_int_rd;
reg_out <= pcpi_int_rd; latched_store <= pcpi_int_wr;
latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch;
end else
if (pcpi_timeout || instr_ecall_ebreak) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch; cpu_state <= cpu_state_fetch;
end else end else
if (pcpi_timeout || instr_ecall_ebreak) begin cpu_state <= cpu_state_trap;
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end end
end else begin end else begin
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
@ -1331,32 +1302,29 @@ module picorv32 #(
reg_op1 <= cpuregs_rs1; reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1; dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1; dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) reg_sh <= cpuregs_rs2;
reg_sh <= cpuregs_rs2; reg_op2 <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2; dbg_rs2val <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2; dbg_rs2val_valid <= 1;
dbg_rs2val_valid <= 1; (* parallel_case *)
(* parallel_case *) case (1'b1)
case (1'b1) is_sb_sh_sw: begin
is_sb_sh_sw: begin cpu_state <= cpu_state_stmem;
cpu_state <= cpu_state_stmem; mem_do_rinst <= 1;
mem_do_rinst <= 1; end
end is_sll_srl_sra && !BARREL_SHIFTER: begin
is_sll_srl_sra && !BARREL_SHIFTER: begin cpu_state <= cpu_state_shift;
cpu_state <= cpu_state_shift; end
end default: begin
default: begin if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); alu_wait <= 1;
alu_wait <= 1; end else
end else mem_do_rinst <= mem_do_prefetch;
mem_do_rinst <= mem_do_prefetch; cpu_state <= cpu_state_exec;
cpu_state <= cpu_state_exec; end
end endcase
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end end
endcase endcase
end end