Remove TWO_CYCLE_COMPARE.
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picorv32.v
32
picorv32.v
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@ -45,7 +45,6 @@
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module picorv32 #(
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parameter [0:0] TWO_STAGE_SHIFT = 1,
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parameter [0:0] BARREL_SHIFTER = 0,
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parameter [0:0] TWO_CYCLE_COMPARE = 0,
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parameter [0:0] ENABLE_TRACE = 0,
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parameter [31:0] MASKED_IRQ = 32'h0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'hffff_ffff,
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@ -810,7 +809,6 @@ module picorv32 #(
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reg [31:0] alu_out, alu_out_q;
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reg alu_out_0, alu_out_0_q;
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reg alu_wait, alu_wait_2; // AAAA
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reg [31:0] alu_add_sub;
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reg [31:0] alu_shl, alu_shr;
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@ -833,10 +831,8 @@ module picorv32 #(
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instr_bne: alu_out_0 = !alu_eq;
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instr_bge: alu_out_0 = !alu_lts;
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instr_bgeu: alu_out_0 = !alu_ltu;
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is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
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alu_out_0 = alu_lts;
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is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq, instr_bne, instr_bge, instr_bgeu}):
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alu_out_0 = alu_ltu;
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is_slti_blt_slt: alu_out_0 = alu_lts;
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is_sltiu_bltu_sltu: alu_out_0 = alu_ltu;
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endcase
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alu_out = 'bx;
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@ -922,9 +918,6 @@ module picorv32 #(
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alu_out_0_q <= alu_out_0;
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alu_out_q <= alu_out;
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alu_wait <= 0;
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alu_wait_2 <= 0;
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if (launch_next_insn) begin
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dbg_rs1val <= 'bx;
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dbg_rs2val <= 'bx;
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@ -1206,10 +1199,7 @@ module picorv32 #(
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cpu_state <= cpu_state_shift;
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end
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default: begin
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if (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu) begin
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alu_wait_2 <= 0; // AAAA
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alu_wait <= 1;
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end else mem_do_rinst <= mem_do_prefetch;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end
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endcase
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@ -1251,10 +1241,7 @@ module picorv32 #(
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cpu_state <= cpu_state_shift;
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end
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default: begin
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if ((TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
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alu_wait_2 <= 0; // AAAA
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alu_wait <= 1;
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end else mem_do_rinst <= mem_do_prefetch;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end
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endcase
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@ -1262,15 +1249,12 @@ module picorv32 #(
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cpu_state_exec: begin
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reg_out <= reg_pc + decoded_imm;
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if (TWO_CYCLE_COMPARE && (alu_wait || alu_wait_2)) begin
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mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
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alu_wait <= alu_wait_2;
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end else if (is_beq_bne_blt_bge_bltu_bgeu) begin
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if (is_beq_bne_blt_bge_bltu_bgeu) begin
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latched_rd <= 0;
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latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
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latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
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latched_store <= alu_out_0;
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latched_branch <= alu_out_0;
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if (mem_done) cpu_state <= cpu_state_fetch;
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if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
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if (alu_out_0) begin
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decoder_trigger <= 0;
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set_mem_do_rinst = 1;
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end
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