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Remove some trailing whitespace

This commit is contained in:
Larry Doolittle 2017-06-07 08:05:19 -07:00 committed by Clifford Wolf
parent 45b80f985a
commit c9de8001fe
9 changed files with 11 additions and 11 deletions
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2
dhrystone/syscalls.c
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@ -62,7 +62,7 @@ ssize_t write(int file, const void *ptr, size_t len)
return len; return len;
} }
int close(int file) int close(int file)
{ {
// close is called before _exit() // close is called before _exit()
return 0; return 0;

2
picorv32.v
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@ -654,7 +654,7 @@ module picorv32 #(
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};

2
scripts/csmith/syscalls.c
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@ -62,7 +62,7 @@ ssize_t write(int file, const void *ptr, size_t len)
return len; return len;
} }
int close(int file) int close(int file)
{ {
// close is called before _exit() // close is called before _exit()
return 0; return 0;

2
scripts/cxxdemo/syscalls.c
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@ -62,7 +62,7 @@ ssize_t write(int file, const void *ptr, size_t len)
return len; return len;
} }
int close(int file) int close(int file)
{ {
// close is called before _exit() // close is called before _exit()
return 0; return 0;

4
scripts/quartus/tabtest.sh
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@ -37,7 +37,7 @@ set_global_assignment -name SDC_FILE test_${1}.sdc
EOT EOT
echo "Running tab_${ip}_${dev}_${grade}/test_${1}.." echo "Running tab_${ip}_${dev}_${grade}/test_${1}.."
if ! $QUARTUS_BIN/quartus_map test_${1}; then if ! $QUARTUS_BIN/quartus_map test_${1}; then
exit 1 exit 1
fi fi
@ -47,7 +47,7 @@ set_global_assignment -name SDC_FILE test_${1}.sdc
if ! $QUARTUS_BIN/quartus_sta test_${1} -c test_${1}; then if ! $QUARTUS_BIN/quartus_sta test_${1} -c test_${1}; then
exit 1 exit 1
fi fi
cp output_files/test_${1}.sta.summary test_${1}.txt cp output_files/test_${1}.sta.summary test_${1}.txt
} }

2
scripts/smtbmc/opcode.v
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@ -86,7 +86,7 @@ function opcode_sys;
if (opcode[31:20] == 12'hC81 && opcode[19:12] == 3'b010 && opcode[6:0] == 7'b1110011) opcode_sys = 1; // RDTIMEH if (opcode[31:20] == 12'hC81 && opcode[19:12] == 3'b010 && opcode[6:0] == 7'b1110011) opcode_sys = 1; // RDTIMEH
if (opcode[31:20] == 12'hC82 && opcode[19:12] == 3'b010 && opcode[6:0] == 7'b1110011) opcode_sys = 1; // RDINSTRETH if (opcode[31:20] == 12'hC82 && opcode[19:12] == 3'b010 && opcode[6:0] == 7'b1110011) opcode_sys = 1; // RDINSTRETH
end end
endfunction endfunction
function opcode_valid; function opcode_valid;

2
scripts/tomthumbtg/run.sh
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@ -9,7 +9,7 @@ if [ ! -f testgen.tgz ]; then
fi fi
rm -rf tests testgen/ rm -rf tests testgen/
tar xvzf testgen.tgz tar xvzf testgen.tgz
iverilog -o testbench_a -s testbench testbench.v ../../picorv32.v -DTWO_STAGE_SHIFT=0 -DBARREL_SHIFTER=0 -DTWO_CYCLE_COMPARE=0 -DTWO_CYCLE_ALU=0 iverilog -o testbench_a -s testbench testbench.v ../../picorv32.v -DTWO_STAGE_SHIFT=0 -DBARREL_SHIFTER=0 -DTWO_CYCLE_COMPARE=0 -DTWO_CYCLE_ALU=0
iverilog -o testbench_b -s testbench testbench.v ../../picorv32.v -DTWO_STAGE_SHIFT=1 -DBARREL_SHIFTER=0 -DTWO_CYCLE_COMPARE=0 -DTWO_CYCLE_ALU=0 iverilog -o testbench_b -s testbench testbench.v ../../picorv32.v -DTWO_STAGE_SHIFT=1 -DBARREL_SHIFTER=0 -DTWO_CYCLE_COMPARE=0 -DTWO_CYCLE_ALU=0

2
scripts/yosys-cmp/lse.sh
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@ -29,7 +29,7 @@ cat > lse.prj << EOT
-fsm_encoding_style Auto -fsm_encoding_style Auto
-use_io_insertion 1 -use_io_insertion 1
-use_io_reg auto -use_io_reg auto
-ifd -ifd
-resolve_mixed_drivers 0 -resolve_mixed_drivers 0
-RWCheckOnRam 0 -RWCheckOnRam 0
-fix_gated_clocks 1 -fix_gated_clocks 1

4
tests/srli.S
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@ -48,11 +48,11 @@ RVTEST_CODE_BEGIN
TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 ); TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_IMM_ZEROSRC1( 28, srli, 0, 31 ); TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
TEST_IMM_ZERODEST( 29, srli, 33, 20 ); TEST_IMM_ZERODEST( 29, srli, 33, 20 );