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Support mem_la interface in torture test

This commit is contained in:
Clifford Wolf 2016-04-10 13:39:39 +02:00
parent fce9656604
commit df1ae479e3
4 changed files with 60 additions and 16 deletions
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1
scripts/torture/.gitignore vendored
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@ -10,3 +10,4 @@ test.bin
test.hex test.hex
test.ref test.ref
test.vvp test.vvp
test.vcd

2
scripts/torture/Makefile
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@ -82,7 +82,7 @@ loop:
clean: clean:
rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests obj_dir rm -rf riscv-torture riscv-fesvr riscv-isa-sim tests obj_dir
rm -f test.S test.elf test.bin test.hex test.ref test.vvp rm -f test.S test.elf test.bin test.hex test.ref test.vvp test.vcd
.PHONY: test batch loop clean .PHONY: test batch loop clean

2
scripts/torture/test.sh
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@ -24,5 +24,5 @@ python3 ../../firmware/makehex.py test.bin 4096 > test.hex
## Run test ## Run test
iverilog -o test.vvp testbench.v ../../picorv32.v iverilog -o test.vvp testbench.v ../../picorv32.v
vvp test.vvp +hex=test.hex +ref=test.ref vvp test.vvp +vcd +hex=test.hex +ref=test.ref

71
scripts/torture/testbench.v
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@ -18,19 +18,45 @@ module testbench (
wire [3:0] mem_wstrb; wire [3:0] mem_wstrb;
reg [31:0] mem_rdata; reg [31:0] mem_rdata;
wire mem_la_read;
wire mem_la_write;
wire [31:0] mem_la_addr;
wire [31:0] mem_la_wdata;
wire [3:0] mem_la_wstrb;
reg [31:0] x32 = 314159265;
reg [31:0] next_x32;
always @(posedge clk) begin
if (resetn) begin
next_x32 = x32;
next_x32 = next_x32 ^ (next_x32 << 13);
next_x32 = next_x32 ^ (next_x32 >> 17);
next_x32 = next_x32 ^ (next_x32 << 5);
x32 <= next_x32;
end
end
picorv32 #( picorv32 #(
.COMPRESSED_ISA(1) .COMPRESSED_ISA(1)
) uut ( ) uut (
.clk (clk ), .clk (clk ),
.resetn (resetn ), .resetn (resetn ),
.trap (trap ), .trap (trap ),
.mem_valid (mem_valid ), .mem_valid (mem_valid ),
.mem_instr (mem_instr ), .mem_instr (mem_instr ),
.mem_ready (mem_ready ), .mem_ready (mem_ready ),
.mem_addr (mem_addr ), .mem_addr (mem_addr ),
.mem_wdata (mem_wdata ), .mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ), .mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ) .mem_rdata (mem_rdata ),
.mem_la_read (mem_la_read ),
.mem_la_write(mem_la_write),
.mem_la_addr (mem_la_addr ),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb)
); );
localparam integer filename_len = 18; localparam integer filename_len = 18;
@ -45,8 +71,12 @@ module testbench (
initial begin initial begin
if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory); if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory);
if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref); if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref);
// $dumpfile("testbench.vcd"); `ifndef VERILATOR
// $dumpvars(0, testbench); if ($test$plusargs("vcd")) begin
$dumpfile("test.vcd");
$dumpvars(0, testbench);
end
`endif
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -54,15 +84,28 @@ module testbench (
mem_rdata <= 'bx; mem_rdata <= 'bx;
if (!trap || !resetn) begin if (!trap || !resetn) begin
if (mem_valid && !mem_ready && resetn) begin if (x32[0] && resetn) begin
mem_ready <= 1; if (mem_la_read) begin
if (mem_wstrb) begin mem_ready <= 1;
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; mem_rdata <= memory[mem_la_addr >> 2];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; end else
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; if (mem_la_write) begin
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; mem_ready <= 1;
end else begin if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
mem_rdata <= memory[mem_addr >> 2]; if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
end else
if (mem_valid && !mem_ready) begin
mem_ready <= 1;
if (mem_wstrb) begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end else begin
mem_rdata <= memory[mem_addr >> 2];
end
end end
end end
end else begin end else begin
@ -74,9 +117,9 @@ module testbench (
end end
end end
if (errcount) if (errcount)
$display("FAILED: Got %1d errors for %s => %s!", errcount, hex_filename, ref_filename); $display("FAILED: Got %1d errors for %1s => %1s!", errcount, hex_filename, ref_filename);
else else
$display("PASSED %s => %s.", hex_filename, ref_filename); $display("PASSED %1s => %1s.", hex_filename, ref_filename);
$finish; $finish;
end end