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588 Commits

Author SHA1 Message Date
matt venn fe1867817d fix ifdef to include flash functions for hx8k 2018-08-30 22:27:18 +02:00
Clifford Wolf e9c5831097 Fix chown call in Makefile (for building tools) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-26 18:23:55 +02:00
Clifford Wolf 2d6d5c055b More PicoSoC firmware improvements for icebreaker 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 14:39:20 +02:00
Clifford Wolf 68c69136b9 Add icebreaker example PicoSoC implementation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 13:38:59 +02:00
Clifford Wolf 1afe3af452 Add PicoSoC IceBreaker demo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 20:17:21 +02:00
Clifford Wolf b634224ccb
Merge pull request #79 from olofk/irqconfig 
Expose ENABLE_IRQ_QREGS and PROGADDR_IRQ from picosoc.v
 2018-08-18 19:32:35 +02:00
Olof Kindgren 75aa1055f8 Expose ENABLE_IRQ_QREGS and PROGADDR_IRQ from picosoc.v 2018-08-16 22:06:26 +02:00
Clifford Wolf 7c256656c2 PicoSoC: Use RDSR1+RDCR1+WRR instead of RDAR+WRAR 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 14:09:12 +02:00
Clifford Wolf 89c2761f57 Update riscv-gnu-toolchain 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 20:54:30 +02:00
Clifford Wolf 4c1e0f47a6 Add rs232 decode to picosoc hx8kdemo test bench 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 14:27:09 +02:00
Clifford Wolf 28d6f97b00 Fix picosoc quad spi mode (flashio_worker must be multiple of 4 bytes) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 14:26:49 +02:00
Clifford Wolf b3f292a988 Improve picosoc demo firmware, picosoc firmware build fixes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 13:49:08 +02:00
Clifford Wolf ce9d92939a
Merge pull request #61 from mmicko/linker-script 
Created lds file (section mapping) and init for data and bss sections
 2018-08-14 13:05:56 +02:00
Clifford Wolf 2a0cff8672
Merge pull request #74 from olofk/picosoc-fusesoc_v2 
Picosoc fusesoc v2
 2018-08-14 13:04:03 +02:00
Olof Kindgren 12274e9f8a Add FuseSoC .core file for hx8kdemo 
The core file specifies targets for FPGA implementation (fusesoc
build hx8kdemo) and simulation (fusesoc run --tool=<tool>
--target=sim hx8kdemo --firmware=path/to/firmware.he).

Simulation has been tested successfully with icarus, modelsim and xsim
 2018-07-27 23:23:41 +02:00
Olof Kindgren 80f128713d Add FuseSoC .core file for picosoc 
This allows other cores to depend on the generic parts of picosoc
and use that as a base design.
 2018-07-27 23:23:41 +02:00
Olof Kindgren 262da6444c Add FuseSoC .core file for SPI Flash model 
This allows other cores to depend on spiflash. Can also be used to
run the spiflash testbench with

fusesoc run --tool=<tool> spiflash --firmware=path/to/firmware.hex

This has been tested with icarus, modelsim and xsim. Fails with isim
If --tool is left out, icarus will be used as default
 2018-07-26 23:26:43 +02:00
Clifford Wolf 9b6ea045f9 Update riscv-gnu-toolchain to cb6b34b 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 22:35:22 +02:00
Clifford Wolf 4fed27fc16 Fix showtrace.py for changed objdump output format 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 21:13:14 +02:00
Clifford Wolf 1cc9784d71 Fix "make testbench_verilator" bug 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 21:04:30 +02:00
Clifford Wolf 3f55fb4ccb Improve testbench_verilator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 13:04:49 +02:00
Clifford Wolf 247a19dd58 Add "make test_verilator" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 12:53:21 +02:00
Clifford Wolf 147da6432a
Merge pull request #69 from olofk/picosoc_regs_v3 
Bypass picosoc compile order check if PICORV32_REGS is defined.
 2018-05-19 12:09:52 +02:00
Olof Kindgren 2ceb472178 Bypass picosoc compile order check if PICORV32_REGS is defined. 
Previously, picosoc.v needed to be sourced before picorv32.v to
ensure that the PICORV32_REGS `define (used to select implementation
for the register file) was set to picosoc_regs

This allows for overriding PICORV32_REGS, e.g. by setting it
externally in the EDA tool invocation. In this case, the compile
order between picorv32.v and picosoc.v is not important.

Note: This change will break the safety check if PICORV32_REGS
is defined between sourcing picorv32.v and picosoc.v
 2018-05-18 23:52:31 +02:00
Clifford Wolf 3015c18e53
Merge pull request #66 from olofk/spiflash-plusarg 
spiflash: Allow setting firmware from plusarg
 2018-05-15 11:43:44 +02:00
Olof Kindgren c9470e3e04 spiflash: Allow setting firmware from plusarg 2018-05-15 09:53:33 +02:00
Clifford Wolf ad95e88e11
Merge pull request #63 from olofk/fix-spiflash_tb 
Fix spiflash_tb
 2018-05-12 15:29:16 +02:00
Olof Kindgren d26e505251 Fix spiflash_tb 
Update expected two first Flash words to reflect changes in start.s

Add dummy SPI cycles to account for latency
 2018-05-11 22:56:52 +02:00
Larry Doolittle 8b32bc5bd6 Fix miscellaneous typos in documentation 2018-04-17 17:53:08 +02:00
Miodrag Milanovic 9300a510c5 Created lfs file (section mappint) and init for data and bss sections 2018-04-16 20:04:01 +02:00
Clifford Wolf a1f22a6d9c
Merge pull request #59 from tinyfpga/master 
add .data and .bss segments to picosoc
 2018-04-08 13:36:55 +02:00
Luke Valenty a0d5f8efd7
add .data and .bss segments to picosoc 
added .data and .bss segments to picosoc firmware linker script so that static variables may be used.
 2018-04-07 18:42:59 -07:00
Clifford Wolf f52f36762e Update riscv-gnu-toolchain to 1b80cbe 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-03 20:14:17 +02:00
Clifford Wolf f9d4a5dc0c
Merge pull request #56 from olofk/fusesoc 
Verilator testbench and FuseSoC support
 2018-03-05 17:27:21 +01:00
Olof Kindgren 6c5579b490 Add FuseSoC core file 2018-03-04 21:22:03 +01:00
Olof Kindgren 70ea50e60d Add verilator testbench 2018-03-04 21:20:29 +01:00
Clifford Wolf 2ba76e0311
Merge pull request #54 from thoughtpolice/misc-fixes 
Small fixes to the IceStorm scripts
 2018-02-16 12:03:50 +01:00
Austin Seipp 77a6b2dd26 scripts/icestorm: use 'yosys-config' to find data directory 
This fixes the icestorm script to query yosys-config itself for the
right data directory. Not only does this fix installs where yosys was
not installed into /usr/local, it also ensures Icarus picks up a data
directory consistent with the version of yosys that you're using.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2018-02-14 16:54:47 -06:00
Austin Seipp 2260d2ab8a scripts: remove old -m32 argument to riscv-gcc 
See also 55da6c7cd1

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2018-02-14 16:54:47 -06:00
Clifford Wolf a9e0ea54cf
Merge pull request #52 from olofk/testbench_wb_fixes 
Testbench wb fixes
 2017-12-31 14:46:15 +01:00
Olof Kindgren f1949e9bf1 testbench_wb: Add proper attribution for wb_ram module 2017-12-27 20:38:19 +01:00
Olof Kindgren 0495ce8b5a testbench_wb: Load firmware with plusarg instead of parameter 2017-12-27 20:32:33 +01:00
Clifford Wolf df01132185 Update riscv-gnu-toolchain to bf5697a 2017-11-19 01:54:56 +00:00
Clifford Wolf 65f32c38db Fix picosoc hx8kdemo_tb 2017-11-11 19:49:01 +01:00
Clifford Wolf dda7db273d Add missing "volatile" to "asm" statements 2017-10-30 11:22:54 +01:00
Clifford Wolf 31588b871e Update evaluation results to Vivado 2017.3 2017-10-21 02:54:19 +02:00
Clifford Wolf d9d5220071 Update riscv-gnu-toolchain to git rev e9f5458 2017-10-19 17:18:47 +02:00
Clifford Wolf ed69f9e451 Update riscv-formal altops bitmasks 2017-10-07 01:24:59 +02:00
Clifford Wolf 7b6aa21f34 Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS support 2017-10-06 17:33:44 +02:00
Clifford Wolf ad08edd2e5 Add PICORV32_REGS mechanism for ASIC sram instantiation 2017-10-01 15:45:46 +02:00