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609 Commits

Author SHA1 Message Date
Clifford Wolf 77277a0d32 Fix typo, closes #136 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-25 11:28:08 +02:00
Clifford Wolf 3f9b5048bc Fix initialization of "irq" in verilog testbench 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-22 13:59:43 +02:00
Clifford Wolf 881f928e05 Improve showtrace.py (and fix for new binutils) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-21 13:19:15 +02:00
Clifford Wolf 392ee1dd91 Improve test firmware, increase testbench memory size to 128kB 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-12 10:50:45 +02:00
Clifford Wolf 3bb692a954
Merge pull request #131 from tomverbeure/dhry_trace 
Add tracing support to dhrystone test
 2019-08-19 13:12:54 +02:00
Tom Verbeure 6edd0bfe14 Add tracing support to dhrystone test 2019-08-18 08:32:45 -07:00
Clifford Wolf d124abbacd
Update README.md 2019-08-09 09:23:17 +02:00
Clifford Wolf e6779ba52b Disable verilator warnings, fixes #128 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 15:16:06 +02:00
Clifford Wolf d046cbfa49 Add PICORV32_TESTBUG_nnn ifdefs for testing purposes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-30 11:30:18 +02:00
Clifford Wolf 18cd609853 Add rvfi_ixl 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 00:07:16 +02:00
Clifford Wolf e0baf2e0bd Add RVFI CSRs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 00:04:37 +02:00
Clifford Wolf 3d36751b88 Do not peek into core for cycle count in WB testbench 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-03 08:17:08 +02:00
Clifford Wolf f3a42746ca Do not peek into core for cycle count in testbench 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-03 08:14:16 +02:00
Clifford Wolf b7e82dfcd1 Merge branch 'yanghao-master' 2019-04-28 10:32:49 +02:00
Clifford Wolf cf69d4da58 Undo Makefile changes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-28 10:32:23 +02:00
Yanghao Hua d60ffd8eea fix firmware/sections.lds section size alignment on 4 bytes 2019-04-27 12:37:35 +02:00
Clifford Wolf 507f49d086
Merge pull request #117 from Fatsie/wbdoc 
README.md: Also refer to picorv32_wb
 2019-04-17 13:02:49 +02:00
Staf Verhaegen 11d28a0f50 README.md: Also refer to picorv32_wb 2019-03-28 11:08:34 +01:00
Clifford Wolf f48f5fe970 Add Verilator version infos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 14:33:50 +01:00
Clifford Wolf 6d145b708d Rename decoded_imm_uj to decoded_imm_j 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 14:29:27 -08:00
Clifford Wolf 6efa7d1c8b Remove riscv-dejagnu from "make build-tools" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 14:12:07 -08:00
Clifford Wolf 348de8e797 Remove riscv-qemu from "make build-tools" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 14:12:07 -08:00
Clifford Wolf 1d42f5725b
Merge pull request #114 from csquaredphd/master 
fix typo in picosoc/Makefile for hx8k board
 2019-03-02 14:11:59 -08:00
Clifford Wolf 243a09fd8d Add buffer cell to scripts/yosys/synth_gates.lib 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 09:17:56 -08:00
Chris Clark 7ac4102fc4 fix typo in picosoc/Makefile for hx8k board 2019-03-01 19:57:22 -05:00
Clifford Wolf ed1138d6a6 Update riscv-gnu-toolchain to 411d134 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-19 10:47:53 +01:00
Clifford Wolf 5c081c3291
Merge pull request #111 from stv0g/icebreaker-spram 
Use SPRAM on ICE40UP5K based boards
 2019-02-13 14:13:58 +01:00
Clifford Wolf 358dde2376
Merge branch 'master' into icebreaker-spram 2019-02-13 14:13:23 +01:00
Clifford Wolf 0886cc7562
Merge pull request #104 from thoughtpolice/dev 
Various touchups to scripts/icestorm demo
 2019-02-13 14:10:47 +01:00
Clifford Wolf e9e311d53e
Merge pull request #109 from stv0g/cmd-echo 
Added echo command to PicoSoc firmware for testing UART
 2019-02-13 14:07:08 +01:00
Clifford Wolf 6e55b7afbc
Merge pull request #110 from stv0g/add-torture-readme 
Add readme file for torture test
 2019-02-13 14:06:25 +01:00
Steffen Vogel 3710a86b81 icebreaker: artificially limit available RAM to speed-up simulation 2019-02-12 00:13:33 +01:00
Steffen Vogel eb64df6c3e picosoc: use preprocessor for generating target-specific linker script 2019-02-11 23:44:47 +01:00
Steffen Vogel f3b1246c86 picosoc: added memtest 2019-02-11 23:14:56 +01:00
Steffen Vogel d21937bafc picosoc: increase available memory by using SPRAM instead of BRAM for the Icebreaker example 2019-02-11 23:13:05 +01:00
Steffen Vogel 017f537317 add readme file for torture test (closes #93) 2019-02-11 21:39:15 +01:00
Steffen Vogel 672c99b71e added echo command for testing simpleuart 2019-02-11 21:26:45 +01:00
Austin Seipp 1c7f51ed60 scripts/icestorm: check circuit @ 62MHz 
With arachne-pnr this circuit couldn't hit 60MHz, just barely under it.
OTOH, nextpnr hits about ~68 MHz. So let's set it somewhere inbetween to
make sure this is true over time!

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:49:37 -06:00
Austin Seipp af3b1bb75d scripts/icestorm: dedupe calls to yosys-config 
Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:49:18 -06:00
Austin Seipp 770b5bd4c6 scripts/icestorm: add readme 
Notes about how to build proper simulation vs hardware bitstreams.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp 13a9edf122 scripts/icestorm: remove unneeded -lgcc 
This freestanding firmware doesn't need anything from the supporting
toolchain.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp 2944564ba8 scripts/icestorm: move SHIFT_COUNTER_BITS into Makefile 
This makes it easier to build separate bitstreams for simulation targets
vs the real bitstream for hardware, without editing any source code.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp 752790a4d7 scripts/icestorm: comments only 
Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp d711ce527e scripts/icestorm: add 'timing' target 
This dumps a simple IceTime report for the bitstream; we fix the device
package to CT256, corresponding to the HX8K.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp 4900ebb693 scripts/icestorm: force -march=rv32i 
The IceStorm example core doesn't include compressed instructions or the
MULT extension; it is an rv32i core, not rv32i[m|c]. If the given
riscv32 toolchain is not explicitly told to generate rv32i code for the
firmware, it may generate invalid instructions which cause a trap during
simulation or on the hardware itself (although CATCH_ILLINSN is set to
zero in this case, too).

Luckily, any rv32i* toolchain (rv32imc for example) can fit the bill
here -- there's no use of libgcc or anything (which might introduce
illegal instructions generated previously) so just forcing the compiler
to generate the right code works nicely.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp fc71cadda4 scripts/icestorm: switch to nextpnr-ice40 
nextpnr-ice40 gives a better fMAX for this design (by about ~9Mhz for
me: ~59MHz -> ~68MHz) and is The Way Of The Future.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 16:09:07 -06:00
Austin Seipp 070367c88d scripts/icestorm: touch up Makefile a bit 
This touches up the Makefile so that it:

  - uses $@, $< and $^ in more places for brevity and robustness (typo
    guards, etc)
  - tracks dependencies slightly better (e.g. .pcf file changes weren't
    tracked before)

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 15:59:56 -06:00
Austin Seipp 42b7477ba7 Add shell.nix for Nix-based PicoRV32 development 
The net result of this is that cd'ing into the main source directory and
running:

    $ nix-shell

will get you every tool needed to immediately do RISC-V development with
picorv32 or picosoc (assuming you're targeting ICE40 or ECP5).

The shell.nix file contains many comments on how to use the resulting
environment.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 15:58:31 -06:00
Austin Seipp 9bf2fcb410 gitignore: update to ignore verilator artifacts 
Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2019-01-11 13:10:43 -06:00
Clifford Wolf 9b70921103
Merge pull request #102 from emilio93/patch-2 
Update vivado scripts
 2018-11-09 13:03:48 +01:00