colin.liang
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e345620054
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Add dhry.hex build in the top makefile.
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2023-01-13 15:32:58 +08:00 |
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colin.liang
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2cf0e04e02
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Add disasmmably.
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2023-01-13 15:10:40 +08:00 |
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colin.liang
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c676992a07
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Remove RISCV_FORMAL.
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2023-01-09 13:26:32 +08:00 |
Austin Seipp
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9bf2fcb410
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gitignore: update to ignore verilator artifacts
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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2019-01-11 13:10:43 -06:00 |
Clifford Wolf
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a412d3ea69
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Add "make test_rvf"
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2017-09-13 18:45:57 +02:00 |
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Clifford Wolf
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98ee8098b9
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Add testbench_ez
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2017-07-27 21:36:38 +02:00 |
Antony Pavlov
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a25597532d
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WIP: add WISHBONE testbench
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
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2017-03-14 09:37:05 +03:00 |
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Clifford Wolf
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85d8401c3d
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Renamed testbench_slow_mem to testbench_nola (no look ahead)
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2016-09-04 12:29:09 +02:00 |
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Clifford Wolf
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7094e61af7
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Added tracer support (under construction)
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2016-08-25 14:15:42 +02:00 |
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Clifford Wolf
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6c69b3812e
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Using .vvp instead of .exe for iverilog executables
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2016-05-04 08:57:16 +02:00 |
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Clifford Wolf
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36cdf83b3f
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Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories
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2016-04-09 12:51:50 +02:00 |
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Clifford Wolf
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07f28068f6
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Added "make check"
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2015-10-14 23:26:04 +02:00 |
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Clifford Wolf
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476046c177
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Minor Makefile changes
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2015-07-02 11:01:21 +02:00 |
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Clifford Wolf
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997c5ce341
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Added "make test_synth"
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2015-06-30 01:46:25 +02:00 |
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Clifford Wolf
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44571601c1
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Added "make test_sp"
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2015-06-26 23:54:12 +02:00 |
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Clifford Wolf
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d4331491a8
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Test firmware refactoring
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2015-06-26 23:15:30 +02:00 |
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Clifford Wolf
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23b700cf73
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Added basic IRQ support
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2015-06-25 14:08:39 +02:00 |
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Clifford Wolf
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e84f044bc5
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Major redesign of main FSM
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2015-06-07 11:49:47 +02:00 |
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Clifford Wolf
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9df9d7ff90
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Improved Xilinx example
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2015-06-06 20:14:58 +02:00 |
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Clifford Wolf
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77ba5a1897
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Initial import
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2015-06-06 14:14:32 +02:00 |