1683 lines
97 KiB
Plaintext
1683 lines
97 KiB
Plaintext
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit dbg :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_5 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_6 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_6 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_6 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_7 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_7 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_7 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_8 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_8 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_8 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_9 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_9 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_9 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module dbg :
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input clock : Clock
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input reset : AsyncReset
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output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : AsyncReset, flip clk_override : UInt<1>, flip scan_mode : UInt<1>}
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wire dbg_state : UInt<4>
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dbg_state <= UInt<4>("h00")
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wire dbg_state_en : UInt<1>
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dbg_state_en <= UInt<1>("h00")
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wire sb_state : UInt<4>
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sb_state <= UInt<4>("h00")
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wire sb_state_en : UInt<1>
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sb_state_en <= UInt<1>("h00")
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wire dmcontrol_reg : UInt<32>
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dmcontrol_reg <= UInt<32>("h00")
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wire sbaddress0_reg : UInt<32>
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sbaddress0_reg <= UInt<32>("h00")
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wire sbcs_sbbusy_wren : UInt<1>
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sbcs_sbbusy_wren <= UInt<1>("h00")
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wire sbcs_sberror_wren : UInt<1>
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sbcs_sberror_wren <= UInt<1>("h00")
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wire sb_bus_rdata : UInt<64>
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sb_bus_rdata <= UInt<64>("h00")
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wire sbaddress0_reg_wren1 : UInt<1>
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sbaddress0_reg_wren1 <= UInt<1>("h00")
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wire dmstatus_reg : UInt<32>
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dmstatus_reg <= UInt<32>("h00")
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wire dmstatus_havereset : UInt<1>
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dmstatus_havereset <= UInt<1>("h00")
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wire dmstatus_haveresetn : UInt<1>
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dmstatus_haveresetn <= UInt<1>("h00")
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wire dmstatus_resumeack : UInt<1>
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dmstatus_resumeack <= UInt<1>("h00")
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wire dmstatus_unavail : UInt<1>
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dmstatus_unavail <= UInt<1>("h00")
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wire dmstatus_running : UInt<1>
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dmstatus_running <= UInt<1>("h00")
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wire dmstatus_halted : UInt<1>
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dmstatus_halted <= UInt<1>("h00")
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wire abstractcs_busy_wren : UInt<1>
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abstractcs_busy_wren <= UInt<1>("h00")
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wire abstractcs_busy_din : UInt<1>
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abstractcs_busy_din <= UInt<1>("h00")
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wire sb_bus_cmd_read : UInt<1>
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sb_bus_cmd_read <= UInt<1>("h00")
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wire sb_bus_cmd_write_addr : UInt<1>
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sb_bus_cmd_write_addr <= UInt<1>("h00")
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wire sb_bus_cmd_write_data : UInt<1>
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sb_bus_cmd_write_data <= UInt<1>("h00")
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wire sb_bus_rsp_read : UInt<1>
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sb_bus_rsp_read <= UInt<1>("h00")
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wire sb_bus_rsp_error : UInt<1>
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sb_bus_rsp_error <= UInt<1>("h00")
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wire sb_bus_rsp_write : UInt<1>
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sb_bus_rsp_write <= UInt<1>("h00")
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wire sbcs_sbbusy_din : UInt<1>
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sbcs_sbbusy_din <= UInt<1>("h00")
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wire sbcs_sberror_din : UInt<3>
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sbcs_sberror_din <= UInt<3>("h00")
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wire abmem_addr : UInt<32>
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abmem_addr <= UInt<32>("h00")
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wire sbcs_reg : UInt<32>
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sbcs_reg <= UInt<32>("h00")
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wire execute_command : UInt<1>
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execute_command <= UInt<1>("h00")
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wire command_reg : UInt<32>
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command_reg <= UInt<32>("h00")
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wire dbg_sb_bus_error : UInt<1>
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dbg_sb_bus_error <= UInt<1>("h00")
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wire command_wren : UInt<1>
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||
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|
command_wren <= UInt<1>("h00")
|
||
|
|
wire command_din : UInt<32>
|
||
|
|
command_din <= UInt<32>("h00")
|
||
|
|
wire dbg_cmd_next_addr : UInt<32>
|
||
|
|
dbg_cmd_next_addr <= UInt<32>("h00")
|
||
|
|
wire data0_reg_wren2 : UInt<1>
|
||
|
|
data0_reg_wren2 <= UInt<1>("h00")
|
||
|
|
wire sb_abmem_cmd_done_in : UInt<1>
|
||
|
|
sb_abmem_cmd_done_in <= UInt<1>("h00")
|
||
|
|
wire sb_abmem_data_done_in : UInt<1>
|
||
|
|
sb_abmem_data_done_in <= UInt<1>("h00")
|
||
|
|
wire sb_abmem_cmd_done_en : UInt<1>
|
||
|
|
sb_abmem_cmd_done_en <= UInt<1>("h00")
|
||
|
|
wire sb_abmem_data_done_en : UInt<1>
|
||
|
|
sb_abmem_data_done_en <= UInt<1>("h00")
|
||
|
|
wire abmem_addr_external : UInt<1>
|
||
|
|
abmem_addr_external <= UInt<1>("h00")
|
||
|
|
wire sb_cmd_pending : UInt<1>
|
||
|
|
sb_cmd_pending <= UInt<1>("h00")
|
||
|
|
wire sb_abmem_cmd_write : UInt<1>
|
||
|
|
sb_abmem_cmd_write <= UInt<1>("h00")
|
||
|
|
wire abmem_addr_in_dccm_region : UInt<1>
|
||
|
|
abmem_addr_in_dccm_region <= UInt<1>("h00")
|
||
|
|
wire abmem_addr_in_iccm_region : UInt<1>
|
||
|
|
abmem_addr_in_iccm_region <= UInt<1>("h00")
|
||
|
|
wire abmem_addr_in_pic_region : UInt<1>
|
||
|
|
abmem_addr_in_pic_region <= UInt<1>("h00")
|
||
|
|
wire sb_abmem_cmd_size : UInt<4>
|
||
|
|
sb_abmem_cmd_size <= UInt<4>("h00")
|
||
|
|
wire abstractcs_error_din : UInt<3>
|
||
|
|
abstractcs_error_din <= UInt<3>("h00")
|
||
|
|
wire dmcontrol_wren_Q : UInt<1>
|
||
|
|
dmcontrol_wren_Q <= UInt<1>("h00")
|
||
|
|
wire abstractcs_reg : UInt<32>
|
||
|
|
abstractcs_reg <= UInt<32>("h02")
|
||
|
|
node _T = or(io.dmi_reg_en, execute_command) @[dbg.scala 114:39]
|
||
|
|
node _T_1 = neq(dbg_state, UInt<4>("h00")) @[dbg.scala 114:70]
|
||
|
|
node _T_2 = or(_T, _T_1) @[dbg.scala 114:57]
|
||
|
|
node _T_3 = or(_T_2, dbg_state_en) @[dbg.scala 114:88]
|
||
|
|
node _T_4 = or(_T_3, io.dec_tlu_dbg_halted) @[dbg.scala 114:103]
|
||
|
|
node _T_5 = or(_T_4, io.dec_tlu_mpc_halted_only) @[dbg.scala 114:127]
|
||
|
|
node _T_6 = or(_T_5, io.dec_tlu_debug_mode) @[dbg.scala 115:32]
|
||
|
|
node _T_7 = or(_T_6, io.dbg_halt_req) @[dbg.scala 115:56]
|
||
|
|
node dbg_free_clken = or(_T_7, io.clk_override) @[dbg.scala 115:74]
|
||
|
|
node _T_8 = or(io.dmi_reg_en, execute_command) @[dbg.scala 116:39]
|
||
|
|
node _T_9 = or(_T_8, sb_state_en) @[dbg.scala 116:57]
|
||
|
|
node _T_10 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 116:83]
|
||
|
|
node _T_11 = or(_T_9, _T_10) @[dbg.scala 116:71]
|
||
|
|
node sb_free_clken = or(_T_11, io.clk_override) @[dbg.scala 116:106]
|
||
|
|
inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
|
||
|
|
rvclkhdr.clock <= clock
|
||
|
|
rvclkhdr.reset <= reset
|
||
|
|
rvclkhdr.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr.io.en <= dbg_free_clken @[lib.scala 345:16]
|
||
|
|
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23]
|
||
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22]
|
||
|
|
rvclkhdr_1.clock <= clock
|
||
|
|
rvclkhdr_1.reset <= reset
|
||
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
|
||
|
|
rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 345:16]
|
||
|
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23]
|
||
|
|
node _T_12 = asUInt(io.dbg_rst_l) @[dbg.scala 121:51]
|
||
|
|
node _T_13 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 121:70]
|
||
|
|
node _T_14 = or(_T_13, io.scan_mode) @[dbg.scala 121:74]
|
||
|
|
node _T_15 = and(_T_12, _T_14) @[dbg.scala 121:54]
|
||
|
|
node dbg_dm_rst_l = asAsyncReset(_T_15) @[dbg.scala 121:103]
|
||
|
|
node _T_16 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 122:46]
|
||
|
|
node _T_17 = eq(_T_16, UInt<1>("h00")) @[dbg.scala 122:32]
|
||
|
|
node _T_18 = bits(_T_17, 0, 0) @[dbg.scala 122:57]
|
||
|
|
node _T_19 = or(_T_18, io.scan_mode) @[dbg.scala 122:60]
|
||
|
|
io.dbg_core_rst_l <= _T_19 @[dbg.scala 122:28]
|
||
|
|
node _T_20 = eq(io.dmi_reg_addr, UInt<7>("h038")) @[dbg.scala 123:48]
|
||
|
|
node _T_21 = and(_T_20, io.dmi_reg_en) @[dbg.scala 123:66]
|
||
|
|
node _T_22 = and(_T_21, io.dmi_reg_wr_en) @[dbg.scala 123:82]
|
||
|
|
node _T_23 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 123:113]
|
||
|
|
node sbcs_wren = and(_T_22, _T_23) @[dbg.scala 123:101]
|
||
|
|
node _T_24 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 124:60]
|
||
|
|
node _T_25 = and(sbcs_wren, _T_24) @[dbg.scala 124:42]
|
||
|
|
node _T_26 = bits(sbcs_reg, 21, 21) @[dbg.scala 124:77]
|
||
|
|
node _T_27 = and(_T_26, io.dmi_reg_en) @[dbg.scala 124:82]
|
||
|
|
node _T_28 = eq(io.dmi_reg_addr, UInt<7>("h039")) @[dbg.scala 125:22]
|
||
|
|
node _T_29 = and(io.dmi_reg_wr_en, _T_28) @[dbg.scala 124:119]
|
||
|
|
node _T_30 = eq(io.dmi_reg_addr, UInt<7>("h03c")) @[dbg.scala 125:60]
|
||
|
|
node _T_31 = or(_T_29, _T_30) @[dbg.scala 125:41]
|
||
|
|
node _T_32 = eq(io.dmi_reg_addr, UInt<7>("h03d")) @[dbg.scala 126:22]
|
||
|
|
node _T_33 = or(_T_31, _T_32) @[dbg.scala 125:78]
|
||
|
|
node _T_34 = and(_T_27, _T_33) @[dbg.scala 124:98]
|
||
|
|
node sbcs_sbbusyerror_wren = or(_T_25, _T_34) @[dbg.scala 124:66]
|
||
|
|
node _T_35 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 128:62]
|
||
|
|
node _T_36 = and(sbcs_wren, _T_35) @[dbg.scala 128:44]
|
||
|
|
node sbcs_sbbusyerror_din = not(_T_36) @[dbg.scala 128:32]
|
||
|
|
reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbcs_sbbusyerror_wren : @[Reg.scala 28:19]
|
||
|
|
temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbcs_sbbusy_wren : @[Reg.scala 28:19]
|
||
|
|
temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_37 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 134:31]
|
||
|
|
reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbcs_wren : @[Reg.scala 28:19]
|
||
|
|
temp_sbcs_20 <= _T_37 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_38 = bits(io.dmi_reg_wdata, 19, 19) @[dbg.scala 136:35]
|
||
|
|
node _T_39 = bits(io.dmi_reg_wdata, 18, 18) @[dbg.scala 136:58]
|
||
|
|
node _T_40 = not(_T_39) @[dbg.scala 136:41]
|
||
|
|
node _T_41 = bits(io.dmi_reg_wdata, 17, 15) @[dbg.scala 136:80]
|
||
|
|
node _T_42 = cat(_T_38, _T_40) @[Cat.scala 29:58]
|
||
|
|
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
|
||
|
|
reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbcs_wren : @[Reg.scala 28:19]
|
||
|
|
temp_sbcs_19_15 <= _T_43 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_44 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 138:31]
|
||
|
|
reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbcs_sberror_wren : @[Reg.scala 28:19]
|
||
|
|
temp_sbcs_14_12 <= _T_44 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_45 = bits(temp_sbcs_19_15, 4, 4) @[dbg.scala 140:96]
|
||
|
|
node _T_46 = bits(temp_sbcs_19_15, 3, 3) @[dbg.scala 140:117]
|
||
|
|
node _T_47 = not(_T_46) @[dbg.scala 140:101]
|
||
|
|
node _T_48 = bits(temp_sbcs_19_15, 2, 0) @[dbg.scala 141:20]
|
||
|
|
node _T_49 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58]
|
||
|
|
node _T_50 = cat(_T_47, _T_48) @[Cat.scala 29:58]
|
||
|
|
node _T_51 = cat(_T_50, temp_sbcs_14_12) @[Cat.scala 29:58]
|
||
|
|
node _T_52 = cat(_T_51, _T_49) @[Cat.scala 29:58]
|
||
|
|
node _T_53 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58]
|
||
|
|
node _T_54 = cat(_T_53, _T_45) @[Cat.scala 29:58]
|
||
|
|
node _T_55 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_56 = cat(_T_55, temp_sbcs_22) @[Cat.scala 29:58]
|
||
|
|
node _T_57 = cat(_T_56, _T_54) @[Cat.scala 29:58]
|
||
|
|
node _T_58 = cat(_T_57, _T_52) @[Cat.scala 29:58]
|
||
|
|
sbcs_reg <= _T_58 @[dbg.scala 140:12]
|
||
|
|
node _T_59 = bits(sbcs_reg, 19, 17) @[dbg.scala 143:33]
|
||
|
|
node _T_60 = eq(_T_59, UInt<3>("h01")) @[dbg.scala 143:42]
|
||
|
|
node _T_61 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 143:72]
|
||
|
|
node _T_62 = and(_T_60, _T_61) @[dbg.scala 143:56]
|
||
|
|
node _T_63 = bits(sbcs_reg, 19, 17) @[dbg.scala 144:14]
|
||
|
|
node _T_64 = eq(_T_63, UInt<3>("h02")) @[dbg.scala 144:23]
|
||
|
|
node _T_65 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 144:53]
|
||
|
|
node _T_66 = orr(_T_65) @[dbg.scala 144:60]
|
||
|
|
node _T_67 = and(_T_64, _T_66) @[dbg.scala 144:37]
|
||
|
|
node _T_68 = or(_T_62, _T_67) @[dbg.scala 143:76]
|
||
|
|
node _T_69 = bits(sbcs_reg, 19, 17) @[dbg.scala 145:14]
|
||
|
|
node _T_70 = eq(_T_69, UInt<3>("h03")) @[dbg.scala 145:23]
|
||
|
|
node _T_71 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 145:53]
|
||
|
|
node _T_72 = orr(_T_71) @[dbg.scala 145:60]
|
||
|
|
node _T_73 = and(_T_70, _T_72) @[dbg.scala 145:37]
|
||
|
|
node sbcs_unaligned = or(_T_68, _T_73) @[dbg.scala 144:64]
|
||
|
|
node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 147:35]
|
||
|
|
node _T_74 = bits(sbcs_reg, 19, 17) @[dbg.scala 148:44]
|
||
|
|
node _T_75 = eq(_T_74, UInt<3>("h00")) @[dbg.scala 148:53]
|
||
|
|
node _T_76 = bits(_T_75, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_77 = mux(_T_76, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_78 = and(_T_77, UInt<4>("h01")) @[dbg.scala 148:68]
|
||
|
|
node _T_79 = bits(sbcs_reg, 19, 17) @[dbg.scala 148:98]
|
||
|
|
node _T_80 = eq(_T_79, UInt<3>("h01")) @[dbg.scala 148:107]
|
||
|
|
node _T_81 = bits(_T_80, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_82 = mux(_T_81, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_83 = and(_T_82, UInt<4>("h02")) @[dbg.scala 148:122]
|
||
|
|
node _T_84 = or(_T_78, _T_83) @[dbg.scala 148:79]
|
||
|
|
node _T_85 = bits(sbcs_reg, 19, 17) @[dbg.scala 149:22]
|
||
|
|
node _T_86 = eq(_T_85, UInt<3>("h02")) @[dbg.scala 149:31]
|
||
|
|
node _T_87 = bits(_T_86, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_88 = mux(_T_87, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_89 = and(_T_88, UInt<4>("h04")) @[dbg.scala 149:46]
|
||
|
|
node _T_90 = or(_T_84, _T_89) @[dbg.scala 148:133]
|
||
|
|
node _T_91 = bits(sbcs_reg, 19, 17) @[dbg.scala 149:76]
|
||
|
|
node _T_92 = eq(_T_91, UInt<3>("h03")) @[dbg.scala 149:85]
|
||
|
|
node _T_93 = bits(_T_92, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_94 = mux(_T_93, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_95 = and(_T_94, UInt<4>("h08")) @[dbg.scala 149:100]
|
||
|
|
node sbaddress0_incr = or(_T_90, _T_95) @[dbg.scala 149:57]
|
||
|
|
node _T_96 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 151:41]
|
||
|
|
node _T_97 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 151:79]
|
||
|
|
node sbdata0_reg_wren0 = and(_T_96, _T_97) @[dbg.scala 151:60]
|
||
|
|
node _T_98 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 152:37]
|
||
|
|
node _T_99 = and(_T_98, sb_state_en) @[dbg.scala 152:60]
|
||
|
|
node _T_100 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 152:76]
|
||
|
|
node sbdata0_reg_wren1 = and(_T_99, _T_100) @[dbg.scala 152:74]
|
||
|
|
node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 153:45]
|
||
|
|
node _T_101 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 154:41]
|
||
|
|
node _T_102 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 154:79]
|
||
|
|
node sbdata1_reg_wren0 = and(_T_101, _T_102) @[dbg.scala 154:60]
|
||
|
|
node _T_103 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 155:37]
|
||
|
|
node _T_104 = and(_T_103, sb_state_en) @[dbg.scala 155:60]
|
||
|
|
node _T_105 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 155:76]
|
||
|
|
node sbdata1_reg_wren1 = and(_T_104, _T_105) @[dbg.scala 155:74]
|
||
|
|
node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 156:45]
|
||
|
|
node _T_106 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_107 = mux(_T_106, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_108 = and(_T_107, io.dmi_reg_wdata) @[dbg.scala 157:55]
|
||
|
|
node _T_109 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_111 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 157:118]
|
||
|
|
node _T_112 = and(_T_110, _T_111) @[dbg.scala 157:104]
|
||
|
|
node sbdata0_din = or(_T_108, _T_112) @[dbg.scala 157:74]
|
||
|
|
node _T_113 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_114 = mux(_T_113, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_115 = and(_T_114, io.dmi_reg_wdata) @[dbg.scala 158:55]
|
||
|
|
node _T_116 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_117 = mux(_T_116, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_118 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 158:118]
|
||
|
|
node _T_119 = and(_T_117, _T_118) @[dbg.scala 158:104]
|
||
|
|
node sbdata1_din = or(_T_115, _T_119) @[dbg.scala 158:74]
|
||
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_2.clock <= clock
|
||
|
|
rvclkhdr_2.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg sbdata0_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbdata0_reg_wren : @[Reg.scala 28:19]
|
||
|
|
sbdata0_reg <= sbdata0_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_3.clock <= clock
|
||
|
|
rvclkhdr_3.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg sbdata1_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbdata1_reg_wren : @[Reg.scala 28:19]
|
||
|
|
sbdata1_reg <= sbdata1_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_120 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:45]
|
||
|
|
node _T_121 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:83]
|
||
|
|
node sbaddress0_reg_wren0 = and(_T_120, _T_121) @[dbg.scala 163:64]
|
||
|
|
node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 164:52]
|
||
|
|
node _T_122 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_123 = mux(_T_122, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_124 = and(_T_123, io.dmi_reg_wdata) @[dbg.scala 165:62]
|
||
|
|
node _T_125 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_127 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
|
||
|
|
node _T_128 = add(sbaddress0_reg, _T_127) @[dbg.scala 166:54]
|
||
|
|
node _T_129 = tail(_T_128, 1) @[dbg.scala 166:54]
|
||
|
|
node _T_130 = and(_T_126, _T_129) @[dbg.scala 166:36]
|
||
|
|
node sbaddress0_reg_din = or(_T_124, _T_130) @[dbg.scala 165:81]
|
||
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_4.clock <= clock
|
||
|
|
rvclkhdr_4.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg _T_131 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sbaddress0_reg_wren : @[Reg.scala 28:19]
|
||
|
|
_T_131 <= sbaddress0_reg_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
sbaddress0_reg <= _T_131 @[dbg.scala 168:18]
|
||
|
|
node _T_132 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 170:43]
|
||
|
|
node _T_133 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 170:81]
|
||
|
|
node _T_134 = and(_T_132, _T_133) @[dbg.scala 170:62]
|
||
|
|
node _T_135 = bits(sbcs_reg, 20, 20) @[dbg.scala 170:104]
|
||
|
|
node sbreadonaddr_access = and(_T_134, _T_135) @[dbg.scala 170:94]
|
||
|
|
node _T_136 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 171:45]
|
||
|
|
node _T_137 = and(io.dmi_reg_en, _T_136) @[dbg.scala 171:43]
|
||
|
|
node _T_138 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 171:82]
|
||
|
|
node _T_139 = and(_T_137, _T_138) @[dbg.scala 171:63]
|
||
|
|
node _T_140 = bits(sbcs_reg, 15, 15) @[dbg.scala 171:105]
|
||
|
|
node sbreadondata_access = and(_T_139, _T_140) @[dbg.scala 171:95]
|
||
|
|
node _T_141 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 172:43]
|
||
|
|
node _T_142 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 172:81]
|
||
|
|
node sbdata0wr_access = and(_T_141, _T_142) @[dbg.scala 172:62]
|
||
|
|
node _T_143 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 173:46]
|
||
|
|
node _T_144 = and(_T_143, io.dmi_reg_en) @[dbg.scala 173:59]
|
||
|
|
node dmcontrol_wren = and(_T_144, io.dmi_reg_wr_en) @[dbg.scala 173:75]
|
||
|
|
node _T_145 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 174:43]
|
||
|
|
node _T_146 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 174:64]
|
||
|
|
node _T_147 = eq(_T_146, UInt<1>("h00")) @[dbg.scala 174:50]
|
||
|
|
node _T_148 = and(_T_145, _T_147) @[dbg.scala 174:48]
|
||
|
|
node _T_149 = and(_T_148, dmcontrol_wren_Q) @[dbg.scala 174:69]
|
||
|
|
node resumereq = bits(_T_149, 0, 0) @[dbg.scala 174:95]
|
||
|
|
node _T_150 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 177:35]
|
||
|
|
node _T_151 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 177:61]
|
||
|
|
node _T_152 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 177:83]
|
||
|
|
node _T_153 = cat(_T_150, _T_151) @[Cat.scala 29:58]
|
||
|
|
node _T_154 = cat(_T_153, _T_152) @[Cat.scala 29:58]
|
||
|
|
reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
||
|
|
dm_temp <= _T_154 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_155 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 179:31]
|
||
|
|
reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when dmcontrol_wren : @[Reg.scala 28:19]
|
||
|
|
dm_temp_0 <= _T_155 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_156 = bits(dm_temp, 3, 2) @[dbg.scala 180:32]
|
||
|
|
node _T_157 = bits(dm_temp, 1, 1) @[dbg.scala 180:52]
|
||
|
|
node _T_158 = bits(dm_temp, 0, 0) @[dbg.scala 180:75]
|
||
|
|
node _T_159 = cat(UInt<26>("h00"), _T_158) @[Cat.scala 29:58]
|
||
|
|
node _T_160 = cat(_T_159, dm_temp_0) @[Cat.scala 29:58]
|
||
|
|
node _T_161 = cat(_T_156, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_162 = cat(_T_161, _T_157) @[Cat.scala 29:58]
|
||
|
|
node temp = cat(_T_162, _T_160) @[Cat.scala 29:58]
|
||
|
|
dmcontrol_reg <= temp @[dbg.scala 181:18]
|
||
|
|
reg _T_163 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 184:12]
|
||
|
|
_T_163 <= dmcontrol_wren @[dbg.scala 184:12]
|
||
|
|
dmcontrol_wren_Q <= _T_163 @[dbg.scala 183:21]
|
||
|
|
node _T_164 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_165 = mux(_T_164, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_166 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_167 = mux(_T_166, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_168 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_169 = mux(_T_168, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_170 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_172 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_174 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
|
||
|
|
node _T_175 = cat(_T_171, _T_173) @[Cat.scala 29:58]
|
||
|
|
node _T_176 = cat(_T_175, UInt<1>("h01")) @[Cat.scala 29:58]
|
||
|
|
node _T_177 = cat(_T_176, _T_174) @[Cat.scala 29:58]
|
||
|
|
node _T_178 = cat(UInt<2>("h00"), _T_169) @[Cat.scala 29:58]
|
||
|
|
node _T_179 = cat(UInt<12>("h00"), _T_165) @[Cat.scala 29:58]
|
||
|
|
node _T_180 = cat(_T_179, _T_167) @[Cat.scala 29:58]
|
||
|
|
node _T_181 = cat(_T_180, _T_178) @[Cat.scala 29:58]
|
||
|
|
node _T_182 = cat(_T_181, _T_177) @[Cat.scala 29:58]
|
||
|
|
dmstatus_reg <= _T_182 @[dbg.scala 186:16]
|
||
|
|
node _T_183 = eq(dbg_state, UInt<4>("h09")) @[dbg.scala 189:44]
|
||
|
|
node _T_184 = and(_T_183, io.dec_tlu_resume_ack) @[dbg.scala 189:66]
|
||
|
|
node _T_185 = and(dmstatus_resumeack, resumereq) @[dbg.scala 189:111]
|
||
|
|
node _T_186 = and(_T_185, dmstatus_halted) @[dbg.scala 189:123]
|
||
|
|
node dmstatus_resumeack_wren = or(_T_184, _T_186) @[dbg.scala 189:90]
|
||
|
|
node _T_187 = eq(dbg_state, UInt<4>("h09")) @[dbg.scala 190:44]
|
||
|
|
node dmstatus_resumeack_din = and(_T_187, io.dec_tlu_resume_ack) @[dbg.scala 190:66]
|
||
|
|
node _T_188 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 191:51]
|
||
|
|
node _T_189 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 191:82]
|
||
|
|
node _T_190 = and(_T_188, _T_189) @[dbg.scala 191:64]
|
||
|
|
node _T_191 = and(_T_190, io.dmi_reg_en) @[dbg.scala 191:87]
|
||
|
|
node _T_192 = and(_T_191, io.dmi_reg_wr_en) @[dbg.scala 191:103]
|
||
|
|
node _T_193 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 191:137]
|
||
|
|
node dmstatus_haveresetn_wren = and(_T_192, _T_193) @[dbg.scala 191:122]
|
||
|
|
node _T_194 = not(dmstatus_haveresetn) @[dbg.scala 192:26]
|
||
|
|
dmstatus_havereset <= _T_194 @[dbg.scala 192:23]
|
||
|
|
node temp_rst = asUInt(reset) @[dbg.scala 194:35]
|
||
|
|
node _T_195 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 195:37]
|
||
|
|
node _T_196 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 195:43]
|
||
|
|
node _T_197 = or(_T_195, _T_196) @[dbg.scala 195:41]
|
||
|
|
node _T_198 = bits(_T_197, 0, 0) @[dbg.scala 195:62]
|
||
|
|
dmstatus_unavail <= _T_198 @[dbg.scala 195:20]
|
||
|
|
node _T_199 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 196:42]
|
||
|
|
node _T_200 = not(_T_199) @[dbg.scala 196:23]
|
||
|
|
dmstatus_running <= _T_200 @[dbg.scala 196:20]
|
||
|
|
node _T_201 = bits(dmstatus_resumeack_wren, 0, 0) @[dbg.scala 199:74]
|
||
|
|
reg _T_202 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when _T_201 : @[Reg.scala 28:19]
|
||
|
|
_T_202 <= dmstatus_resumeack_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
dmstatus_resumeack <= _T_202 @[dbg.scala 198:22]
|
||
|
|
node _T_203 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 201:37]
|
||
|
|
node _T_204 = and(io.dec_tlu_dbg_halted, _T_203) @[dbg.scala 201:35]
|
||
|
|
reg _T_205 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 201:12]
|
||
|
|
_T_205 <= _T_204 @[dbg.scala 201:12]
|
||
|
|
dmstatus_halted <= _T_205 @[dbg.scala 200:22]
|
||
|
|
reg _T_206 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when dmstatus_haveresetn_wren : @[Reg.scala 28:19]
|
||
|
|
_T_206 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
dmstatus_haveresetn <= _T_206 @[dbg.scala 202:23]
|
||
|
|
node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58]
|
||
|
|
node _T_207 = bits(abstractcs_reg, 12, 12) @[dbg.scala 207:45]
|
||
|
|
node _T_208 = bits(abstractcs_reg, 10, 8) @[dbg.scala 207:68]
|
||
|
|
node _T_209 = orr(_T_208) @[dbg.scala 207:75]
|
||
|
|
node _T_210 = not(_T_209) @[dbg.scala 207:52]
|
||
|
|
node _T_211 = and(_T_207, _T_210) @[dbg.scala 207:50]
|
||
|
|
node _T_212 = and(_T_211, io.dmi_reg_en) @[dbg.scala 207:80]
|
||
|
|
node _T_213 = eq(io.dmi_reg_addr, UInt<7>("h016")) @[dbg.scala 207:137]
|
||
|
|
node _T_214 = eq(io.dmi_reg_addr, UInt<7>("h017")) @[dbg.scala 208:22]
|
||
|
|
node _T_215 = or(_T_213, _T_214) @[dbg.scala 207:155]
|
||
|
|
node _T_216 = and(io.dmi_reg_wr_en, _T_215) @[dbg.scala 207:117]
|
||
|
|
node _T_217 = eq(io.dmi_reg_addr, UInt<7>("h018")) @[dbg.scala 208:60]
|
||
|
|
node _T_218 = or(_T_216, _T_217) @[dbg.scala 208:41]
|
||
|
|
node _T_219 = eq(io.dmi_reg_addr, UInt<7>("h04")) @[dbg.scala 208:98]
|
||
|
|
node _T_220 = or(_T_218, _T_219) @[dbg.scala 208:79]
|
||
|
|
node _T_221 = eq(io.dmi_reg_addr, UInt<7>("h05")) @[dbg.scala 209:22]
|
||
|
|
node _T_222 = or(_T_220, _T_221) @[dbg.scala 208:112]
|
||
|
|
node abstractcs_error_sel0 = and(_T_212, _T_222) @[dbg.scala 207:96]
|
||
|
|
node _T_223 = bits(abstractcs_reg, 10, 8) @[dbg.scala 210:65]
|
||
|
|
node _T_224 = orr(_T_223) @[dbg.scala 210:72]
|
||
|
|
node _T_225 = not(_T_224) @[dbg.scala 210:49]
|
||
|
|
node _T_226 = and(execute_command, _T_225) @[dbg.scala 210:47]
|
||
|
|
node _T_227 = bits(command_reg, 31, 24) @[dbg.scala 211:21]
|
||
|
|
node _T_228 = eq(_T_227, UInt<8>("h00")) @[dbg.scala 211:29]
|
||
|
|
node _T_229 = bits(command_reg, 31, 24) @[dbg.scala 211:57]
|
||
|
|
node _T_230 = eq(_T_229, UInt<8>("h02")) @[dbg.scala 211:65]
|
||
|
|
node _T_231 = or(_T_228, _T_230) @[dbg.scala 211:43]
|
||
|
|
node _T_232 = eq(_T_231, UInt<1>("h00")) @[dbg.scala 211:7]
|
||
|
|
node _T_233 = bits(command_reg, 22, 20) @[dbg.scala 212:21]
|
||
|
|
node _T_234 = eq(_T_233, UInt<3>("h03")) @[dbg.scala 212:29]
|
||
|
|
node _T_235 = bits(command_reg, 22, 22) @[dbg.scala 212:57]
|
||
|
|
node _T_236 = or(_T_234, _T_235) @[dbg.scala 212:43]
|
||
|
|
node _T_237 = bits(command_reg, 31, 24) @[dbg.scala 212:78]
|
||
|
|
node _T_238 = eq(_T_237, UInt<8>("h02")) @[dbg.scala 212:86]
|
||
|
|
node _T_239 = and(_T_236, _T_238) @[dbg.scala 212:64]
|
||
|
|
node _T_240 = or(_T_232, _T_239) @[dbg.scala 211:81]
|
||
|
|
node _T_241 = bits(command_reg, 22, 20) @[dbg.scala 213:20]
|
||
|
|
node _T_242 = neq(_T_241, UInt<3>("h02")) @[dbg.scala 213:28]
|
||
|
|
node _T_243 = bits(command_reg, 31, 24) @[dbg.scala 213:57]
|
||
|
|
node _T_244 = eq(_T_243, UInt<8>("h00")) @[dbg.scala 213:65]
|
||
|
|
node _T_245 = bits(command_reg, 17, 17) @[dbg.scala 213:92]
|
||
|
|
node _T_246 = and(_T_244, _T_245) @[dbg.scala 213:79]
|
||
|
|
node _T_247 = and(_T_242, _T_246) @[dbg.scala 213:42]
|
||
|
|
node _T_248 = or(_T_240, _T_247) @[dbg.scala 212:101]
|
||
|
|
node _T_249 = bits(command_reg, 31, 24) @[dbg.scala 214:20]
|
||
|
|
node _T_250 = eq(_T_249, UInt<8>("h00")) @[dbg.scala 214:28]
|
||
|
|
node _T_251 = bits(command_reg, 18, 18) @[dbg.scala 214:55]
|
||
|
|
node _T_252 = and(_T_250, _T_251) @[dbg.scala 214:42]
|
||
|
|
node _T_253 = or(_T_248, _T_252) @[dbg.scala 213:101]
|
||
|
|
node abstractcs_error_sel1 = and(_T_226, _T_253) @[dbg.scala 210:77]
|
||
|
|
node _T_254 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 215:54]
|
||
|
|
node _T_255 = bits(command_reg, 31, 24) @[dbg.scala 216:36]
|
||
|
|
node _T_256 = eq(_T_255, UInt<8>("h00")) @[dbg.scala 216:44]
|
||
|
|
node _T_257 = and(execute_command, _T_256) @[dbg.scala 216:22]
|
||
|
|
node _T_258 = bits(command_reg, 15, 12) @[dbg.scala 217:21]
|
||
|
|
node _T_259 = eq(_T_258, UInt<4>("h01")) @[dbg.scala 217:29]
|
||
|
|
node _T_260 = bits(command_reg, 11, 5) @[dbg.scala 217:57]
|
||
|
|
node _T_261 = neq(_T_260, UInt<7>("h00")) @[dbg.scala 217:64]
|
||
|
|
node _T_262 = and(_T_259, _T_261) @[dbg.scala 217:43]
|
||
|
|
node _T_263 = bits(command_reg, 15, 13) @[dbg.scala 217:93]
|
||
|
|
node _T_264 = neq(_T_263, UInt<3>("h00")) @[dbg.scala 217:101]
|
||
|
|
node _T_265 = or(_T_262, _T_264) @[dbg.scala 217:79]
|
||
|
|
node _T_266 = and(_T_257, _T_265) @[dbg.scala 216:58]
|
||
|
|
node _T_267 = or(_T_254, _T_266) @[dbg.scala 215:78]
|
||
|
|
node _T_268 = bits(abstractcs_reg, 10, 8) @[dbg.scala 217:136]
|
||
|
|
node _T_269 = orr(_T_268) @[dbg.scala 217:143]
|
||
|
|
node _T_270 = not(_T_269) @[dbg.scala 217:120]
|
||
|
|
node abstractcs_error_sel2 = and(_T_267, _T_270) @[dbg.scala 217:118]
|
||
|
|
node _T_271 = neq(dbg_state, UInt<4>("h02")) @[dbg.scala 218:60]
|
||
|
|
node _T_272 = and(execute_command, _T_271) @[dbg.scala 218:47]
|
||
|
|
node _T_273 = bits(abstractcs_reg, 10, 8) @[dbg.scala 218:98]
|
||
|
|
node _T_274 = orr(_T_273) @[dbg.scala 218:105]
|
||
|
|
node _T_275 = not(_T_274) @[dbg.scala 218:82]
|
||
|
|
node abstractcs_error_sel3 = and(_T_272, _T_275) @[dbg.scala 218:80]
|
||
|
|
node _T_276 = and(dbg_sb_bus_error, io.dbg_bus_clk_en) @[dbg.scala 219:48]
|
||
|
|
node _T_277 = bits(abstractcs_reg, 10, 8) @[dbg.scala 219:86]
|
||
|
|
node _T_278 = orr(_T_277) @[dbg.scala 219:93]
|
||
|
|
node _T_279 = not(_T_278) @[dbg.scala 219:70]
|
||
|
|
node abstractcs_error_sel4 = and(_T_276, _T_279) @[dbg.scala 219:68]
|
||
|
|
node _T_280 = bits(command_reg, 31, 24) @[dbg.scala 220:61]
|
||
|
|
node _T_281 = eq(_T_280, UInt<8>("h02")) @[dbg.scala 220:69]
|
||
|
|
node _T_282 = and(execute_command, _T_281) @[dbg.scala 220:47]
|
||
|
|
node _T_283 = bits(abstractcs_reg, 10, 8) @[dbg.scala 220:101]
|
||
|
|
node _T_284 = orr(_T_283) @[dbg.scala 220:108]
|
||
|
|
node _T_285 = not(_T_284) @[dbg.scala 220:85]
|
||
|
|
node _T_286 = and(_T_282, _T_285) @[dbg.scala 220:83]
|
||
|
|
node _T_287 = bits(command_reg, 22, 20) @[dbg.scala 221:19]
|
||
|
|
node _T_288 = eq(_T_287, UInt<3>("h01")) @[dbg.scala 221:27]
|
||
|
|
node _T_289 = bits(abmem_addr, 0, 0) @[dbg.scala 221:52]
|
||
|
|
node _T_290 = and(_T_288, _T_289) @[dbg.scala 221:41]
|
||
|
|
node _T_291 = bits(command_reg, 22, 20) @[dbg.scala 221:72]
|
||
|
|
node _T_292 = eq(_T_291, UInt<3>("h02")) @[dbg.scala 221:80]
|
||
|
|
node _T_293 = bits(abmem_addr, 1, 0) @[dbg.scala 221:106]
|
||
|
|
node _T_294 = orr(_T_293) @[dbg.scala 221:112]
|
||
|
|
node _T_295 = and(_T_292, _T_294) @[dbg.scala 221:94]
|
||
|
|
node _T_296 = or(_T_290, _T_295) @[dbg.scala 221:57]
|
||
|
|
node abstractcs_error_sel5 = and(_T_286, _T_296) @[dbg.scala 220:113]
|
||
|
|
node _T_297 = eq(io.dmi_reg_addr, UInt<7>("h016")) @[dbg.scala 222:48]
|
||
|
|
node _T_298 = and(_T_297, io.dmi_reg_en) @[dbg.scala 222:67]
|
||
|
|
node abstractcs_error_sel6 = and(_T_298, io.dmi_reg_wr_en) @[dbg.scala 222:83]
|
||
|
|
node _T_299 = bits(abstractcs_reg, 10, 8) @[dbg.scala 224:50]
|
||
|
|
node _T_300 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 231:48]
|
||
|
|
node _T_301 = not(_T_300) @[dbg.scala 231:31]
|
||
|
|
node _T_302 = bits(abstractcs_reg, 10, 8) @[dbg.scala 231:71]
|
||
|
|
node _T_303 = and(_T_301, _T_302) @[dbg.scala 231:55]
|
||
|
|
node _T_304 = mux(abstractcs_error_sel6, _T_303, _T_299) @[Mux.scala 98:16]
|
||
|
|
node _T_305 = mux(abstractcs_error_sel5, UInt<3>("h07"), _T_304) @[Mux.scala 98:16]
|
||
|
|
node _T_306 = mux(abstractcs_error_sel4, UInt<3>("h05"), _T_305) @[Mux.scala 98:16]
|
||
|
|
node _T_307 = mux(abstractcs_error_sel3, UInt<3>("h04"), _T_306) @[Mux.scala 98:16]
|
||
|
|
node _T_308 = mux(abstractcs_error_sel2, UInt<3>("h03"), _T_307) @[Mux.scala 98:16]
|
||
|
|
node _T_309 = mux(abstractcs_error_sel1, UInt<3>("h02"), _T_308) @[Mux.scala 98:16]
|
||
|
|
node _T_310 = mux(abstractcs_error_sel0, UInt<3>("h01"), _T_309) @[Mux.scala 98:16]
|
||
|
|
abstractcs_error_din <= _T_310 @[dbg.scala 224:25]
|
||
|
|
reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when abstractcs_busy_wren : @[Reg.scala 28:19]
|
||
|
|
abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 236:12]
|
||
|
|
abs_temp_10_8 <= abstractcs_error_din @[dbg.scala 236:12]
|
||
|
|
node _T_311 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
|
||
|
|
node _T_312 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
|
||
|
|
node _T_313 = cat(_T_312, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58]
|
||
|
|
abstractcs_reg <= _T_314 @[dbg.scala 238:20]
|
||
|
|
node _T_315 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 240:45]
|
||
|
|
node _T_316 = eq(io.dmi_reg_addr, UInt<7>("h018")) @[dbg.scala 240:83]
|
||
|
|
node _T_317 = and(_T_315, _T_316) @[dbg.scala 240:64]
|
||
|
|
node _T_318 = bits(abstractcs_reg, 12, 12) @[dbg.scala 240:118]
|
||
|
|
node _T_319 = eq(_T_318, UInt<1>("h00")) @[dbg.scala 240:103]
|
||
|
|
node abstractauto_reg_wren = and(_T_317, _T_319) @[dbg.scala 240:101]
|
||
|
|
node _T_320 = bits(io.dmi_reg_wdata, 1, 0) @[dbg.scala 242:31]
|
||
|
|
reg abstractauto_reg : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when abstractauto_reg_wren : @[Reg.scala 28:19]
|
||
|
|
abstractauto_reg <= _T_320 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_321 = bits(abstractcs_reg, 12, 12) @[dbg.scala 244:75]
|
||
|
|
node _T_322 = eq(_T_321, UInt<1>("h00")) @[dbg.scala 244:60]
|
||
|
|
node _T_323 = and(io.dmi_reg_en, _T_322) @[dbg.scala 244:58]
|
||
|
|
node _T_324 = eq(io.dmi_reg_addr, UInt<7>("h04")) @[dbg.scala 244:101]
|
||
|
|
node _T_325 = bits(abstractauto_reg, 0, 0) @[dbg.scala 245:21]
|
||
|
|
node _T_326 = and(_T_324, _T_325) @[dbg.scala 244:115]
|
||
|
|
node _T_327 = eq(io.dmi_reg_addr, UInt<7>("h05")) @[dbg.scala 245:46]
|
||
|
|
node _T_328 = bits(abstractauto_reg, 1, 1) @[dbg.scala 245:78]
|
||
|
|
node _T_329 = and(_T_327, _T_328) @[dbg.scala 245:60]
|
||
|
|
node _T_330 = or(_T_326, _T_329) @[dbg.scala 245:26]
|
||
|
|
node _T_331 = and(_T_323, _T_330) @[dbg.scala 244:80]
|
||
|
|
node execute_command_ns = or(command_wren, _T_331) @[dbg.scala 244:41]
|
||
|
|
node _T_332 = eq(io.dmi_reg_addr, UInt<7>("h017")) @[dbg.scala 246:45]
|
||
|
|
node _T_333 = and(_T_332, io.dmi_reg_en) @[dbg.scala 246:64]
|
||
|
|
node _T_334 = and(_T_333, io.dmi_reg_wr_en) @[dbg.scala 246:80]
|
||
|
|
command_wren <= _T_334 @[dbg.scala 246:25]
|
||
|
|
node _T_335 = bits(command_reg, 31, 24) @[dbg.scala 247:56]
|
||
|
|
node _T_336 = eq(_T_335, UInt<8>("h00")) @[dbg.scala 247:64]
|
||
|
|
node _T_337 = bits(command_reg, 19, 19) @[dbg.scala 247:91]
|
||
|
|
node _T_338 = and(_T_336, _T_337) @[dbg.scala 247:78]
|
||
|
|
node _T_339 = eq(dbg_state, UInt<4>("h08")) @[dbg.scala 247:109]
|
||
|
|
node _T_340 = and(_T_338, _T_339) @[dbg.scala 247:96]
|
||
|
|
node _T_341 = bits(abstractcs_reg, 10, 8) @[dbg.scala 248:21]
|
||
|
|
node _T_342 = orr(_T_341) @[dbg.scala 248:28]
|
||
|
|
node _T_343 = not(_T_342) @[dbg.scala 248:5]
|
||
|
|
node _T_344 = and(_T_340, _T_343) @[dbg.scala 247:131]
|
||
|
|
node command_regno_wren = or(command_wren, _T_344) @[dbg.scala 247:41]
|
||
|
|
node _T_345 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 250:50]
|
||
|
|
node _T_346 = eq(_T_345, UInt<8>("h00")) @[dbg.scala 250:58]
|
||
|
|
node _T_347 = bits(io.dmi_reg_wdata, 18, 18) @[dbg.scala 250:90]
|
||
|
|
node command_postexec_din = and(_T_346, _T_347) @[dbg.scala 250:72]
|
||
|
|
node _T_348 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 251:50]
|
||
|
|
node _T_349 = eq(_T_348, UInt<8>("h00")) @[dbg.scala 251:58]
|
||
|
|
node _T_350 = bits(io.dmi_reg_wdata, 17, 17) @[dbg.scala 251:90]
|
||
|
|
node command_transfer_din = and(_T_349, _T_350) @[dbg.scala 251:72]
|
||
|
|
node _T_351 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 252:53]
|
||
|
|
node _T_352 = bits(io.dmi_reg_wdata, 22, 19) @[dbg.scala 252:83]
|
||
|
|
node _T_353 = bits(io.dmi_reg_wdata, 16, 16) @[dbg.scala 252:152]
|
||
|
|
node _T_354 = cat(command_postexec_din, command_transfer_din) @[Cat.scala 29:58]
|
||
|
|
node _T_355 = cat(_T_354, _T_353) @[Cat.scala 29:58]
|
||
|
|
node _T_356 = cat(_T_351, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_357 = cat(_T_356, _T_352) @[Cat.scala 29:58]
|
||
|
|
node temp_command_din_31_16 = cat(_T_357, _T_355) @[Cat.scala 29:58]
|
||
|
|
node _T_358 = bits(io.dmi_reg_wdata, 15, 0) @[dbg.scala 253:68]
|
||
|
|
node _T_359 = bits(dbg_cmd_next_addr, 15, 0) @[dbg.scala 253:93]
|
||
|
|
node temp_command_din_15_0 = mux(command_wren, _T_358, _T_359) @[dbg.scala 253:37]
|
||
|
|
node _T_360 = cat(temp_command_din_31_16, temp_command_din_15_0) @[Cat.scala 29:58]
|
||
|
|
command_din <= _T_360 @[dbg.scala 255:19]
|
||
|
|
reg _T_361 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 257:12]
|
||
|
|
_T_361 <= execute_command_ns @[dbg.scala 257:12]
|
||
|
|
execute_command <= _T_361 @[dbg.scala 256:19]
|
||
|
|
node _T_362 = bits(command_din, 31, 16) @[dbg.scala 260:23]
|
||
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_5.clock <= clock
|
||
|
|
rvclkhdr_5.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_5.io.en <= command_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg temp_command_reg_31_16 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when command_wren : @[Reg.scala 28:19]
|
||
|
|
temp_command_reg_31_16 <= _T_362 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_363 = bits(command_din, 15, 0) @[dbg.scala 262:23]
|
||
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_6.clock <= clock
|
||
|
|
rvclkhdr_6.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_6.io.en <= command_regno_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg temp_command_reg_15_0 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when command_regno_wren : @[Reg.scala 28:19]
|
||
|
|
temp_command_reg_15_0 <= _T_363 @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_364 = cat(temp_command_reg_31_16, temp_command_reg_15_0) @[Cat.scala 29:58]
|
||
|
|
command_reg <= _T_364 @[dbg.scala 264:15]
|
||
|
|
node _T_365 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 266:39]
|
||
|
|
node _T_366 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 266:77]
|
||
|
|
node _T_367 = and(_T_365, _T_366) @[dbg.scala 266:58]
|
||
|
|
node _T_368 = eq(dbg_state, UInt<4>("h02")) @[dbg.scala 266:102]
|
||
|
|
node _T_369 = and(_T_367, _T_368) @[dbg.scala 266:89]
|
||
|
|
node _T_370 = bits(abstractcs_reg, 12, 12) @[dbg.scala 266:139]
|
||
|
|
node _T_371 = eq(_T_370, UInt<1>("h00")) @[dbg.scala 266:124]
|
||
|
|
node data0_reg_wren0 = and(_T_369, _T_371) @[dbg.scala 266:122]
|
||
|
|
node _T_372 = eq(dbg_state, UInt<4>("h04")) @[dbg.scala 267:59]
|
||
|
|
node _T_373 = and(io.core_dbg_cmd_done, _T_372) @[dbg.scala 267:46]
|
||
|
|
node _T_374 = bits(command_reg, 16, 16) @[dbg.scala 267:100]
|
||
|
|
node _T_375 = eq(_T_374, UInt<1>("h00")) @[dbg.scala 267:88]
|
||
|
|
node data0_reg_wren1 = and(_T_373, _T_375) @[dbg.scala 267:86]
|
||
|
|
node _T_376 = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 268:41]
|
||
|
|
node data0_reg_wren = or(_T_376, data0_reg_wren2) @[dbg.scala 268:59]
|
||
|
|
node _T_377 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_378 = mux(_T_377, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_379 = and(_T_378, io.dmi_reg_wdata) @[dbg.scala 270:45]
|
||
|
|
node _T_380 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_382 = and(_T_381, io.core_dbg_rddata) @[dbg.scala 271:31]
|
||
|
|
node _T_383 = or(_T_379, _T_382) @[dbg.scala 270:64]
|
||
|
|
node _T_384 = bits(data0_reg_wren2, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_385 = mux(_T_384, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_386 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 272:45]
|
||
|
|
node _T_387 = and(_T_385, _T_386) @[dbg.scala 272:31]
|
||
|
|
node data0_din = or(_T_383, _T_387) @[dbg.scala 271:52]
|
||
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_7.clock <= clock
|
||
|
|
rvclkhdr_7.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_7.io.en <= data0_reg_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg data0_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when data0_reg_wren : @[Reg.scala 28:19]
|
||
|
|
data0_reg <= data0_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
node _T_388 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 277:40]
|
||
|
|
node _T_389 = eq(io.dmi_reg_addr, UInt<7>("h05")) @[dbg.scala 277:78]
|
||
|
|
node _T_390 = and(_T_388, _T_389) @[dbg.scala 277:59]
|
||
|
|
node _T_391 = eq(dbg_state, UInt<4>("h02")) @[dbg.scala 277:105]
|
||
|
|
node _T_392 = and(_T_390, _T_391) @[dbg.scala 277:92]
|
||
|
|
node _T_393 = bits(abstractcs_reg, 12, 12) @[dbg.scala 277:143]
|
||
|
|
node _T_394 = eq(_T_393, UInt<1>("h00")) @[dbg.scala 277:128]
|
||
|
|
node data1_reg_wren0 = and(_T_392, _T_394) @[dbg.scala 277:126]
|
||
|
|
node _T_395 = eq(dbg_state, UInt<4>("h08")) @[dbg.scala 278:36]
|
||
|
|
node _T_396 = bits(command_reg, 31, 24) @[dbg.scala 278:72]
|
||
|
|
node _T_397 = eq(_T_396, UInt<8>("h02")) @[dbg.scala 278:80]
|
||
|
|
node _T_398 = and(_T_395, _T_397) @[dbg.scala 278:58]
|
||
|
|
node _T_399 = bits(command_reg, 19, 19) @[dbg.scala 278:107]
|
||
|
|
node _T_400 = and(_T_398, _T_399) @[dbg.scala 278:94]
|
||
|
|
node _T_401 = bits(abstractcs_reg, 10, 8) @[dbg.scala 278:130]
|
||
|
|
node _T_402 = orr(_T_401) @[dbg.scala 278:137]
|
||
|
|
node _T_403 = not(_T_402) @[dbg.scala 278:114]
|
||
|
|
node data1_reg_wren1 = and(_T_400, _T_403) @[dbg.scala 278:112]
|
||
|
|
node data1_reg_wren = or(data1_reg_wren0, data1_reg_wren1) @[dbg.scala 279:41]
|
||
|
|
node _T_404 = bits(data1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_406 = and(_T_405, io.dmi_reg_wdata) @[dbg.scala 281:45]
|
||
|
|
node _T_407 = bits(data1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_408 = mux(_T_407, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_409 = bits(dbg_cmd_next_addr, 31, 0) @[dbg.scala 281:111]
|
||
|
|
node _T_410 = and(_T_408, _T_409) @[dbg.scala 281:92]
|
||
|
|
node data1_din = or(_T_406, _T_410) @[dbg.scala 281:64]
|
||
|
|
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_8.clock <= clock
|
||
|
|
rvclkhdr_8.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_8.io.en <= data1_reg_wren @[lib.scala 412:17]
|
||
|
|
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg _T_411 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when data1_reg_wren : @[Reg.scala 28:19]
|
||
|
|
_T_411 <= data1_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
abmem_addr <= _T_411 @[dbg.scala 282:16]
|
||
|
|
reg sb_abmem_cmd_done : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sb_abmem_cmd_done_en : @[Reg.scala 28:19]
|
||
|
|
sb_abmem_cmd_done <= sb_abmem_cmd_done_in @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
reg sb_abmem_data_done : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sb_abmem_data_done_en : @[Reg.scala 28:19]
|
||
|
|
sb_abmem_data_done <= sb_abmem_data_done_in @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
wire dbg_nxtstate : UInt<4>
|
||
|
|
dbg_nxtstate <= UInt<4>("h00")
|
||
|
|
dbg_nxtstate <= UInt<4>("h00") @[dbg.scala 290:25]
|
||
|
|
dbg_state_en <= UInt<1>("h00") @[dbg.scala 291:25]
|
||
|
|
abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 292:25]
|
||
|
|
abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 293:25]
|
||
|
|
io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 294:25]
|
||
|
|
io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 295:25]
|
||
|
|
dbg_sb_bus_error <= UInt<1>("h00") @[dbg.scala 296:25]
|
||
|
|
data0_reg_wren2 <= UInt<1>("h00") @[dbg.scala 297:25]
|
||
|
|
sb_abmem_cmd_done_in <= UInt<1>("h00") @[dbg.scala 298:25]
|
||
|
|
sb_abmem_data_done_in <= UInt<1>("h00") @[dbg.scala 299:25]
|
||
|
|
sb_abmem_cmd_done_en <= UInt<1>("h00") @[dbg.scala 300:25]
|
||
|
|
sb_abmem_data_done_en <= UInt<1>("h00") @[dbg.scala 301:25]
|
||
|
|
node _T_412 = eq(UInt<4>("h00"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_412 : @[Conditional.scala 40:58]
|
||
|
|
node _T_413 = bits(dmstatus_reg, 9, 9) @[dbg.scala 304:42]
|
||
|
|
node _T_414 = or(_T_413, io.dec_tlu_mpc_halted_only) @[dbg.scala 304:46]
|
||
|
|
node _T_415 = mux(_T_414, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 304:29]
|
||
|
|
dbg_nxtstate <= _T_415 @[dbg.scala 304:23]
|
||
|
|
node _T_416 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:41]
|
||
|
|
node _T_417 = bits(dmstatus_reg, 9, 9) @[dbg.scala 305:60]
|
||
|
|
node _T_418 = or(_T_416, _T_417) @[dbg.scala 305:46]
|
||
|
|
node _T_419 = or(_T_418, io.dec_tlu_mpc_halted_only) @[dbg.scala 305:64]
|
||
|
|
dbg_state_en <= _T_419 @[dbg.scala 305:23]
|
||
|
|
node _T_420 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 306:39]
|
||
|
|
node _T_421 = bits(_T_420, 0, 0) @[dbg.scala 306:50]
|
||
|
|
io.dbg_halt_req <= _T_421 @[dbg.scala 306:23]
|
||
|
|
skip @[Conditional.scala 40:58]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_422 = eq(UInt<4>("h01"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_422 : @[Conditional.scala 39:67]
|
||
|
|
dbg_nxtstate <= UInt<4>("h02") @[dbg.scala 309:23]
|
||
|
|
node _T_423 = bits(dmstatus_reg, 9, 9) @[dbg.scala 310:38]
|
||
|
|
node _T_424 = or(_T_423, io.dec_tlu_mpc_halted_only) @[dbg.scala 310:42]
|
||
|
|
dbg_state_en <= _T_424 @[dbg.scala 310:23]
|
||
|
|
node _T_425 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 311:59]
|
||
|
|
node _T_426 = and(dmcontrol_wren_Q, _T_425) @[dbg.scala 311:44]
|
||
|
|
node _T_427 = bits(_T_426, 0, 0) @[dbg.scala 311:71]
|
||
|
|
io.dbg_halt_req <= _T_427 @[dbg.scala 311:23]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_428 = eq(UInt<4>("h02"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_428 : @[Conditional.scala 39:67]
|
||
|
|
node _T_429 = bits(dmstatus_reg, 9, 9) @[dbg.scala 314:39]
|
||
|
|
node _T_430 = bits(command_reg, 31, 24) @[dbg.scala 314:93]
|
||
|
|
node _T_431 = eq(_T_430, UInt<8>("h02")) @[dbg.scala 314:102]
|
||
|
|
node _T_432 = and(_T_431, abmem_addr_external) @[dbg.scala 314:116]
|
||
|
|
node _T_433 = mux(_T_432, UInt<4>("h05"), UInt<4>("h03")) @[dbg.scala 314:80]
|
||
|
|
node _T_434 = mux(resumereq, UInt<4>("h09"), _T_433) @[dbg.scala 314:47]
|
||
|
|
node _T_435 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 315:74]
|
||
|
|
node _T_436 = mux(_T_435, UInt<4>("h01"), UInt<4>("h00")) @[dbg.scala 315:60]
|
||
|
|
node _T_437 = mux(_T_429, _T_434, _T_436) @[dbg.scala 314:26]
|
||
|
|
dbg_nxtstate <= _T_437 @[dbg.scala 314:20]
|
||
|
|
node _T_438 = bits(dmstatus_reg, 9, 9) @[dbg.scala 316:35]
|
||
|
|
node _T_439 = and(_T_438, resumereq) @[dbg.scala 316:39]
|
||
|
|
node _T_440 = or(_T_439, execute_command) @[dbg.scala 316:51]
|
||
|
|
node _T_441 = bits(dmstatus_reg, 9, 9) @[dbg.scala 316:85]
|
||
|
|
node _T_442 = or(_T_441, io.dec_tlu_mpc_halted_only) @[dbg.scala 316:89]
|
||
|
|
node _T_443 = eq(_T_442, UInt<1>("h00")) @[dbg.scala 316:71]
|
||
|
|
node _T_444 = or(_T_440, _T_443) @[dbg.scala 316:69]
|
||
|
|
dbg_state_en <= _T_444 @[dbg.scala 316:20]
|
||
|
|
node _T_445 = eq(dbg_nxtstate, UInt<4>("h03")) @[dbg.scala 318:62]
|
||
|
|
node _T_446 = eq(dbg_nxtstate, UInt<4>("h05")) @[dbg.scala 318:106]
|
||
|
|
node _T_447 = or(_T_445, _T_446) @[dbg.scala 318:90]
|
||
|
|
node _T_448 = and(dbg_state_en, _T_447) @[dbg.scala 318:45]
|
||
|
|
abstractcs_busy_wren <= _T_448 @[dbg.scala 318:29]
|
||
|
|
abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 319:29]
|
||
|
|
node _T_449 = eq(dbg_nxtstate, UInt<4>("h09")) @[dbg.scala 320:62]
|
||
|
|
node _T_450 = and(dbg_state_en, _T_449) @[dbg.scala 320:46]
|
||
|
|
node _T_451 = bits(_T_450, 0, 0) @[dbg.scala 320:91]
|
||
|
|
io.dbg_resume_req <= _T_451 @[dbg.scala 320:29]
|
||
|
|
node _T_452 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 321:65]
|
||
|
|
node _T_453 = and(dmcontrol_wren_Q, _T_452) @[dbg.scala 321:50]
|
||
|
|
node _T_454 = bits(_T_453, 0, 0) @[dbg.scala 321:77]
|
||
|
|
io.dbg_halt_req <= _T_454 @[dbg.scala 321:29]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_455 = eq(UInt<4>("h03"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_455 : @[Conditional.scala 39:67]
|
||
|
|
node _T_456 = bits(abstractcs_reg, 10, 8) @[dbg.scala 324:44]
|
||
|
|
node _T_457 = orr(_T_456) @[dbg.scala 324:52]
|
||
|
|
node _T_458 = bits(command_reg, 31, 24) @[dbg.scala 324:71]
|
||
|
|
node _T_459 = eq(_T_458, UInt<8>("h00")) @[dbg.scala 324:80]
|
||
|
|
node _T_460 = bits(command_reg, 17, 17) @[dbg.scala 324:108]
|
||
|
|
node _T_461 = eq(_T_460, UInt<1>("h00")) @[dbg.scala 324:96]
|
||
|
|
node _T_462 = and(_T_459, _T_461) @[dbg.scala 324:94]
|
||
|
|
node _T_463 = or(_T_457, _T_462) @[dbg.scala 324:56]
|
||
|
|
node _T_464 = mux(_T_463, UInt<4>("h08"), UInt<4>("h04")) @[dbg.scala 324:29]
|
||
|
|
dbg_nxtstate <= _T_464 @[dbg.scala 324:23]
|
||
|
|
node _T_465 = bits(abstractcs_reg, 10, 8) @[dbg.scala 325:78]
|
||
|
|
node _T_466 = orr(_T_465) @[dbg.scala 325:86]
|
||
|
|
node _T_467 = or(io.dbg_dec_dma.dbg_ib.dbg_cmd_valid, _T_466) @[dbg.scala 325:62]
|
||
|
|
node _T_468 = bits(command_reg, 31, 24) @[dbg.scala 325:105]
|
||
|
|
node _T_469 = eq(_T_468, UInt<8>("h00")) @[dbg.scala 325:114]
|
||
|
|
node _T_470 = bits(command_reg, 17, 17) @[dbg.scala 325:142]
|
||
|
|
node _T_471 = eq(_T_470, UInt<1>("h00")) @[dbg.scala 325:130]
|
||
|
|
node _T_472 = and(_T_469, _T_471) @[dbg.scala 325:128]
|
||
|
|
node _T_473 = or(_T_467, _T_472) @[dbg.scala 325:90]
|
||
|
|
dbg_state_en <= _T_473 @[dbg.scala 325:23]
|
||
|
|
node _T_474 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 326:59]
|
||
|
|
node _T_475 = and(dmcontrol_wren_Q, _T_474) @[dbg.scala 326:44]
|
||
|
|
node _T_476 = bits(_T_475, 0, 0) @[dbg.scala 326:71]
|
||
|
|
io.dbg_halt_req <= _T_476 @[dbg.scala 326:23]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_477 = eq(UInt<4>("h04"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_477 : @[Conditional.scala 39:67]
|
||
|
|
dbg_nxtstate <= UInt<4>("h08") @[dbg.scala 329:23]
|
||
|
|
dbg_state_en <= io.core_dbg_cmd_done @[dbg.scala 330:23]
|
||
|
|
node _T_478 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 331:59]
|
||
|
|
node _T_479 = and(dmcontrol_wren_Q, _T_478) @[dbg.scala 331:44]
|
||
|
|
node _T_480 = bits(_T_479, 0, 0) @[dbg.scala 331:71]
|
||
|
|
io.dbg_halt_req <= _T_480 @[dbg.scala 331:23]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_481 = eq(UInt<4>("h05"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_481 : @[Conditional.scala 39:67]
|
||
|
|
node _T_482 = bits(abstractcs_reg, 10, 8) @[dbg.scala 334:44]
|
||
|
|
node _T_483 = orr(_T_482) @[dbg.scala 334:52]
|
||
|
|
node _T_484 = mux(_T_483, UInt<4>("h08"), UInt<4>("h06")) @[dbg.scala 334:29]
|
||
|
|
dbg_nxtstate <= _T_484 @[dbg.scala 334:23]
|
||
|
|
node _T_485 = eq(sb_cmd_pending, UInt<1>("h00")) @[dbg.scala 335:47]
|
||
|
|
node _T_486 = and(io.dbg_bus_clk_en, _T_485) @[dbg.scala 335:45]
|
||
|
|
node _T_487 = bits(abstractcs_reg, 10, 8) @[dbg.scala 335:80]
|
||
|
|
node _T_488 = orr(_T_487) @[dbg.scala 335:88]
|
||
|
|
node _T_489 = or(_T_486, _T_488) @[dbg.scala 335:64]
|
||
|
|
dbg_state_en <= _T_489 @[dbg.scala 335:23]
|
||
|
|
node _T_490 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 336:59]
|
||
|
|
node _T_491 = and(dmcontrol_wren_Q, _T_490) @[dbg.scala 336:44]
|
||
|
|
node _T_492 = bits(_T_491, 0, 0) @[dbg.scala 336:71]
|
||
|
|
io.dbg_halt_req <= _T_492 @[dbg.scala 336:23]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_493 = eq(UInt<4>("h06"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_493 : @[Conditional.scala 39:67]
|
||
|
|
sb_abmem_cmd_done_in <= UInt<1>("h01") @[dbg.scala 339:29]
|
||
|
|
sb_abmem_data_done_in <= UInt<1>("h01") @[dbg.scala 340:29]
|
||
|
|
node _T_494 = or(sb_bus_cmd_read, sb_bus_cmd_write_addr) @[dbg.scala 341:49]
|
||
|
|
node _T_495 = and(_T_494, io.dbg_bus_clk_en) @[dbg.scala 341:74]
|
||
|
|
sb_abmem_cmd_done_en <= _T_495 @[dbg.scala 341:29]
|
||
|
|
node _T_496 = or(sb_bus_cmd_read, sb_bus_cmd_write_data) @[dbg.scala 342:49]
|
||
|
|
node _T_497 = and(_T_496, io.dbg_bus_clk_en) @[dbg.scala 342:74]
|
||
|
|
sb_abmem_data_done_en <= _T_497 @[dbg.scala 342:29]
|
||
|
|
dbg_nxtstate <= UInt<4>("h07") @[dbg.scala 343:29]
|
||
|
|
node _T_498 = or(sb_abmem_cmd_done, sb_abmem_cmd_done_en) @[dbg.scala 344:51]
|
||
|
|
node _T_499 = or(sb_abmem_data_done, sb_abmem_data_done_en) @[dbg.scala 344:97]
|
||
|
|
node _T_500 = and(_T_498, _T_499) @[dbg.scala 344:75]
|
||
|
|
node _T_501 = and(_T_500, io.dbg_bus_clk_en) @[dbg.scala 344:122]
|
||
|
|
dbg_state_en <= _T_501 @[dbg.scala 344:29]
|
||
|
|
node _T_502 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 345:65]
|
||
|
|
node _T_503 = and(dmcontrol_wren_Q, _T_502) @[dbg.scala 345:50]
|
||
|
|
node _T_504 = bits(_T_503, 0, 0) @[dbg.scala 345:77]
|
||
|
|
io.dbg_halt_req <= _T_504 @[dbg.scala 345:29]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_505 = eq(UInt<4>("h07"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_505 : @[Conditional.scala 39:67]
|
||
|
|
dbg_nxtstate <= UInt<4>("h08") @[dbg.scala 348:25]
|
||
|
|
node _T_506 = or(sb_bus_rsp_read, sb_bus_rsp_write) @[dbg.scala 349:45]
|
||
|
|
node _T_507 = and(_T_506, io.dbg_bus_clk_en) @[dbg.scala 349:65]
|
||
|
|
dbg_state_en <= _T_507 @[dbg.scala 349:25]
|
||
|
|
node _T_508 = or(sb_bus_rsp_read, sb_bus_rsp_write) @[dbg.scala 350:45]
|
||
|
|
node _T_509 = and(_T_508, sb_bus_rsp_error) @[dbg.scala 350:65]
|
||
|
|
node _T_510 = and(_T_509, io.dbg_bus_clk_en) @[dbg.scala 350:84]
|
||
|
|
dbg_sb_bus_error <= _T_510 @[dbg.scala 350:25]
|
||
|
|
node _T_511 = eq(sb_abmem_cmd_write, UInt<1>("h00")) @[dbg.scala 351:43]
|
||
|
|
node _T_512 = and(dbg_state_en, _T_511) @[dbg.scala 351:41]
|
||
|
|
node _T_513 = eq(dbg_sb_bus_error, UInt<1>("h00")) @[dbg.scala 351:65]
|
||
|
|
node _T_514 = and(_T_512, _T_513) @[dbg.scala 351:63]
|
||
|
|
data0_reg_wren2 <= _T_514 @[dbg.scala 351:25]
|
||
|
|
node _T_515 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 352:61]
|
||
|
|
node _T_516 = and(dmcontrol_wren_Q, _T_515) @[dbg.scala 352:46]
|
||
|
|
node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 352:73]
|
||
|
|
io.dbg_halt_req <= _T_517 @[dbg.scala 352:25]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_518 = eq(UInt<4>("h08"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_518 : @[Conditional.scala 39:67]
|
||
|
|
dbg_nxtstate <= UInt<4>("h02") @[dbg.scala 355:29]
|
||
|
|
dbg_state_en <= UInt<1>("h01") @[dbg.scala 356:29]
|
||
|
|
abstractcs_busy_wren <= dbg_state_en @[dbg.scala 357:29]
|
||
|
|
abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 358:29]
|
||
|
|
node _T_519 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 359:65]
|
||
|
|
node _T_520 = and(dmcontrol_wren_Q, _T_519) @[dbg.scala 359:50]
|
||
|
|
node _T_521 = bits(_T_520, 0, 0) @[dbg.scala 359:77]
|
||
|
|
io.dbg_halt_req <= _T_521 @[dbg.scala 359:29]
|
||
|
|
sb_abmem_cmd_done_in <= UInt<1>("h00") @[dbg.scala 360:29]
|
||
|
|
sb_abmem_data_done_in <= UInt<1>("h00") @[dbg.scala 361:29]
|
||
|
|
sb_abmem_cmd_done_en <= UInt<1>("h01") @[dbg.scala 362:29]
|
||
|
|
sb_abmem_data_done_en <= UInt<1>("h01") @[dbg.scala 363:29]
|
||
|
|
node _T_522 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 364:65]
|
||
|
|
node _T_523 = and(dmcontrol_wren_Q, _T_522) @[dbg.scala 364:50]
|
||
|
|
node _T_524 = bits(_T_523, 0, 0) @[dbg.scala 364:77]
|
||
|
|
io.dbg_halt_req <= _T_524 @[dbg.scala 364:29]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_525 = eq(UInt<4>("h09"), dbg_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_525 : @[Conditional.scala 39:67]
|
||
|
|
dbg_nxtstate <= UInt<4>("h00") @[dbg.scala 367:20]
|
||
|
|
node _T_526 = bits(dmstatus_reg, 17, 17) @[dbg.scala 368:35]
|
||
|
|
dbg_state_en <= _T_526 @[dbg.scala 368:20]
|
||
|
|
node _T_527 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 369:59]
|
||
|
|
node _T_528 = and(dmcontrol_wren_Q, _T_527) @[dbg.scala 369:44]
|
||
|
|
node _T_529 = bits(_T_528, 0, 0) @[dbg.scala 369:71]
|
||
|
|
io.dbg_halt_req <= _T_529 @[dbg.scala 369:23]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
node _T_530 = eq(io.dmi_reg_addr, UInt<7>("h04")) @[dbg.scala 372:52]
|
||
|
|
node _T_531 = bits(_T_530, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_532 = mux(_T_531, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_533 = and(_T_532, data0_reg) @[dbg.scala 372:76]
|
||
|
|
node _T_534 = eq(io.dmi_reg_addr, UInt<7>("h05")) @[dbg.scala 373:30]
|
||
|
|
node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_536 = mux(_T_535, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_537 = and(_T_536, abmem_addr) @[dbg.scala 373:47]
|
||
|
|
node _T_538 = or(_T_533, _T_537) @[dbg.scala 372:88]
|
||
|
|
node _T_539 = eq(io.dmi_reg_addr, UInt<7>("h010")) @[dbg.scala 374:30]
|
||
|
|
node _T_540 = bits(_T_539, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_541 = mux(_T_540, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_542 = bits(dmcontrol_reg, 29, 29) @[dbg.scala 374:77]
|
||
|
|
node _T_543 = bits(dmcontrol_reg, 27, 0) @[dbg.scala 374:101]
|
||
|
|
node _T_544 = cat(UInt<1>("h00"), _T_543) @[Cat.scala 29:58]
|
||
|
|
node _T_545 = cat(UInt<2>("h00"), _T_542) @[Cat.scala 29:58]
|
||
|
|
node _T_546 = cat(_T_545, _T_544) @[Cat.scala 29:58]
|
||
|
|
node _T_547 = and(_T_541, _T_546) @[dbg.scala 374:48]
|
||
|
|
node _T_548 = or(_T_538, _T_547) @[dbg.scala 373:59]
|
||
|
|
node _T_549 = eq(io.dmi_reg_addr, UInt<7>("h011")) @[dbg.scala 375:30]
|
||
|
|
node _T_550 = bits(_T_549, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_551 = mux(_T_550, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_552 = and(_T_551, dmstatus_reg) @[dbg.scala 375:48]
|
||
|
|
node _T_553 = or(_T_548, _T_552) @[dbg.scala 374:109]
|
||
|
|
node _T_554 = eq(io.dmi_reg_addr, UInt<7>("h016")) @[dbg.scala 376:30]
|
||
|
|
node _T_555 = bits(_T_554, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_556 = mux(_T_555, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_557 = and(_T_556, abstractcs_reg) @[dbg.scala 376:48]
|
||
|
|
node _T_558 = or(_T_553, _T_557) @[dbg.scala 375:63]
|
||
|
|
node _T_559 = eq(io.dmi_reg_addr, UInt<7>("h017")) @[dbg.scala 377:30]
|
||
|
|
node _T_560 = bits(_T_559, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_561 = mux(_T_560, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_562 = and(_T_561, command_reg) @[dbg.scala 377:48]
|
||
|
|
node _T_563 = or(_T_558, _T_562) @[dbg.scala 376:65]
|
||
|
|
node _T_564 = eq(io.dmi_reg_addr, UInt<7>("h018")) @[dbg.scala 378:30]
|
||
|
|
node _T_565 = bits(_T_564, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_566 = mux(_T_565, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_567 = bits(abstractauto_reg, 1, 0) @[dbg.scala 378:81]
|
||
|
|
node _T_568 = cat(UInt<30>("h00"), _T_567) @[Cat.scala 29:58]
|
||
|
|
node _T_569 = and(_T_566, _T_568) @[dbg.scala 378:48]
|
||
|
|
node _T_570 = or(_T_563, _T_569) @[dbg.scala 377:62]
|
||
|
|
node _T_571 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 379:30]
|
||
|
|
node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_573 = mux(_T_572, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_574 = and(_T_573, haltsum0_reg) @[dbg.scala 379:48]
|
||
|
|
node _T_575 = or(_T_570, _T_574) @[dbg.scala 378:88]
|
||
|
|
node _T_576 = eq(io.dmi_reg_addr, UInt<7>("h038")) @[dbg.scala 380:30]
|
||
|
|
node _T_577 = bits(_T_576, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_578 = mux(_T_577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_579 = and(_T_578, sbcs_reg) @[dbg.scala 380:48]
|
||
|
|
node _T_580 = or(_T_575, _T_579) @[dbg.scala 379:63]
|
||
|
|
node _T_581 = eq(io.dmi_reg_addr, UInt<7>("h039")) @[dbg.scala 381:30]
|
||
|
|
node _T_582 = bits(_T_581, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_583 = mux(_T_582, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_584 = and(_T_583, sbaddress0_reg) @[dbg.scala 381:48]
|
||
|
|
node _T_585 = or(_T_580, _T_584) @[dbg.scala 380:59]
|
||
|
|
node _T_586 = eq(io.dmi_reg_addr, UInt<7>("h03c")) @[dbg.scala 382:30]
|
||
|
|
node _T_587 = bits(_T_586, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_588 = mux(_T_587, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_589 = and(_T_588, sbdata0_reg) @[dbg.scala 382:48]
|
||
|
|
node _T_590 = or(_T_585, _T_589) @[dbg.scala 381:65]
|
||
|
|
node _T_591 = eq(io.dmi_reg_addr, UInt<7>("h03d")) @[dbg.scala 383:30]
|
||
|
|
node _T_592 = bits(_T_591, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_593 = mux(_T_592, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_594 = and(_T_593, sbdata1_reg) @[dbg.scala 383:48]
|
||
|
|
node dmi_reg_rdata_din = or(_T_590, _T_594) @[dbg.scala 382:62]
|
||
|
|
node _T_595 = asUInt(dbg_dm_rst_l) @[dbg.scala 385:68]
|
||
|
|
node _T_596 = and(_T_595, temp_rst) @[dbg.scala 385:71]
|
||
|
|
node _T_597 = asAsyncReset(_T_596) @[dbg.scala 385:95]
|
||
|
|
reg _T_598 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_597, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when dbg_state_en : @[Reg.scala 28:19]
|
||
|
|
_T_598 <= dbg_nxtstate @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
dbg_state <= _T_598 @[dbg.scala 385:13]
|
||
|
|
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 409:23]
|
||
|
|
rvclkhdr_9.clock <= clock
|
||
|
|
rvclkhdr_9.reset <= dbg_dm_rst_l
|
||
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 411:18]
|
||
|
|
rvclkhdr_9.io.en <= io.dmi_reg_en @[lib.scala 412:17]
|
||
|
|
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24]
|
||
|
|
reg _T_599 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when io.dmi_reg_en : @[Reg.scala 28:19]
|
||
|
|
_T_599 <= dmi_reg_rdata_din @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
io.dmi_reg_rdata <= _T_599 @[dbg.scala 388:21]
|
||
|
|
node _T_600 = or(abmem_addr_in_dccm_region, abmem_addr_in_iccm_region) @[dbg.scala 392:58]
|
||
|
|
node abmem_addr_core_local = or(_T_600, abmem_addr_in_pic_region) @[dbg.scala 392:86]
|
||
|
|
node _T_601 = eq(abmem_addr_core_local, UInt<1>("h00")) @[dbg.scala 393:31]
|
||
|
|
abmem_addr_external <= _T_601 @[dbg.scala 393:28]
|
||
|
|
node _T_602 = bits(abmem_addr, 31, 28) @[dbg.scala 395:43]
|
||
|
|
node _T_603 = eq(_T_602, UInt<4>("h0f")) @[dbg.scala 395:51]
|
||
|
|
node _T_604 = and(_T_603, UInt<1>("h01")) @[dbg.scala 395:75]
|
||
|
|
abmem_addr_in_dccm_region <= _T_604 @[dbg.scala 395:29]
|
||
|
|
node _T_605 = bits(abmem_addr, 31, 28) @[dbg.scala 396:43]
|
||
|
|
node _T_606 = eq(_T_605, UInt<4>("h0e")) @[dbg.scala 396:51]
|
||
|
|
node _T_607 = and(_T_606, UInt<1>("h01")) @[dbg.scala 396:75]
|
||
|
|
abmem_addr_in_iccm_region <= _T_607 @[dbg.scala 396:29]
|
||
|
|
node _T_608 = bits(abmem_addr, 31, 28) @[dbg.scala 397:43]
|
||
|
|
node _T_609 = eq(_T_608, UInt<4>("h0f")) @[dbg.scala 397:51]
|
||
|
|
abmem_addr_in_pic_region <= _T_609 @[dbg.scala 397:29]
|
||
|
|
node _T_610 = bits(command_reg, 31, 24) @[dbg.scala 399:59]
|
||
|
|
node _T_611 = eq(_T_610, UInt<2>("h02")) @[dbg.scala 399:68]
|
||
|
|
node _T_612 = bits(command_reg, 11, 0) @[dbg.scala 399:118]
|
||
|
|
node _T_613 = cat(UInt<20>("h00"), _T_612) @[Cat.scala 29:58]
|
||
|
|
node _T_614 = mux(_T_611, abmem_addr, _T_613) @[dbg.scala 399:46]
|
||
|
|
io.dbg_dec_dma.dbg_ib.dbg_cmd_addr <= _T_614 @[dbg.scala 399:40]
|
||
|
|
node _T_615 = bits(data0_reg, 31, 0) @[dbg.scala 400:54]
|
||
|
|
io.dbg_dec_dma.dbg_dctl.dbg_cmd_wrdata <= _T_615 @[dbg.scala 400:42]
|
||
|
|
node _T_616 = eq(dbg_state, UInt<4>("h03")) @[dbg.scala 401:54]
|
||
|
|
node _T_617 = bits(abstractcs_reg, 10, 8) @[dbg.scala 401:101]
|
||
|
|
node _T_618 = orr(_T_617) @[dbg.scala 401:108]
|
||
|
|
node _T_619 = bits(command_reg, 31, 24) @[dbg.scala 401:128]
|
||
|
|
node _T_620 = eq(_T_619, UInt<8>("h00")) @[dbg.scala 401:136]
|
||
|
|
node _T_621 = bits(command_reg, 17, 17) @[dbg.scala 401:164]
|
||
|
|
node _T_622 = eq(_T_621, UInt<1>("h00")) @[dbg.scala 401:152]
|
||
|
|
node _T_623 = and(_T_620, _T_622) @[dbg.scala 401:150]
|
||
|
|
node _T_624 = or(_T_618, _T_623) @[dbg.scala 401:113]
|
||
|
|
node _T_625 = bits(command_reg, 31, 24) @[dbg.scala 402:18]
|
||
|
|
node _T_626 = eq(_T_625, UInt<8>("h02")) @[dbg.scala 402:26]
|
||
|
|
node _T_627 = and(_T_626, abmem_addr_external) @[dbg.scala 402:40]
|
||
|
|
node _T_628 = or(_T_624, _T_627) @[dbg.scala 401:170]
|
||
|
|
node _T_629 = eq(_T_628, UInt<1>("h00")) @[dbg.scala 401:84]
|
||
|
|
node _T_630 = and(_T_616, _T_629) @[dbg.scala 401:82]
|
||
|
|
node _T_631 = and(_T_630, io.dbg_dma.dma_dbg_ready) @[dbg.scala 402:64]
|
||
|
|
io.dbg_dec_dma.dbg_ib.dbg_cmd_valid <= _T_631 @[dbg.scala 401:40]
|
||
|
|
node _T_632 = bits(command_reg, 16, 16) @[dbg.scala 403:54]
|
||
|
|
node _T_633 = bits(_T_632, 0, 0) @[dbg.scala 403:65]
|
||
|
|
io.dbg_dec_dma.dbg_ib.dbg_cmd_write <= _T_633 @[dbg.scala 403:40]
|
||
|
|
node _T_634 = bits(command_reg, 31, 24) @[dbg.scala 404:59]
|
||
|
|
node _T_635 = eq(_T_634, UInt<2>("h02")) @[dbg.scala 404:68]
|
||
|
|
node _T_636 = bits(command_reg, 15, 12) @[dbg.scala 404:114]
|
||
|
|
node _T_637 = eq(_T_636, UInt<1>("h00")) @[dbg.scala 404:123]
|
||
|
|
node _T_638 = cat(UInt<1>("h00"), _T_637) @[Cat.scala 29:58]
|
||
|
|
node _T_639 = mux(_T_635, UInt<2>("h02"), _T_638) @[dbg.scala 404:46]
|
||
|
|
io.dbg_dec_dma.dbg_ib.dbg_cmd_type <= _T_639 @[dbg.scala 404:40]
|
||
|
|
node _T_640 = bits(command_reg, 21, 20) @[dbg.scala 405:35]
|
||
|
|
io.dbg_cmd_size <= _T_640 @[dbg.scala 405:21]
|
||
|
|
node _T_641 = bits(command_reg, 31, 24) @[dbg.scala 407:43]
|
||
|
|
node _T_642 = eq(_T_641, UInt<8>("h02")) @[dbg.scala 407:51]
|
||
|
|
node _T_643 = bits(sb_abmem_cmd_size, 1, 0) @[dbg.scala 407:96]
|
||
|
|
node _T_644 = dshl(UInt<4>("h01"), _T_643) @[dbg.scala 407:76]
|
||
|
|
node dbg_cmd_addr_incr = mux(_T_642, _T_644, UInt<4>("h01")) @[dbg.scala 407:30]
|
||
|
|
node _T_645 = bits(command_reg, 31, 24) @[dbg.scala 408:43]
|
||
|
|
node _T_646 = eq(_T_645, UInt<8>("h02")) @[dbg.scala 408:51]
|
||
|
|
node _T_647 = bits(command_reg, 15, 0) @[dbg.scala 408:103]
|
||
|
|
node _T_648 = cat(UInt<16>("h00"), _T_647) @[Cat.scala 29:58]
|
||
|
|
node dbg_cmd_curr_addr = mux(_T_646, abmem_addr, _T_648) @[dbg.scala 408:30]
|
||
|
|
node _T_649 = cat(UInt<28>("h00"), dbg_cmd_addr_incr) @[Cat.scala 29:58]
|
||
|
|
node _T_650 = add(dbg_cmd_curr_addr, _T_649) @[dbg.scala 409:45]
|
||
|
|
node _T_651 = tail(_T_650, 1) @[dbg.scala 409:45]
|
||
|
|
dbg_cmd_next_addr <= _T_651 @[dbg.scala 409:24]
|
||
|
|
node _T_652 = eq(dbg_state, UInt<4>("h03")) @[dbg.scala 411:44]
|
||
|
|
node _T_653 = bits(abstractcs_reg, 10, 8) @[dbg.scala 411:90]
|
||
|
|
node _T_654 = orr(_T_653) @[dbg.scala 411:98]
|
||
|
|
node _T_655 = not(_T_654) @[dbg.scala 411:74]
|
||
|
|
node _T_656 = and(_T_652, _T_655) @[dbg.scala 411:72]
|
||
|
|
node _T_657 = eq(dbg_state, UInt<4>("h04")) @[dbg.scala 411:116]
|
||
|
|
node _T_658 = or(_T_656, _T_657) @[dbg.scala 411:103]
|
||
|
|
node _T_659 = bits(_T_658, 0, 0) @[dbg.scala 411:150]
|
||
|
|
io.dbg_dma.dbg_dma_bubble <= _T_659 @[dbg.scala 411:29]
|
||
|
|
node _T_660 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 413:41]
|
||
|
|
node _T_661 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 413:76]
|
||
|
|
node _T_662 = or(_T_660, _T_661) @[dbg.scala 413:64]
|
||
|
|
node _T_663 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 413:111]
|
||
|
|
node _T_664 = or(_T_662, _T_663) @[dbg.scala 413:99]
|
||
|
|
node _T_665 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 414:15]
|
||
|
|
node _T_666 = or(_T_664, _T_665) @[dbg.scala 413:139]
|
||
|
|
node _T_667 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 414:55]
|
||
|
|
node _T_668 = or(_T_666, _T_667) @[dbg.scala 414:43]
|
||
|
|
node _T_669 = eq(sb_state, UInt<4>("h08")) @[dbg.scala 414:90]
|
||
|
|
node _T_670 = or(_T_668, _T_669) @[dbg.scala 414:78]
|
||
|
|
sb_cmd_pending <= _T_670 @[dbg.scala 413:28]
|
||
|
|
node _T_671 = eq(dbg_state, UInt<4>("h05")) @[dbg.scala 415:42]
|
||
|
|
node _T_672 = eq(dbg_state, UInt<4>("h06")) @[dbg.scala 415:81]
|
||
|
|
node _T_673 = or(_T_671, _T_672) @[dbg.scala 415:68]
|
||
|
|
node _T_674 = eq(dbg_state, UInt<4>("h07")) @[dbg.scala 415:119]
|
||
|
|
node sb_abmem_cmd_pending = or(_T_673, _T_674) @[dbg.scala 415:106]
|
||
|
|
wire sb_nxtstate : UInt<4>
|
||
|
|
sb_nxtstate <= UInt<4>("h00")
|
||
|
|
sb_nxtstate <= UInt<4>("h00") @[dbg.scala 418:15]
|
||
|
|
sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 420:20]
|
||
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 421:19]
|
||
|
|
sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 422:21]
|
||
|
|
sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 423:20]
|
||
|
|
sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 424:24]
|
||
|
|
node _T_675 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_675 : @[Conditional.scala 40:58]
|
||
|
|
node _T_676 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 427:25]
|
||
|
|
sb_nxtstate <= _T_676 @[dbg.scala 427:19]
|
||
|
|
node _T_677 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 428:40]
|
||
|
|
node _T_678 = or(_T_677, sbreadonaddr_access) @[dbg.scala 428:62]
|
||
|
|
node _T_679 = bits(sbcs_reg, 14, 12) @[dbg.scala 428:97]
|
||
|
|
node _T_680 = orr(_T_679) @[dbg.scala 428:105]
|
||
|
|
node _T_681 = not(_T_680) @[dbg.scala 428:87]
|
||
|
|
node _T_682 = and(_T_678, _T_681) @[dbg.scala 428:85]
|
||
|
|
node _T_683 = bits(sbcs_reg, 22, 22) @[dbg.scala 428:121]
|
||
|
|
node _T_684 = eq(_T_683, UInt<1>("h00")) @[dbg.scala 428:112]
|
||
|
|
node _T_685 = and(_T_682, _T_684) @[dbg.scala 428:110]
|
||
|
|
sb_state_en <= _T_685 @[dbg.scala 428:19]
|
||
|
|
sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 429:24]
|
||
|
|
sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 430:23]
|
||
|
|
node _T_686 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 431:56]
|
||
|
|
node _T_687 = orr(_T_686) @[dbg.scala 431:65]
|
||
|
|
node _T_688 = and(sbcs_wren, _T_687) @[dbg.scala 431:38]
|
||
|
|
sbcs_sberror_wren <= _T_688 @[dbg.scala 431:25]
|
||
|
|
node _T_689 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 432:44]
|
||
|
|
node _T_690 = not(_T_689) @[dbg.scala 432:27]
|
||
|
|
node _T_691 = bits(sbcs_reg, 14, 12) @[dbg.scala 432:63]
|
||
|
|
node _T_692 = and(_T_690, _T_691) @[dbg.scala 432:53]
|
||
|
|
sbcs_sberror_din <= _T_692 @[dbg.scala 432:24]
|
||
|
|
skip @[Conditional.scala 40:58]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_693 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_693 : @[Conditional.scala 39:67]
|
||
|
|
node _T_694 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 435:47]
|
||
|
|
node _T_695 = mux(_T_694, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 435:31]
|
||
|
|
sb_nxtstate <= _T_695 @[dbg.scala 435:25]
|
||
|
|
node _T_696 = eq(sb_abmem_cmd_pending, UInt<1>("h00")) @[dbg.scala 436:49]
|
||
|
|
node _T_697 = and(io.dbg_bus_clk_en, _T_696) @[dbg.scala 436:47]
|
||
|
|
node _T_698 = or(_T_697, sbcs_unaligned) @[dbg.scala 436:72]
|
||
|
|
node _T_699 = or(_T_698, sbcs_illegal_size) @[dbg.scala 436:89]
|
||
|
|
sb_state_en <= _T_699 @[dbg.scala 436:25]
|
||
|
|
node _T_700 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 437:43]
|
||
|
|
sbcs_sberror_wren <= _T_700 @[dbg.scala 437:25]
|
||
|
|
node _T_701 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 438:31]
|
||
|
|
sbcs_sberror_din <= _T_701 @[dbg.scala 438:25]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_702 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_702 : @[Conditional.scala 39:67]
|
||
|
|
node _T_703 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 441:47]
|
||
|
|
node _T_704 = mux(_T_703, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 441:31]
|
||
|
|
sb_nxtstate <= _T_704 @[dbg.scala 441:25]
|
||
|
|
node _T_705 = eq(sb_abmem_cmd_pending, UInt<1>("h00")) @[dbg.scala 442:49]
|
||
|
|
node _T_706 = and(io.dbg_bus_clk_en, _T_705) @[dbg.scala 442:47]
|
||
|
|
node _T_707 = or(_T_706, sbcs_unaligned) @[dbg.scala 442:72]
|
||
|
|
node _T_708 = or(_T_707, sbcs_illegal_size) @[dbg.scala 442:89]
|
||
|
|
sb_state_en <= _T_708 @[dbg.scala 442:25]
|
||
|
|
node _T_709 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 443:43]
|
||
|
|
sbcs_sberror_wren <= _T_709 @[dbg.scala 443:25]
|
||
|
|
node _T_710 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 444:31]
|
||
|
|
sbcs_sberror_din <= _T_710 @[dbg.scala 444:25]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_711 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_711 : @[Conditional.scala 39:67]
|
||
|
|
sb_nxtstate <= UInt<4>("h07") @[dbg.scala 447:19]
|
||
|
|
node _T_712 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 448:38]
|
||
|
|
sb_state_en <= _T_712 @[dbg.scala 448:19]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_713 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_713 : @[Conditional.scala 39:67]
|
||
|
|
node _T_714 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 451:48]
|
||
|
|
node _T_715 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 452:12]
|
||
|
|
node _T_716 = mux(_T_714, UInt<4>("h08"), _T_715) @[dbg.scala 451:25]
|
||
|
|
sb_nxtstate <= _T_716 @[dbg.scala 451:19]
|
||
|
|
node _T_717 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 453:45]
|
||
|
|
node _T_718 = and(_T_717, io.dbg_bus_clk_en) @[dbg.scala 453:70]
|
||
|
|
sb_state_en <= _T_718 @[dbg.scala 453:19]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_719 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_719 : @[Conditional.scala 39:67]
|
||
|
|
sb_nxtstate <= UInt<4>("h08") @[dbg.scala 456:19]
|
||
|
|
node _T_720 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 457:44]
|
||
|
|
sb_state_en <= _T_720 @[dbg.scala 457:19]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_721 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_721 : @[Conditional.scala 39:67]
|
||
|
|
sb_nxtstate <= UInt<4>("h08") @[dbg.scala 460:19]
|
||
|
|
node _T_722 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 461:44]
|
||
|
|
sb_state_en <= _T_722 @[dbg.scala 461:19]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_723 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_723 : @[Conditional.scala 39:67]
|
||
|
|
sb_nxtstate <= UInt<4>("h09") @[dbg.scala 464:19]
|
||
|
|
node _T_724 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 465:38]
|
||
|
|
sb_state_en <= _T_724 @[dbg.scala 465:19]
|
||
|
|
node _T_725 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 466:40]
|
||
|
|
sbcs_sberror_wren <= _T_725 @[dbg.scala 466:25]
|
||
|
|
sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 467:24]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_726 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_726 : @[Conditional.scala 39:67]
|
||
|
|
sb_nxtstate <= UInt<4>("h09") @[dbg.scala 470:19]
|
||
|
|
node _T_727 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 471:39]
|
||
|
|
sb_state_en <= _T_727 @[dbg.scala 471:19]
|
||
|
|
node _T_728 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 472:40]
|
||
|
|
sbcs_sberror_wren <= _T_728 @[dbg.scala 472:25]
|
||
|
|
sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 473:24]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
else : @[Conditional.scala 39:67]
|
||
|
|
node _T_729 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
|
||
|
|
when _T_729 : @[Conditional.scala 39:67]
|
||
|
|
sb_nxtstate <= UInt<4>("h00") @[dbg.scala 476:19]
|
||
|
|
sb_state_en <= UInt<1>("h01") @[dbg.scala 477:19]
|
||
|
|
sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 478:24]
|
||
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 479:23]
|
||
|
|
node _T_730 = bits(sbcs_reg, 16, 16) @[dbg.scala 480:39]
|
||
|
|
node _T_731 = bits(sbcs_reg, 14, 12) @[dbg.scala 480:55]
|
||
|
|
node _T_732 = eq(_T_731, UInt<3>("h00")) @[dbg.scala 480:63]
|
||
|
|
node _T_733 = and(_T_730, _T_732) @[dbg.scala 480:44]
|
||
|
|
sbaddress0_reg_wren1 <= _T_733 @[dbg.scala 480:28]
|
||
|
|
skip @[Conditional.scala 39:67]
|
||
|
|
reg _T_734 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||
|
|
when sb_state_en : @[Reg.scala 28:19]
|
||
|
|
_T_734 <= sb_nxtstate @[Reg.scala 28:23]
|
||
|
|
skip @[Reg.scala 28:19]
|
||
|
|
sb_state <= _T_734 @[dbg.scala 483:12]
|
||
|
|
node _T_735 = bits(command_reg, 16, 16) @[dbg.scala 487:48]
|
||
|
|
sb_abmem_cmd_write <= _T_735 @[dbg.scala 487:34]
|
||
|
|
node _T_736 = bits(command_reg, 21, 20) @[dbg.scala 488:62]
|
||
|
|
node _T_737 = cat(UInt<1>("h00"), _T_736) @[Cat.scala 29:58]
|
||
|
|
sb_abmem_cmd_size <= _T_737 @[dbg.scala 488:34]
|
||
|
|
node sb_cmd_size = bits(sbcs_reg, 19, 17) @[dbg.scala 492:31]
|
||
|
|
node _T_738 = bits(sbdata1_reg, 31, 0) @[dbg.scala 493:38]
|
||
|
|
node _T_739 = bits(sbdata0_reg, 31, 0) @[dbg.scala 493:57]
|
||
|
|
node sb_cmd_wdata = cat(_T_738, _T_739) @[Cat.scala 29:58]
|
||
|
|
node sb_cmd_addr = bits(sbaddress0_reg, 31, 0) @[dbg.scala 494:37]
|
||
|
|
node _T_740 = eq(dbg_state, UInt<4>("h06")) @[dbg.scala 496:42]
|
||
|
|
node _T_741 = and(_T_740, sb_abmem_cmd_write) @[dbg.scala 496:67]
|
||
|
|
node _T_742 = eq(sb_abmem_cmd_done, UInt<1>("h00")) @[dbg.scala 496:90]
|
||
|
|
node sb_abmem_cmd_awvalid = and(_T_741, _T_742) @[dbg.scala 496:88]
|
||
|
|
node _T_743 = eq(dbg_state, UInt<4>("h06")) @[dbg.scala 497:42]
|
||
|
|
node _T_744 = and(_T_743, sb_abmem_cmd_write) @[dbg.scala 497:67]
|
||
|
|
node _T_745 = eq(sb_abmem_data_done, UInt<1>("h00")) @[dbg.scala 497:90]
|
||
|
|
node sb_abmem_cmd_wvalid = and(_T_744, _T_745) @[dbg.scala 497:88]
|
||
|
|
node _T_746 = eq(dbg_state, UInt<4>("h06")) @[dbg.scala 498:42]
|
||
|
|
node _T_747 = eq(sb_abmem_cmd_write, UInt<1>("h00")) @[dbg.scala 498:69]
|
||
|
|
node _T_748 = and(_T_746, _T_747) @[dbg.scala 498:67]
|
||
|
|
node _T_749 = eq(sb_abmem_cmd_done, UInt<1>("h00")) @[dbg.scala 498:91]
|
||
|
|
node _T_750 = and(_T_748, _T_749) @[dbg.scala 498:89]
|
||
|
|
node _T_751 = eq(sb_abmem_data_done, UInt<1>("h00")) @[dbg.scala 498:112]
|
||
|
|
node sb_abmem_cmd_arvalid = and(_T_750, _T_751) @[dbg.scala 498:110]
|
||
|
|
node _T_752 = eq(dbg_state, UInt<4>("h07")) @[dbg.scala 499:42]
|
||
|
|
node _T_753 = eq(sb_abmem_cmd_write, UInt<1>("h00")) @[dbg.scala 499:69]
|
||
|
|
node sb_abmem_read_pend = and(_T_752, _T_753) @[dbg.scala 499:67]
|
||
|
|
node _T_754 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 501:36]
|
||
|
|
node _T_755 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 501:71]
|
||
|
|
node sb_cmd_awvalid = or(_T_754, _T_755) @[dbg.scala 501:59]
|
||
|
|
node _T_756 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 502:36]
|
||
|
|
node _T_757 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 502:71]
|
||
|
|
node sb_cmd_wvalid = or(_T_756, _T_757) @[dbg.scala 502:59]
|
||
|
|
node sb_cmd_arvalid = eq(sb_state, UInt<4>("h03")) @[dbg.scala 503:35]
|
||
|
|
node sb_read_pend = eq(sb_state, UInt<4>("h03")) @[dbg.scala 504:35]
|
||
|
|
node _T_758 = or(sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid) @[dbg.scala 506:49]
|
||
|
|
node _T_759 = or(_T_758, sb_abmem_cmd_arvalid) @[dbg.scala 506:71]
|
||
|
|
node _T_760 = or(_T_759, sb_abmem_read_pend) @[dbg.scala 506:94]
|
||
|
|
node _T_761 = bits(sb_abmem_cmd_size, 2, 0) @[dbg.scala 506:134]
|
||
|
|
node _T_762 = bits(sb_cmd_size, 2, 0) @[dbg.scala 506:152]
|
||
|
|
node sb_axi_size = mux(_T_760, _T_761, _T_762) @[dbg.scala 506:26]
|
||
|
|
node _T_763 = or(sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid) @[dbg.scala 507:49]
|
||
|
|
node _T_764 = or(_T_763, sb_abmem_cmd_arvalid) @[dbg.scala 507:71]
|
||
|
|
node _T_765 = or(_T_764, sb_abmem_read_pend) @[dbg.scala 507:94]
|
||
|
|
node _T_766 = bits(abmem_addr, 31, 0) @[dbg.scala 507:134]
|
||
|
|
node _T_767 = bits(sb_cmd_addr, 31, 0) @[dbg.scala 507:153]
|
||
|
|
node sb_axi_addr = mux(_T_765, _T_766, _T_767) @[dbg.scala 507:26]
|
||
|
|
node _T_768 = or(sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid) @[dbg.scala 508:49]
|
||
|
|
node _T_769 = bits(data0_reg, 31, 0) @[dbg.scala 508:99]
|
||
|
|
node _T_770 = cat(_T_769, _T_769) @[Cat.scala 29:58]
|
||
|
|
node _T_771 = bits(sb_cmd_wdata, 63, 0) @[dbg.scala 508:120]
|
||
|
|
node sb_axi_wrdata = mux(_T_768, _T_770, _T_771) @[dbg.scala 508:26]
|
||
|
|
node _T_772 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 510:47]
|
||
|
|
sb_bus_cmd_read <= _T_772 @[dbg.scala 510:25]
|
||
|
|
node _T_773 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 511:47]
|
||
|
|
sb_bus_cmd_write_addr <= _T_773 @[dbg.scala 511:25]
|
||
|
|
node _T_774 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 512:46]
|
||
|
|
sb_bus_cmd_write_data <= _T_774 @[dbg.scala 512:25]
|
||
|
|
node _T_775 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 513:46]
|
||
|
|
sb_bus_rsp_read <= _T_775 @[dbg.scala 513:25]
|
||
|
|
node _T_776 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 514:46]
|
||
|
|
sb_bus_rsp_write <= _T_776 @[dbg.scala 514:25]
|
||
|
|
node _T_777 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 515:67]
|
||
|
|
node _T_778 = orr(_T_777) @[dbg.scala 515:74]
|
||
|
|
node _T_779 = and(sb_bus_rsp_read, _T_778) @[dbg.scala 515:44]
|
||
|
|
node _T_780 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 515:120]
|
||
|
|
node _T_781 = orr(_T_780) @[dbg.scala 515:127]
|
||
|
|
node _T_782 = and(sb_bus_rsp_write, _T_781) @[dbg.scala 515:97]
|
||
|
|
node _T_783 = or(_T_779, _T_782) @[dbg.scala 515:78]
|
||
|
|
sb_bus_rsp_error <= _T_783 @[dbg.scala 515:25]
|
||
|
|
node _T_784 = or(sb_abmem_cmd_awvalid, sb_cmd_awvalid) @[dbg.scala 517:48]
|
||
|
|
io.sb_axi.aw.valid <= _T_784 @[dbg.scala 517:24]
|
||
|
|
io.sb_axi.aw.bits.addr <= sb_axi_addr @[dbg.scala 518:29]
|
||
|
|
io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 519:29]
|
||
|
|
io.sb_axi.aw.bits.size <= sb_axi_size @[dbg.scala 520:29]
|
||
|
|
io.sb_axi.aw.bits.prot <= UInt<3>("h01") @[dbg.scala 521:29]
|
||
|
|
io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 522:29]
|
||
|
|
node _T_785 = bits(sb_axi_addr, 31, 28) @[dbg.scala 523:43]
|
||
|
|
io.sb_axi.aw.bits.region <= _T_785 @[dbg.scala 523:29]
|
||
|
|
io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 524:29]
|
||
|
|
io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 525:29]
|
||
|
|
io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 526:29]
|
||
|
|
io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 527:29]
|
||
|
|
node _T_786 = or(sb_abmem_cmd_wvalid, sb_cmd_wvalid) @[dbg.scala 529:45]
|
||
|
|
io.sb_axi.w.valid <= _T_786 @[dbg.scala 529:22]
|
||
|
|
node _T_787 = eq(sb_axi_size, UInt<3>("h00")) @[dbg.scala 530:52]
|
||
|
|
node _T_788 = bits(_T_787, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_789 = mux(_T_788, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_790 = bits(sb_axi_wrdata, 7, 0) @[dbg.scala 530:91]
|
||
|
|
node _T_791 = cat(_T_790, _T_790) @[Cat.scala 29:58]
|
||
|
|
node _T_792 = cat(_T_791, _T_791) @[Cat.scala 29:58]
|
||
|
|
node _T_793 = cat(_T_792, _T_792) @[Cat.scala 29:58]
|
||
|
|
node _T_794 = and(_T_789, _T_793) @[dbg.scala 530:67]
|
||
|
|
node _T_795 = eq(sb_axi_size, UInt<3>("h01")) @[dbg.scala 531:27]
|
||
|
|
node _T_796 = bits(_T_795, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_797 = mux(_T_796, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_798 = bits(sb_axi_wrdata, 15, 0) @[dbg.scala 531:65]
|
||
|
|
node _T_799 = cat(_T_798, _T_798) @[Cat.scala 29:58]
|
||
|
|
node _T_800 = cat(_T_799, _T_799) @[Cat.scala 29:58]
|
||
|
|
node _T_801 = and(_T_797, _T_800) @[dbg.scala 531:42]
|
||
|
|
node _T_802 = or(_T_794, _T_801) @[dbg.scala 530:100]
|
||
|
|
node _T_803 = eq(sb_axi_size, UInt<3>("h02")) @[dbg.scala 532:27]
|
||
|
|
node _T_804 = bits(_T_803, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_805 = mux(_T_804, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_806 = bits(sb_axi_wrdata, 31, 0) @[dbg.scala 532:66]
|
||
|
|
node _T_807 = cat(_T_806, _T_806) @[Cat.scala 29:58]
|
||
|
|
node _T_808 = and(_T_805, _T_807) @[dbg.scala 532:42]
|
||
|
|
node _T_809 = or(_T_802, _T_808) @[dbg.scala 531:74]
|
||
|
|
node _T_810 = eq(sb_axi_size, UInt<3>("h03")) @[dbg.scala 533:27]
|
||
|
|
node _T_811 = bits(_T_810, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_812 = mux(_T_811, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_813 = and(_T_812, sb_axi_wrdata) @[dbg.scala 533:42]
|
||
|
|
node _T_814 = or(_T_809, _T_813) @[dbg.scala 532:76]
|
||
|
|
io.sb_axi.w.bits.data <= _T_814 @[dbg.scala 530:27]
|
||
|
|
node _T_815 = eq(sb_axi_size, UInt<3>("h00")) @[dbg.scala 535:49]
|
||
|
|
node _T_816 = bits(_T_815, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_817 = mux(_T_816, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_818 = bits(sb_axi_addr, 2, 0) @[dbg.scala 535:93]
|
||
|
|
node _T_819 = dshl(UInt<8>("h01"), _T_818) @[dbg.scala 535:79]
|
||
|
|
node _T_820 = and(_T_817, _T_819) @[dbg.scala 535:64]
|
||
|
|
node _T_821 = eq(sb_axi_size, UInt<3>("h01")) @[dbg.scala 536:26]
|
||
|
|
node _T_822 = bits(_T_821, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_823 = mux(_T_822, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_824 = bits(sb_axi_addr, 2, 1) @[dbg.scala 536:74]
|
||
|
|
node _T_825 = cat(_T_824, UInt<1>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_826 = dshl(UInt<8>("h03"), _T_825) @[dbg.scala 536:56]
|
||
|
|
node _T_827 = and(_T_823, _T_826) @[dbg.scala 536:41]
|
||
|
|
node _T_828 = or(_T_820, _T_827) @[dbg.scala 535:101]
|
||
|
|
node _T_829 = eq(sb_axi_size, UInt<3>("h02")) @[dbg.scala 537:26]
|
||
|
|
node _T_830 = bits(_T_829, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_831 = mux(_T_830, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_832 = bits(sb_axi_addr, 2, 2) @[dbg.scala 537:74]
|
||
|
|
node _T_833 = cat(_T_832, UInt<2>("h00")) @[Cat.scala 29:58]
|
||
|
|
node _T_834 = dshl(UInt<8>("h0f"), _T_833) @[dbg.scala 537:56]
|
||
|
|
node _T_835 = and(_T_831, _T_834) @[dbg.scala 537:41]
|
||
|
|
node _T_836 = or(_T_828, _T_835) @[dbg.scala 536:93]
|
||
|
|
node _T_837 = eq(sb_axi_size, UInt<3>("h03")) @[dbg.scala 538:26]
|
||
|
|
node _T_838 = bits(_T_837, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_839 = mux(_T_838, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_840 = and(_T_839, UInt<8>("h0ff")) @[dbg.scala 538:41]
|
||
|
|
node _T_841 = or(_T_836, _T_840) @[dbg.scala 537:90]
|
||
|
|
io.sb_axi.w.bits.strb <= _T_841 @[dbg.scala 535:25]
|
||
|
|
io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 540:29]
|
||
|
|
node _T_842 = or(sb_abmem_cmd_arvalid, sb_cmd_arvalid) @[dbg.scala 541:48]
|
||
|
|
io.sb_axi.ar.valid <= _T_842 @[dbg.scala 541:24]
|
||
|
|
io.sb_axi.ar.bits.addr <= sb_axi_addr @[dbg.scala 542:29]
|
||
|
|
io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 543:29]
|
||
|
|
io.sb_axi.ar.bits.size <= sb_axi_size @[dbg.scala 544:29]
|
||
|
|
io.sb_axi.ar.bits.prot <= UInt<3>("h01") @[dbg.scala 545:29]
|
||
|
|
io.sb_axi.ar.bits.cache <= UInt<4>("h00") @[dbg.scala 546:29]
|
||
|
|
node _T_843 = bits(sb_axi_addr, 31, 28) @[dbg.scala 547:43]
|
||
|
|
io.sb_axi.ar.bits.region <= _T_843 @[dbg.scala 547:29]
|
||
|
|
io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 548:29]
|
||
|
|
io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 549:29]
|
||
|
|
io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 550:29]
|
||
|
|
io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 551:29]
|
||
|
|
io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 553:21]
|
||
|
|
io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 554:21]
|
||
|
|
node _T_844 = eq(sb_axi_size, UInt<1>("h00")) @[dbg.scala 556:41]
|
||
|
|
node _T_845 = bits(_T_844, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_846 = mux(_T_845, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_847 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 556:79]
|
||
|
|
node _T_848 = bits(sb_axi_addr, 2, 0) @[dbg.scala 556:107]
|
||
|
|
node _T_849 = mul(UInt<4>("h08"), _T_848) @[dbg.scala 556:94]
|
||
|
|
node _T_850 = dshr(_T_847, _T_849) @[dbg.scala 556:87]
|
||
|
|
node _T_851 = and(_T_850, UInt<64>("h0ff")) @[dbg.scala 556:115]
|
||
|
|
node _T_852 = and(_T_846, _T_851) @[dbg.scala 556:54]
|
||
|
|
node _T_853 = eq(sb_axi_size, UInt<1>("h01")) @[dbg.scala 557:27]
|
||
|
|
node _T_854 = bits(_T_853, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_855 = mux(_T_854, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_856 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 557:65]
|
||
|
|
node _T_857 = bits(sb_axi_addr, 2, 1) @[dbg.scala 557:94]
|
||
|
|
node _T_858 = mul(UInt<5>("h010"), _T_857) @[dbg.scala 557:81]
|
||
|
|
node _T_859 = dshr(_T_856, _T_858) @[dbg.scala 557:73]
|
||
|
|
node _T_860 = and(_T_859, UInt<64>("h0ffff")) @[dbg.scala 557:102]
|
||
|
|
node _T_861 = and(_T_855, _T_860) @[dbg.scala 557:40]
|
||
|
|
node _T_862 = or(_T_852, _T_861) @[dbg.scala 556:132]
|
||
|
|
node _T_863 = eq(sb_axi_size, UInt<2>("h02")) @[dbg.scala 558:27]
|
||
|
|
node _T_864 = bits(_T_863, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_865 = mux(_T_864, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_866 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 558:65]
|
||
|
|
node _T_867 = bits(sb_axi_addr, 2, 2) @[dbg.scala 558:94]
|
||
|
|
node _T_868 = mul(UInt<6>("h020"), _T_867) @[dbg.scala 558:81]
|
||
|
|
node _T_869 = dshr(_T_866, _T_868) @[dbg.scala 558:73]
|
||
|
|
node _T_870 = and(_T_869, UInt<64>("h0ffffffff")) @[dbg.scala 558:99]
|
||
|
|
node _T_871 = and(_T_865, _T_870) @[dbg.scala 558:40]
|
||
|
|
node _T_872 = or(_T_862, _T_871) @[dbg.scala 557:121]
|
||
|
|
node _T_873 = eq(sb_axi_size, UInt<2>("h03")) @[dbg.scala 559:27]
|
||
|
|
node _T_874 = bits(_T_873, 0, 0) @[Bitwise.scala 72:15]
|
||
|
|
node _T_875 = mux(_T_874, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
||
|
|
node _T_876 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 559:63]
|
||
|
|
node _T_877 = and(_T_875, _T_876) @[dbg.scala 559:40]
|
||
|
|
node _T_878 = or(_T_872, _T_877) @[dbg.scala 558:123]
|
||
|
|
sb_bus_rdata <= _T_878 @[dbg.scala 556:16]
|
||
|
|
|