37 lines
1.3 KiB
Scala
37 lines
1.3 KiB
Scala
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package exu
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import chisel3._
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import chisel3.util._
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import include._
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import lib._
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class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
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val io = IO(new Bundle{
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val scan_mode = Input(Bool())
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val mul_p = Input(new el2_mul_pkt_t )
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val rs1_in = Input(UInt(32.W))
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val rs2_in = Input(UInt(32.W))
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val result_x = Output(UInt(32.W))
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})
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val rs1_ext_in = WireInit(SInt(33.W), 0.S)
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val rs2_ext_in = WireInit(SInt(33.W), 0.S)
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val prod_x = WireInit(SInt(66.W), 0.S)
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val low_x = WireInit(0.U(1.W))
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val mul_x_enable = io.mul_p.valid
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rs1_ext_in := Cat(io.mul_p.rs1_sign & io.rs1_in(31),io.rs1_in).asSInt
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rs2_ext_in := Cat(io.mul_p.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
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// --------------------------- Multiply ----------------------------------
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low_x := RegEnable (io.mul_p.low, 0.U, mul_x_enable.asBool)
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val rs1_x = RegEnable (rs1_ext_in, 0.S, mul_x_enable.asBool)
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val rs2_x = RegEnable (rs2_ext_in, 0.S, mul_x_enable.asBool)
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prod_x := rs1_x * rs2_x
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io.result_x := Mux1H (Seq(!low_x.asBool -> prod_x(63,32), low_x.asBool -> prod_x(31,0)))
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}
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object mul_main extends App{
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println("Generate Verilog")
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_mul_ctl()))
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}
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