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lsu updated

This commit is contained in:
​laraibkhan119 2020-10-22 14:52:47 +05:00
parent 2a2474ca44
commit 4e107cc640
324 changed files with 37522 additions and 4833 deletions
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15
TEC_RV_ICG.v Normal file
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module TEC_RV_ICG(
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

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dmi_jtag_to_core_sync.anno.json Normal file
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[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_jtag_to_core_sync"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

35
dmi_jtag_to_core_sync.fir Normal file
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_jtag_to_core_sync :
module dmi_jtag_to_core_sync :
input clock : Clock
input reset : AsyncReset
output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
io.reg_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 19:16]
io.reg_wr_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 20:16]
wire rden : UInt<3>
rden <= UInt<1>("h00")
wire wren : UInt<3>
wren <= UInt<1>("h00")
node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 25:27]
node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 25:18]
_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 25:18]
rden <= _T_2 @[dmi_jtag_to_core_sync.scala 25:8]
node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 26:18]
wren <= _T_5 @[dmi_jtag_to_core_sync.scala 26:8]
node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:21]
node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:32]
node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:27]
node c_rd_en = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:25]
node _T_9 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:21]
node _T_10 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:32]
node _T_11 = eq(_T_10, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:27]
node c_wr_en = and(_T_9, _T_11) @[dmi_jtag_to_core_sync.scala 29:25]
node _T_12 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:24]
io.reg_en <= _T_12 @[dmi_jtag_to_core_sync.scala 31:13]
io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:16]

87
dmi_jtag_to_core_sync.v Normal file
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module dmi_jtag_to_core_sync(
input clock,
input reset,
input io_rd_en,
input io_wr_en,
output io_reg_en,
output io_reg_wr_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 25:18]
reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 26:18]
wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:27]
wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:25]
wire _T_11 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:27]
wire c_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 29:25]
assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 19:16 dmi_jtag_to_core_sync.scala 31:13]
assign io_reg_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 20:16 dmi_jtag_to_core_sync.scala 32:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rden = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wren = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
rden = 3'h0;
end
if (reset) begin
wren = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
rden <= 3'h0;
end else begin
rden <= {rden[1:0],io_rd_en};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wren <= 3'h0;
end else begin
wren <= {wren[1:0],io_wr_en};
end
end
endmodule

18
dmi_wrapper.anno.json Normal file
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[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_wrapper"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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dmi_wrapper.fir Normal file
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_wrapper :
module rvjtag_tap :
input clock : Clock
input reset : AsyncReset
output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, flip rd_data : UInt<32>, flip rd_status : UInt<2>, flip idle : UInt<3>, flip dmi_stat : UInt<2>, flip jtag_id : UInt<32>, flip version : UInt<4>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<7>, wr_en : UInt<1>, rd_en : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>}
io.tdo <= UInt<1>("h00") @[rvjtag_tap.scala 31:21]
io.tdoEnable <= UInt<1>("h00") @[rvjtag_tap.scala 32:21]
io.wr_data <= UInt<1>("h00") @[rvjtag_tap.scala 33:21]
io.wr_addr <= UInt<1>("h00") @[rvjtag_tap.scala 34:21]
io.wr_en <= UInt<1>("h00") @[rvjtag_tap.scala 35:21]
io.rd_en <= UInt<1>("h00") @[rvjtag_tap.scala 36:21]
io.dmi_reset <= UInt<1>("h00") @[rvjtag_tap.scala 37:21]
io.dmi_hard_reset <= UInt<1>("h00") @[rvjtag_tap.scala 38:21]
module dmi_jtag_to_core_sync :
input clock : Clock
input reset : AsyncReset
output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
io.reg_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 19:16]
io.reg_wr_en <= UInt<1>("h00") @[dmi_jtag_to_core_sync.scala 20:16]
wire rden : UInt<3>
rden <= UInt<1>("h00")
wire wren : UInt<3>
wren <= UInt<1>("h00")
node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 25:27]
node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 25:18]
_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 25:18]
rden <= _T_2 @[dmi_jtag_to_core_sync.scala 25:8]
node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 26:18]
wren <= _T_5 @[dmi_jtag_to_core_sync.scala 26:8]
node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:21]
node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:32]
node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:27]
node c_rd_en = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:25]
node _T_9 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:21]
node _T_10 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:32]
node _T_11 = eq(_T_10, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:27]
node c_wr_en = and(_T_9, _T_11) @[dmi_jtag_to_core_sync.scala 29:25]
node _T_12 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:24]
io.reg_en <= _T_12 @[dmi_jtag_to_core_sync.scala 31:13]
io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:16]
module dmi_wrapper :
input clock : Clock
input reset : AsyncReset
output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip core_clk : Clock, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
wire rd_en : UInt<1>
rd_en <= UInt<1>("h00")
wire wr_en : UInt<1>
wr_en <= UInt<1>("h00")
wire dmireset : UInt<1>
dmireset <= UInt<1>("h00")
inst i_jtag_tap of rvjtag_tap @[dmi_wrapper.scala 33:27]
i_jtag_tap.clock <= clock
i_jtag_tap.reset <= reset
i_jtag_tap.io.tck <= io.tck @[dmi_wrapper.scala 36:27]
i_jtag_tap.io.tms <= io.tms @[dmi_wrapper.scala 37:27]
i_jtag_tap.io.tdi <= io.tdi @[dmi_wrapper.scala 38:27]
i_jtag_tap.io.rd_data <= io.rd_data @[dmi_wrapper.scala 39:27]
i_jtag_tap.io.rd_status <= UInt<2>("h00") @[dmi_wrapper.scala 40:27]
i_jtag_tap.io.idle <= UInt<3>("h00") @[dmi_wrapper.scala 41:27]
i_jtag_tap.io.dmi_stat <= UInt<2>("h00") @[dmi_wrapper.scala 42:27]
i_jtag_tap.io.jtag_id <= io.jtag_id @[dmi_wrapper.scala 43:27]
i_jtag_tap.io.version <= UInt<1>("h01") @[dmi_wrapper.scala 44:27]
io.tdo <= i_jtag_tap.io.tdo @[dmi_wrapper.scala 46:27]
io.tdoEnable <= i_jtag_tap.io.tdoEnable @[dmi_wrapper.scala 47:27]
io.reg_wr_data <= i_jtag_tap.io.wr_data @[dmi_wrapper.scala 48:27]
io.reg_wr_addr <= i_jtag_tap.io.wr_addr @[dmi_wrapper.scala 49:27]
rd_en <= i_jtag_tap.io.rd_en @[dmi_wrapper.scala 50:27]
wr_en <= i_jtag_tap.io.wr_en @[dmi_wrapper.scala 51:27]
io.dmi_hard_reset <= i_jtag_tap.io.dmi_hard_reset @[dmi_wrapper.scala 52:27]
dmireset <= i_jtag_tap.io.dmi_reset @[dmi_wrapper.scala 53:27]
inst i_dmi_jtag_to_core_sync of dmi_jtag_to_core_sync @[dmi_wrapper.scala 56:40]
i_dmi_jtag_to_core_sync.clock <= clock
i_dmi_jtag_to_core_sync.reset <= reset
i_dmi_jtag_to_core_sync.io.wr_en <= wr_en @[dmi_wrapper.scala 57:39]
i_dmi_jtag_to_core_sync.io.rd_en <= rd_en @[dmi_wrapper.scala 58:39]
io.reg_en <= i_dmi_jtag_to_core_sync.io.reg_en @[dmi_wrapper.scala 59:39]
io.reg_wr_en <= i_dmi_jtag_to_core_sync.io.reg_wr_en @[dmi_wrapper.scala 60:39]

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module dmi_jtag_to_core_sync(
input clock,
input reset,
output io_reg_en,
output io_reg_wr_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 25:18]
reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 26:18]
wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:27]
wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:25]
wire _T_11 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:27]
wire c_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 29:25]
assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 19:16 dmi_jtag_to_core_sync.scala 31:13]
assign io_reg_wr_en = wren[1] & _T_11; // @[dmi_jtag_to_core_sync.scala 20:16 dmi_jtag_to_core_sync.scala 32:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rden = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wren = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
rden = 3'h0;
end
if (reset) begin
wren = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
rden <= 3'h0;
end else begin
rden <= {rden[1:0],1'h0};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wren <= 3'h0;
end else begin
wren <= {wren[1:0],1'h0};
end
end
endmodule
module dmi_wrapper(
input clock,
input reset,
input io_tck,
input io_tms,
input io_tdi,
output io_tdo,
output io_tdoEnable,
input io_core_clk,
input [31:0] io_jtag_id,
input [31:0] io_rd_data,
output [31:0] io_reg_wr_data,
output [6:0] io_reg_wr_addr,
output io_reg_en,
output io_reg_wr_en,
output io_dmi_hard_reset
);
wire i_dmi_jtag_to_core_sync_clock; // @[dmi_wrapper.scala 56:40]
wire i_dmi_jtag_to_core_sync_reset; // @[dmi_wrapper.scala 56:40]
wire i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 56:40]
wire i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 56:40]
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync ( // @[dmi_wrapper.scala 56:40]
.clock(i_dmi_jtag_to_core_sync_clock),
.reset(i_dmi_jtag_to_core_sync_reset),
.io_reg_en(i_dmi_jtag_to_core_sync_io_reg_en),
.io_reg_wr_en(i_dmi_jtag_to_core_sync_io_reg_wr_en)
);
assign io_tdo = 1'h0; // @[dmi_wrapper.scala 46:27]
assign io_tdoEnable = 1'h0; // @[dmi_wrapper.scala 47:27]
assign io_reg_wr_data = 32'h0; // @[dmi_wrapper.scala 48:27]
assign io_reg_wr_addr = 7'h0; // @[dmi_wrapper.scala 49:27]
assign io_reg_en = i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 59:39]
assign io_reg_wr_en = i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 60:39]
assign io_dmi_hard_reset = 1'h0; // @[dmi_wrapper.scala 52:27]
assign i_dmi_jtag_to_core_sync_clock = clock;
assign i_dmi_jtag_to_core_sync_reset = reset;
endmodule

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_trigger_match_d",
"sources":[
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_",
"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_select",
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dec_trigger"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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module el2_dec_trigger(
input clock,
input reset,
input io_trigger_pkt_any_0_select,
input io_trigger_pkt_any_0_match_,
input io_trigger_pkt_any_0_store,
input io_trigger_pkt_any_0_load,
input io_trigger_pkt_any_0_execute,
input io_trigger_pkt_any_0_m,
input [31:0] io_trigger_pkt_any_0_tdata2,
input io_trigger_pkt_any_1_select,
input io_trigger_pkt_any_1_match_,
input io_trigger_pkt_any_1_store,
input io_trigger_pkt_any_1_load,
input io_trigger_pkt_any_1_execute,
input io_trigger_pkt_any_1_m,
input [31:0] io_trigger_pkt_any_1_tdata2,
input io_trigger_pkt_any_2_select,
input io_trigger_pkt_any_2_match_,
input io_trigger_pkt_any_2_store,
input io_trigger_pkt_any_2_load,
input io_trigger_pkt_any_2_execute,
input io_trigger_pkt_any_2_m,
input [31:0] io_trigger_pkt_any_2_tdata2,
input io_trigger_pkt_any_3_select,
input io_trigger_pkt_any_3_match_,
input io_trigger_pkt_any_3_store,
input io_trigger_pkt_any_3_load,
input io_trigger_pkt_any_3_execute,
input io_trigger_pkt_any_3_m,
input [31:0] io_trigger_pkt_any_3_tdata2,
input [30:0] io_dec_i0_pc_d,
output [3:0] io_dec_i0_trigger_match_d
);
wire _T = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 15:63]
wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_lsu_trigger.scala 15:93]
wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_lsu_trigger.scala 15:127]
wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_lsu_trigger.scala 15:63]
wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_lsu_trigger.scala 15:93]
wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_lsu_trigger.scala 15:127]
wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_lsu_trigger.scala 15:63]
wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_lsu_trigger.scala 15:93]
wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_lsu_trigger.scala 15:127]
wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_lsu_trigger.scala 15:63]
wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_lsu_trigger.scala 15:93]
wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58]
wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_lsu_trigger.scala 15:127]
wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_lsu_trigger.scala 16:83]
wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 194:45]
wire _T_152 = ~_T_151; // @[el2_lib.scala 194:39]
wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 194:37]
wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 195:52]
wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 195:41]
wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 197:43]
wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 197:80]
wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 197:25]
wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 197:43]
wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 197:80]
wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 197:25]
wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 197:43]
wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 197:80]
wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 197:25]
wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 197:43]
wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 197:80]
wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 197:25]
wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 197:43]
wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 197:80]
wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 197:25]
wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 197:43]
wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 197:80]
wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 197:25]
wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 197:43]
wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 197:80]
wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 197:25]
wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 197:43]
wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 197:80]
wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 197:25]
wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 197:43]
wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 197:80]
wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 197:25]
wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 197:43]
wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 197:80]
wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 197:25]
wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 197:43]
wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 197:80]
wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 197:25]
wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 197:43]
wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 197:80]
wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 197:25]
wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 197:43]
wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 197:80]
wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 197:25]
wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 197:43]
wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 197:80]
wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 197:25]
wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 197:43]
wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 197:80]
wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 197:25]
wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 197:43]
wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 197:80]
wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 197:25]
wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 197:43]
wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 197:80]
wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 197:25]
wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 197:43]
wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 197:80]
wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 197:25]
wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 197:43]
wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 197:80]
wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 197:25]
wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 197:43]
wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 197:80]
wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 197:25]
wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 197:43]
wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 197:80]
wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 197:25]
wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 197:43]
wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 197:80]
wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 197:25]
wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 197:43]
wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 197:80]
wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 197:25]
wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 197:43]
wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 197:80]
wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 197:25]
wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 197:43]
wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 197:80]
wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 197:25]
wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 197:43]
wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 197:80]
wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 197:25]
wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 197:43]
wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 197:80]
wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 197:25]
wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 197:43]
wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 197:80]
wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 197:25]
wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 197:43]
wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 197:80]
wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 197:25]
wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 197:43]
wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 197:80]
wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 197:25]
wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 197:43]
wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 197:80]
wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 197:25]
wire _T_375 = _T_157 & _T_164; // @[el2_lib.scala 198:22]
wire _T_376 = _T_375 & _T_171; // @[el2_lib.scala 198:22]
wire _T_377 = _T_376 & _T_178; // @[el2_lib.scala 198:22]
wire _T_378 = _T_377 & _T_185; // @[el2_lib.scala 198:22]
wire _T_379 = _T_378 & _T_192; // @[el2_lib.scala 198:22]
wire _T_380 = _T_379 & _T_199; // @[el2_lib.scala 198:22]
wire _T_381 = _T_380 & _T_206; // @[el2_lib.scala 198:22]
wire _T_382 = _T_381 & _T_213; // @[el2_lib.scala 198:22]
wire _T_383 = _T_382 & _T_220; // @[el2_lib.scala 198:22]
wire _T_384 = _T_383 & _T_227; // @[el2_lib.scala 198:22]
wire _T_385 = _T_384 & _T_234; // @[el2_lib.scala 198:22]
wire _T_386 = _T_385 & _T_241; // @[el2_lib.scala 198:22]
wire _T_387 = _T_386 & _T_248; // @[el2_lib.scala 198:22]
wire _T_388 = _T_387 & _T_255; // @[el2_lib.scala 198:22]
wire _T_389 = _T_388 & _T_262; // @[el2_lib.scala 198:22]
wire _T_390 = _T_389 & _T_269; // @[el2_lib.scala 198:22]
wire _T_391 = _T_390 & _T_276; // @[el2_lib.scala 198:22]
wire _T_392 = _T_391 & _T_283; // @[el2_lib.scala 198:22]
wire _T_393 = _T_392 & _T_290; // @[el2_lib.scala 198:22]
wire _T_394 = _T_393 & _T_297; // @[el2_lib.scala 198:22]
wire _T_395 = _T_394 & _T_304; // @[el2_lib.scala 198:22]
wire _T_396 = _T_395 & _T_311; // @[el2_lib.scala 198:22]
wire _T_397 = _T_396 & _T_318; // @[el2_lib.scala 198:22]
wire _T_398 = _T_397 & _T_325; // @[el2_lib.scala 198:22]
wire _T_399 = _T_398 & _T_332; // @[el2_lib.scala 198:22]
wire _T_400 = _T_399 & _T_339; // @[el2_lib.scala 198:22]
wire _T_401 = _T_400 & _T_346; // @[el2_lib.scala 198:22]
wire _T_402 = _T_401 & _T_353; // @[el2_lib.scala 198:22]
wire _T_403 = _T_402 & _T_360; // @[el2_lib.scala 198:22]
wire _T_404 = _T_403 & _T_367; // @[el2_lib.scala 198:22]
wire _T_405 = _T_404 & _T_374; // @[el2_lib.scala 198:22]
wire _T_406 = _T_148 & _T_405; // @[el2_lsu_trigger.scala 16:109]
wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_lsu_trigger.scala 16:83]
wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 194:45]
wire _T_411 = ~_T_410; // @[el2_lib.scala 194:39]
wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 194:37]
wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 195:52]
wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 195:41]
wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 197:43]
wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 197:80]
wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 197:25]
wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 197:43]
wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 197:80]
wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 197:25]
wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 197:43]
wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 197:80]
wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 197:25]
wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 197:43]
wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 197:80]
wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 197:25]
wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 197:43]
wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 197:80]
wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 197:25]
wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 197:43]
wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 197:80]
wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 197:25]
wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 197:43]
wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 197:80]
wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 197:25]
wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 197:43]
wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 197:80]
wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 197:25]
wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 197:43]
wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 197:80]
wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 197:25]
wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 197:43]
wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 197:80]
wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 197:25]
wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 197:43]
wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 197:80]
wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 197:25]
wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 197:43]
wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 197:80]
wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 197:25]
wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 197:43]
wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 197:80]
wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 197:25]
wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 197:43]
wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 197:80]
wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 197:25]
wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 197:43]
wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 197:80]
wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 197:25]
wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 197:43]
wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 197:80]
wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 197:25]
wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 197:43]
wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 197:80]
wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 197:25]
wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 197:43]
wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 197:80]
wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 197:25]
wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 197:43]
wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 197:80]
wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 197:25]
wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 197:43]
wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 197:80]
wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 197:25]
wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 197:43]
wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 197:80]
wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 197:25]
wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 197:43]
wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 197:80]
wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 197:25]
wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 197:43]
wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 197:80]
wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 197:25]
wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 197:43]
wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 197:80]
wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 197:25]
wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 197:43]
wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 197:80]
wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 197:25]
wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 197:43]
wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 197:80]
wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 197:25]
wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 197:43]
wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 197:80]
wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 197:25]
wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 197:43]
wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 197:80]
wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 197:25]
wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 197:43]
wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 197:80]
wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 197:25]
wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 197:43]
wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 197:80]
wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 197:25]
wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 197:43]
wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 197:80]
wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 197:25]
wire _T_634 = _T_416 & _T_423; // @[el2_lib.scala 198:22]
wire _T_635 = _T_634 & _T_430; // @[el2_lib.scala 198:22]
wire _T_636 = _T_635 & _T_437; // @[el2_lib.scala 198:22]
wire _T_637 = _T_636 & _T_444; // @[el2_lib.scala 198:22]
wire _T_638 = _T_637 & _T_451; // @[el2_lib.scala 198:22]
wire _T_639 = _T_638 & _T_458; // @[el2_lib.scala 198:22]
wire _T_640 = _T_639 & _T_465; // @[el2_lib.scala 198:22]
wire _T_641 = _T_640 & _T_472; // @[el2_lib.scala 198:22]
wire _T_642 = _T_641 & _T_479; // @[el2_lib.scala 198:22]
wire _T_643 = _T_642 & _T_486; // @[el2_lib.scala 198:22]
wire _T_644 = _T_643 & _T_493; // @[el2_lib.scala 198:22]
wire _T_645 = _T_644 & _T_500; // @[el2_lib.scala 198:22]
wire _T_646 = _T_645 & _T_507; // @[el2_lib.scala 198:22]
wire _T_647 = _T_646 & _T_514; // @[el2_lib.scala 198:22]
wire _T_648 = _T_647 & _T_521; // @[el2_lib.scala 198:22]
wire _T_649 = _T_648 & _T_528; // @[el2_lib.scala 198:22]
wire _T_650 = _T_649 & _T_535; // @[el2_lib.scala 198:22]
wire _T_651 = _T_650 & _T_542; // @[el2_lib.scala 198:22]
wire _T_652 = _T_651 & _T_549; // @[el2_lib.scala 198:22]
wire _T_653 = _T_652 & _T_556; // @[el2_lib.scala 198:22]
wire _T_654 = _T_653 & _T_563; // @[el2_lib.scala 198:22]
wire _T_655 = _T_654 & _T_570; // @[el2_lib.scala 198:22]
wire _T_656 = _T_655 & _T_577; // @[el2_lib.scala 198:22]
wire _T_657 = _T_656 & _T_584; // @[el2_lib.scala 198:22]
wire _T_658 = _T_657 & _T_591; // @[el2_lib.scala 198:22]
wire _T_659 = _T_658 & _T_598; // @[el2_lib.scala 198:22]
wire _T_660 = _T_659 & _T_605; // @[el2_lib.scala 198:22]
wire _T_661 = _T_660 & _T_612; // @[el2_lib.scala 198:22]
wire _T_662 = _T_661 & _T_619; // @[el2_lib.scala 198:22]
wire _T_663 = _T_662 & _T_626; // @[el2_lib.scala 198:22]
wire _T_664 = _T_663 & _T_633; // @[el2_lib.scala 198:22]
wire _T_665 = _T_407 & _T_664; // @[el2_lsu_trigger.scala 16:109]
wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_lsu_trigger.scala 16:83]
wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 194:45]
wire _T_670 = ~_T_669; // @[el2_lib.scala 194:39]
wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 194:37]
wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 195:52]
wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 195:41]
wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 197:43]
wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 197:80]
wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 197:25]
wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 197:43]
wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 197:80]
wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 197:25]
wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 197:43]
wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 197:80]
wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 197:25]
wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 197:43]
wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 197:80]
wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 197:25]
wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 197:43]
wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 197:80]
wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 197:25]
wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 197:43]
wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 197:80]
wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 197:25]
wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 197:43]
wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 197:80]
wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 197:25]
wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 197:43]
wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 197:80]
wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 197:25]
wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 197:43]
wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 197:80]
wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 197:25]
wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 197:43]
wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 197:80]
wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 197:25]
wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 197:43]
wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 197:80]
wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 197:25]
wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 197:43]
wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 197:80]
wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 197:25]
wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 197:43]
wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 197:80]
wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 197:25]
wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 197:43]
wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 197:80]
wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 197:25]
wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 197:43]
wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 197:80]
wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 197:25]
wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 197:43]
wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 197:80]
wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 197:25]
wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 197:43]
wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 197:80]
wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 197:25]
wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 197:43]
wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 197:80]
wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 197:25]
wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 197:43]
wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 197:80]
wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 197:25]
wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 197:43]
wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 197:80]
wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 197:25]
wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 197:43]
wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 197:80]
wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 197:25]
wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 197:43]
wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 197:80]
wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 197:25]
wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 197:43]
wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 197:80]
wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 197:25]
wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 197:43]
wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 197:80]
wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 197:25]
wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 197:43]
wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 197:80]
wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 197:25]
wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 197:43]
wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 197:80]
wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 197:25]
wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 197:43]
wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 197:80]
wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 197:25]
wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 197:43]
wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 197:80]
wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 197:25]
wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 197:43]
wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 197:80]
wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 197:25]
wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 197:43]
wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 197:80]
wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 197:25]
wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 197:43]
wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 197:80]
wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 197:25]
wire _T_893 = _T_675 & _T_682; // @[el2_lib.scala 198:22]
wire _T_894 = _T_893 & _T_689; // @[el2_lib.scala 198:22]
wire _T_895 = _T_894 & _T_696; // @[el2_lib.scala 198:22]
wire _T_896 = _T_895 & _T_703; // @[el2_lib.scala 198:22]
wire _T_897 = _T_896 & _T_710; // @[el2_lib.scala 198:22]
wire _T_898 = _T_897 & _T_717; // @[el2_lib.scala 198:22]
wire _T_899 = _T_898 & _T_724; // @[el2_lib.scala 198:22]
wire _T_900 = _T_899 & _T_731; // @[el2_lib.scala 198:22]
wire _T_901 = _T_900 & _T_738; // @[el2_lib.scala 198:22]
wire _T_902 = _T_901 & _T_745; // @[el2_lib.scala 198:22]
wire _T_903 = _T_902 & _T_752; // @[el2_lib.scala 198:22]
wire _T_904 = _T_903 & _T_759; // @[el2_lib.scala 198:22]
wire _T_905 = _T_904 & _T_766; // @[el2_lib.scala 198:22]
wire _T_906 = _T_905 & _T_773; // @[el2_lib.scala 198:22]
wire _T_907 = _T_906 & _T_780; // @[el2_lib.scala 198:22]
wire _T_908 = _T_907 & _T_787; // @[el2_lib.scala 198:22]
wire _T_909 = _T_908 & _T_794; // @[el2_lib.scala 198:22]
wire _T_910 = _T_909 & _T_801; // @[el2_lib.scala 198:22]
wire _T_911 = _T_910 & _T_808; // @[el2_lib.scala 198:22]
wire _T_912 = _T_911 & _T_815; // @[el2_lib.scala 198:22]
wire _T_913 = _T_912 & _T_822; // @[el2_lib.scala 198:22]
wire _T_914 = _T_913 & _T_829; // @[el2_lib.scala 198:22]
wire _T_915 = _T_914 & _T_836; // @[el2_lib.scala 198:22]
wire _T_916 = _T_915 & _T_843; // @[el2_lib.scala 198:22]
wire _T_917 = _T_916 & _T_850; // @[el2_lib.scala 198:22]
wire _T_918 = _T_917 & _T_857; // @[el2_lib.scala 198:22]
wire _T_919 = _T_918 & _T_864; // @[el2_lib.scala 198:22]
wire _T_920 = _T_919 & _T_871; // @[el2_lib.scala 198:22]
wire _T_921 = _T_920 & _T_878; // @[el2_lib.scala 198:22]
wire _T_922 = _T_921 & _T_885; // @[el2_lib.scala 198:22]
wire _T_923 = _T_922 & _T_892; // @[el2_lib.scala 198:22]
wire _T_924 = _T_666 & _T_923; // @[el2_lsu_trigger.scala 16:109]
wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_lsu_trigger.scala 16:83]
wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 194:45]
wire _T_929 = ~_T_928; // @[el2_lib.scala 194:39]
wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 194:37]
wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 195:52]
wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 195:41]
wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 197:43]
wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 197:80]
wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 197:25]
wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 197:43]
wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 197:80]
wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 197:25]
wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 197:43]
wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 197:80]
wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 197:25]
wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 197:43]
wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 197:80]
wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 197:25]
wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 197:43]
wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 197:80]
wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 197:25]
wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 197:43]
wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 197:80]
wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 197:25]
wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 197:43]
wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 197:80]
wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 197:25]
wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 197:43]
wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 197:80]
wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 197:25]
wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 197:43]
wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 197:80]
wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 197:25]
wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 197:80]
wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 197:25]
wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 197:80]
wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 197:25]
wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 197:80]
wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 197:25]
wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 197:80]
wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 197:25]
wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 197:80]
wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 197:25]
wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 197:80]
wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 197:25]
wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 197:80]
wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 197:25]
wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 197:80]
wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 197:25]
wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 197:80]
wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 197:25]
wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 197:80]
wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 197:25]
wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 197:80]
wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 197:25]
wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 197:80]
wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 197:25]
wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 197:80]
wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 197:25]
wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 197:80]
wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 197:25]
wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 197:80]
wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 197:25]
wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 197:80]
wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 197:25]
wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 197:80]
wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 197:25]
wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 197:80]
wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 197:25]
wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 197:80]
wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 197:25]
wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 197:80]
wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 197:25]
wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 197:80]
wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 197:25]
wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 197:43]
wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 197:80]
wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 197:25]
wire _T_1152 = _T_934 & _T_941; // @[el2_lib.scala 198:22]
wire _T_1153 = _T_1152 & _T_948; // @[el2_lib.scala 198:22]
wire _T_1154 = _T_1153 & _T_955; // @[el2_lib.scala 198:22]
wire _T_1155 = _T_1154 & _T_962; // @[el2_lib.scala 198:22]
wire _T_1156 = _T_1155 & _T_969; // @[el2_lib.scala 198:22]
wire _T_1157 = _T_1156 & _T_976; // @[el2_lib.scala 198:22]
wire _T_1158 = _T_1157 & _T_983; // @[el2_lib.scala 198:22]
wire _T_1159 = _T_1158 & _T_990; // @[el2_lib.scala 198:22]
wire _T_1160 = _T_1159 & _T_997; // @[el2_lib.scala 198:22]
wire _T_1161 = _T_1160 & _T_1004; // @[el2_lib.scala 198:22]
wire _T_1162 = _T_1161 & _T_1011; // @[el2_lib.scala 198:22]
wire _T_1163 = _T_1162 & _T_1018; // @[el2_lib.scala 198:22]
wire _T_1164 = _T_1163 & _T_1025; // @[el2_lib.scala 198:22]
wire _T_1165 = _T_1164 & _T_1032; // @[el2_lib.scala 198:22]
wire _T_1166 = _T_1165 & _T_1039; // @[el2_lib.scala 198:22]
wire _T_1167 = _T_1166 & _T_1046; // @[el2_lib.scala 198:22]
wire _T_1168 = _T_1167 & _T_1053; // @[el2_lib.scala 198:22]
wire _T_1169 = _T_1168 & _T_1060; // @[el2_lib.scala 198:22]
wire _T_1170 = _T_1169 & _T_1067; // @[el2_lib.scala 198:22]
wire _T_1171 = _T_1170 & _T_1074; // @[el2_lib.scala 198:22]
wire _T_1172 = _T_1171 & _T_1081; // @[el2_lib.scala 198:22]
wire _T_1173 = _T_1172 & _T_1088; // @[el2_lib.scala 198:22]
wire _T_1174 = _T_1173 & _T_1095; // @[el2_lib.scala 198:22]
wire _T_1175 = _T_1174 & _T_1102; // @[el2_lib.scala 198:22]
wire _T_1176 = _T_1175 & _T_1109; // @[el2_lib.scala 198:22]
wire _T_1177 = _T_1176 & _T_1116; // @[el2_lib.scala 198:22]
wire _T_1178 = _T_1177 & _T_1123; // @[el2_lib.scala 198:22]
wire _T_1179 = _T_1178 & _T_1130; // @[el2_lib.scala 198:22]
wire _T_1180 = _T_1179 & _T_1137; // @[el2_lib.scala 198:22]
wire _T_1181 = _T_1180 & _T_1144; // @[el2_lib.scala 198:22]
wire _T_1182 = _T_1181 & _T_1151; // @[el2_lib.scala 198:22]
wire _T_1183 = _T_925 & _T_1182; // @[el2_lsu_trigger.scala 16:109]
wire [2:0] _T_1185 = {_T_1183,_T_924,_T_665}; // @[Cat.scala 29:58]
assign io_dec_i0_trigger_match_d = {_T_1185,_T_406}; // @[el2_lsu_trigger.scala 16:29]
endmodule

239
el2_exu_alu_ctl.anno.json Normal file
View File

@ -0,0 +1,239 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_way",
"sources":[
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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]
},
{
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"sources":[
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]
},
{
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"sources":[
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]
},
{
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]
},
{
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]
},
{
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_boffset",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_boffset"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_hist",
"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
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"sources":[
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]
},
{
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
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]
},
{
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]
},
{
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out",
"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pja",
"sources":[
"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_alu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

474
el2_exu_alu_ctl.fir Normal file
View File

@ -0,0 +1,474 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu_alu_ctl :
module el2_exu_alu_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : UInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}
reg _T : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.enable : @[Reg.scala 28:19]
_T <= io.pc_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.pc_ff <= _T @[el2_exu_alu_ctl.scala 35:12]
wire result : UInt<32>
result <= UInt<1>("h00")
reg _T_1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.enable : @[Reg.scala 28:19]
_T_1 <= result @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.result_ff <= _T_1 @[el2_exu_alu_ctl.scala 37:16]
node _T_2 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29]
node _T_3 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37]
node bm = mux(_T_2, _T_3, io.b_in) @[el2_exu_alu_ctl.scala 39:17]
wire aout : UInt<33>
aout <= UInt<1>("h00")
node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 43:15]
node _T_5 = cat(UInt<1>("h00"), io.a_in) @[Cat.scala 29:58]
node _T_6 = not(io.b_in) @[el2_exu_alu_ctl.scala 43:63]
node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
node _T_8 = add(_T_5, _T_7) @[el2_exu_alu_ctl.scala 43:48]
node _T_9 = tail(_T_8, 1) @[el2_exu_alu_ctl.scala 43:48]
node _T_10 = add(_T_9, UInt<1>("h01")) @[el2_exu_alu_ctl.scala 43:73]
node _T_11 = tail(_T_10, 1) @[el2_exu_alu_ctl.scala 43:73]
node _T_12 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 44:16]
node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 44:5]
node _T_14 = cat(UInt<1>("h00"), io.a_in) @[Cat.scala 29:58]
node _T_15 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58]
node _T_16 = add(_T_14, _T_15) @[el2_exu_alu_ctl.scala 44:48]
node _T_17 = tail(_T_16, 1) @[el2_exu_alu_ctl.scala 44:48]
node _T_18 = mux(_T_4, _T_11, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_13, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = or(_T_18, _T_19) @[Mux.scala 27:72]
wire _T_21 : UInt<33> @[Mux.scala 27:72]
_T_21 <= _T_20 @[Mux.scala 27:72]
aout <= _T_21 @[el2_exu_alu_ctl.scala 42:8]
node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 46:18]
node _T_22 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 48:22]
node _T_23 = not(_T_22) @[el2_exu_alu_ctl.scala 48:14]
node _T_24 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 48:32]
node _T_25 = not(_T_24) @[el2_exu_alu_ctl.scala 48:29]
node _T_26 = and(_T_23, _T_25) @[el2_exu_alu_ctl.scala 48:27]
node _T_27 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 48:44]
node _T_28 = and(_T_26, _T_27) @[el2_exu_alu_ctl.scala 48:37]
node _T_29 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 48:61]
node _T_30 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 48:71]
node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 48:66]
node _T_32 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 48:83]
node _T_33 = not(_T_32) @[el2_exu_alu_ctl.scala 48:78]
node _T_34 = and(_T_31, _T_33) @[el2_exu_alu_ctl.scala 48:76]
node ov = or(_T_28, _T_34) @[el2_exu_alu_ctl.scala 48:50]
node eq = eq(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 50:38]
node ne = not(eq) @[el2_exu_alu_ctl.scala 51:29]
node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 52:34]
node _T_35 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 53:30]
node _T_36 = xor(neg, ov) @[el2_exu_alu_ctl.scala 53:51]
node _T_37 = and(_T_35, _T_36) @[el2_exu_alu_ctl.scala 53:44]
node _T_38 = not(cout) @[el2_exu_alu_ctl.scala 53:78]
node _T_39 = and(io.ap.unsign, _T_38) @[el2_exu_alu_ctl.scala 53:76]
node lt = or(_T_37, _T_39) @[el2_exu_alu_ctl.scala 53:58]
node ge = not(lt) @[el2_exu_alu_ctl.scala 54:29]
node _T_40 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 58:19]
node _T_41 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 59:16]
node _T_42 = and(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 59:39]
node _T_43 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 60:15]
node _T_44 = or(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 60:39]
node _T_45 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 61:16]
node _T_46 = xor(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 61:39]
node _T_47 = mux(_T_40, io.b_in, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_48 = mux(_T_41, _T_42, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_49 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_50 = mux(_T_45, _T_46, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_51 = or(_T_47, _T_48) @[Mux.scala 27:72]
node _T_52 = or(_T_51, _T_49) @[Mux.scala 27:72]
node _T_53 = or(_T_52, _T_50) @[Mux.scala 27:72]
wire lout : UInt<32> @[Mux.scala 27:72]
lout <= _T_53 @[Mux.scala 27:72]
node _T_54 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 64:15]
node _T_55 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 64:60]
node _T_56 = cat(UInt<1>("h00"), _T_55) @[Cat.scala 29:58]
node _T_57 = sub(UInt<6>("h020"), _T_56) @[el2_exu_alu_ctl.scala 64:38]
node _T_58 = tail(_T_57, 1) @[el2_exu_alu_ctl.scala 64:38]
node _T_59 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 65:15]
node _T_60 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 65:60]
node _T_61 = cat(UInt<1>("h00"), _T_60) @[Cat.scala 29:58]
node _T_62 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 66:15]
node _T_63 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:60]
node _T_64 = cat(UInt<1>("h00"), _T_63) @[Cat.scala 29:58]
node _T_65 = mux(_T_54, _T_58, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_59, _T_61, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_62, _T_64, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = or(_T_65, _T_66) @[Mux.scala 27:72]
node _T_69 = or(_T_68, _T_67) @[Mux.scala 27:72]
wire shift_amount : UInt<6> @[Mux.scala 27:72]
shift_amount <= _T_69 @[Mux.scala 27:72]
wire shift_mask : UInt<32>
shift_mask <= UInt<1>("h00")
wire _T_70 : UInt<1>[5] @[el2_lib.scala 178:24]
_T_70[0] <= io.ap.sll @[el2_lib.scala 178:24]
_T_70[1] <= io.ap.sll @[el2_lib.scala 178:24]
_T_70[2] <= io.ap.sll @[el2_lib.scala 178:24]
_T_70[3] <= io.ap.sll @[el2_lib.scala 178:24]
_T_70[4] <= io.ap.sll @[el2_lib.scala 178:24]
node _T_71 = cat(_T_70[0], _T_70[1]) @[Cat.scala 29:58]
node _T_72 = cat(_T_71, _T_70[2]) @[Cat.scala 29:58]
node _T_73 = cat(_T_72, _T_70[3]) @[Cat.scala 29:58]
node _T_74 = cat(_T_73, _T_70[4]) @[Cat.scala 29:58]
node _T_75 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 69:64]
node _T_76 = and(_T_74, _T_75) @[el2_exu_alu_ctl.scala 69:55]
node _T_77 = dshl(UInt<32>("h0ffffffff"), _T_76) @[el2_exu_alu_ctl.scala 69:33]
shift_mask <= _T_77 @[el2_exu_alu_ctl.scala 69:14]
wire shift_extend : UInt<63>
shift_extend <= UInt<1>("h00")
wire _T_78 : UInt<1>[31] @[el2_lib.scala 178:24]
_T_78[0] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[1] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[2] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[3] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[4] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[5] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[6] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[7] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[8] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[9] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[10] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[11] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[12] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[13] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[14] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[15] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[16] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[17] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[18] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[19] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[20] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[21] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[22] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[23] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[24] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[25] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[26] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[27] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[28] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[29] <= io.ap.sra @[el2_lib.scala 178:24]
_T_78[30] <= io.ap.sra @[el2_lib.scala 178:24]
node _T_79 = cat(_T_78[0], _T_78[1]) @[Cat.scala 29:58]
node _T_80 = cat(_T_79, _T_78[2]) @[Cat.scala 29:58]
node _T_81 = cat(_T_80, _T_78[3]) @[Cat.scala 29:58]
node _T_82 = cat(_T_81, _T_78[4]) @[Cat.scala 29:58]
node _T_83 = cat(_T_82, _T_78[5]) @[Cat.scala 29:58]
node _T_84 = cat(_T_83, _T_78[6]) @[Cat.scala 29:58]
node _T_85 = cat(_T_84, _T_78[7]) @[Cat.scala 29:58]
node _T_86 = cat(_T_85, _T_78[8]) @[Cat.scala 29:58]
node _T_87 = cat(_T_86, _T_78[9]) @[Cat.scala 29:58]
node _T_88 = cat(_T_87, _T_78[10]) @[Cat.scala 29:58]
node _T_89 = cat(_T_88, _T_78[11]) @[Cat.scala 29:58]
node _T_90 = cat(_T_89, _T_78[12]) @[Cat.scala 29:58]
node _T_91 = cat(_T_90, _T_78[13]) @[Cat.scala 29:58]
node _T_92 = cat(_T_91, _T_78[14]) @[Cat.scala 29:58]
node _T_93 = cat(_T_92, _T_78[15]) @[Cat.scala 29:58]
node _T_94 = cat(_T_93, _T_78[16]) @[Cat.scala 29:58]
node _T_95 = cat(_T_94, _T_78[17]) @[Cat.scala 29:58]
node _T_96 = cat(_T_95, _T_78[18]) @[Cat.scala 29:58]
node _T_97 = cat(_T_96, _T_78[19]) @[Cat.scala 29:58]
node _T_98 = cat(_T_97, _T_78[20]) @[Cat.scala 29:58]
node _T_99 = cat(_T_98, _T_78[21]) @[Cat.scala 29:58]
node _T_100 = cat(_T_99, _T_78[22]) @[Cat.scala 29:58]
node _T_101 = cat(_T_100, _T_78[23]) @[Cat.scala 29:58]
node _T_102 = cat(_T_101, _T_78[24]) @[Cat.scala 29:58]
node _T_103 = cat(_T_102, _T_78[25]) @[Cat.scala 29:58]
node _T_104 = cat(_T_103, _T_78[26]) @[Cat.scala 29:58]
node _T_105 = cat(_T_104, _T_78[27]) @[Cat.scala 29:58]
node _T_106 = cat(_T_105, _T_78[28]) @[Cat.scala 29:58]
node _T_107 = cat(_T_106, _T_78[29]) @[Cat.scala 29:58]
node _T_108 = cat(_T_107, _T_78[30]) @[Cat.scala 29:58]
node _T_109 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 72:61]
wire _T_110 : UInt<1>[31] @[el2_lib.scala 178:24]
_T_110[0] <= _T_109 @[el2_lib.scala 178:24]
_T_110[1] <= _T_109 @[el2_lib.scala 178:24]
_T_110[2] <= _T_109 @[el2_lib.scala 178:24]
_T_110[3] <= _T_109 @[el2_lib.scala 178:24]
_T_110[4] <= _T_109 @[el2_lib.scala 178:24]
_T_110[5] <= _T_109 @[el2_lib.scala 178:24]
_T_110[6] <= _T_109 @[el2_lib.scala 178:24]
_T_110[7] <= _T_109 @[el2_lib.scala 178:24]
_T_110[8] <= _T_109 @[el2_lib.scala 178:24]
_T_110[9] <= _T_109 @[el2_lib.scala 178:24]
_T_110[10] <= _T_109 @[el2_lib.scala 178:24]
_T_110[11] <= _T_109 @[el2_lib.scala 178:24]
_T_110[12] <= _T_109 @[el2_lib.scala 178:24]
_T_110[13] <= _T_109 @[el2_lib.scala 178:24]
_T_110[14] <= _T_109 @[el2_lib.scala 178:24]
_T_110[15] <= _T_109 @[el2_lib.scala 178:24]
_T_110[16] <= _T_109 @[el2_lib.scala 178:24]
_T_110[17] <= _T_109 @[el2_lib.scala 178:24]
_T_110[18] <= _T_109 @[el2_lib.scala 178:24]
_T_110[19] <= _T_109 @[el2_lib.scala 178:24]
_T_110[20] <= _T_109 @[el2_lib.scala 178:24]
_T_110[21] <= _T_109 @[el2_lib.scala 178:24]
_T_110[22] <= _T_109 @[el2_lib.scala 178:24]
_T_110[23] <= _T_109 @[el2_lib.scala 178:24]
_T_110[24] <= _T_109 @[el2_lib.scala 178:24]
_T_110[25] <= _T_109 @[el2_lib.scala 178:24]
_T_110[26] <= _T_109 @[el2_lib.scala 178:24]
_T_110[27] <= _T_109 @[el2_lib.scala 178:24]
_T_110[28] <= _T_109 @[el2_lib.scala 178:24]
_T_110[29] <= _T_109 @[el2_lib.scala 178:24]
_T_110[30] <= _T_109 @[el2_lib.scala 178:24]
node _T_111 = cat(_T_110[0], _T_110[1]) @[Cat.scala 29:58]
node _T_112 = cat(_T_111, _T_110[2]) @[Cat.scala 29:58]
node _T_113 = cat(_T_112, _T_110[3]) @[Cat.scala 29:58]
node _T_114 = cat(_T_113, _T_110[4]) @[Cat.scala 29:58]
node _T_115 = cat(_T_114, _T_110[5]) @[Cat.scala 29:58]
node _T_116 = cat(_T_115, _T_110[6]) @[Cat.scala 29:58]
node _T_117 = cat(_T_116, _T_110[7]) @[Cat.scala 29:58]
node _T_118 = cat(_T_117, _T_110[8]) @[Cat.scala 29:58]
node _T_119 = cat(_T_118, _T_110[9]) @[Cat.scala 29:58]
node _T_120 = cat(_T_119, _T_110[10]) @[Cat.scala 29:58]
node _T_121 = cat(_T_120, _T_110[11]) @[Cat.scala 29:58]
node _T_122 = cat(_T_121, _T_110[12]) @[Cat.scala 29:58]
node _T_123 = cat(_T_122, _T_110[13]) @[Cat.scala 29:58]
node _T_124 = cat(_T_123, _T_110[14]) @[Cat.scala 29:58]
node _T_125 = cat(_T_124, _T_110[15]) @[Cat.scala 29:58]
node _T_126 = cat(_T_125, _T_110[16]) @[Cat.scala 29:58]
node _T_127 = cat(_T_126, _T_110[17]) @[Cat.scala 29:58]
node _T_128 = cat(_T_127, _T_110[18]) @[Cat.scala 29:58]
node _T_129 = cat(_T_128, _T_110[19]) @[Cat.scala 29:58]
node _T_130 = cat(_T_129, _T_110[20]) @[Cat.scala 29:58]
node _T_131 = cat(_T_130, _T_110[21]) @[Cat.scala 29:58]
node _T_132 = cat(_T_131, _T_110[22]) @[Cat.scala 29:58]
node _T_133 = cat(_T_132, _T_110[23]) @[Cat.scala 29:58]
node _T_134 = cat(_T_133, _T_110[24]) @[Cat.scala 29:58]
node _T_135 = cat(_T_134, _T_110[25]) @[Cat.scala 29:58]
node _T_136 = cat(_T_135, _T_110[26]) @[Cat.scala 29:58]
node _T_137 = cat(_T_136, _T_110[27]) @[Cat.scala 29:58]
node _T_138 = cat(_T_137, _T_110[28]) @[Cat.scala 29:58]
node _T_139 = cat(_T_138, _T_110[29]) @[Cat.scala 29:58]
node _T_140 = cat(_T_139, _T_110[30]) @[Cat.scala 29:58]
node _T_141 = and(_T_108, _T_140) @[el2_exu_alu_ctl.scala 72:44]
wire _T_142 : UInt<1>[31] @[el2_lib.scala 178:24]
_T_142[0] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[1] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[2] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[3] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[4] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[5] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[6] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[7] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[8] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[9] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[10] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[11] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[12] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[13] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[14] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[15] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[16] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[17] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[18] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[19] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[20] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[21] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[22] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[23] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[24] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[25] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[26] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[27] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[28] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[29] <= io.ap.sll @[el2_lib.scala 178:24]
_T_142[30] <= io.ap.sll @[el2_lib.scala 178:24]
node _T_143 = cat(_T_142[0], _T_142[1]) @[Cat.scala 29:58]
node _T_144 = cat(_T_143, _T_142[2]) @[Cat.scala 29:58]
node _T_145 = cat(_T_144, _T_142[3]) @[Cat.scala 29:58]
node _T_146 = cat(_T_145, _T_142[4]) @[Cat.scala 29:58]
node _T_147 = cat(_T_146, _T_142[5]) @[Cat.scala 29:58]
node _T_148 = cat(_T_147, _T_142[6]) @[Cat.scala 29:58]
node _T_149 = cat(_T_148, _T_142[7]) @[Cat.scala 29:58]
node _T_150 = cat(_T_149, _T_142[8]) @[Cat.scala 29:58]
node _T_151 = cat(_T_150, _T_142[9]) @[Cat.scala 29:58]
node _T_152 = cat(_T_151, _T_142[10]) @[Cat.scala 29:58]
node _T_153 = cat(_T_152, _T_142[11]) @[Cat.scala 29:58]
node _T_154 = cat(_T_153, _T_142[12]) @[Cat.scala 29:58]
node _T_155 = cat(_T_154, _T_142[13]) @[Cat.scala 29:58]
node _T_156 = cat(_T_155, _T_142[14]) @[Cat.scala 29:58]
node _T_157 = cat(_T_156, _T_142[15]) @[Cat.scala 29:58]
node _T_158 = cat(_T_157, _T_142[16]) @[Cat.scala 29:58]
node _T_159 = cat(_T_158, _T_142[17]) @[Cat.scala 29:58]
node _T_160 = cat(_T_159, _T_142[18]) @[Cat.scala 29:58]
node _T_161 = cat(_T_160, _T_142[19]) @[Cat.scala 29:58]
node _T_162 = cat(_T_161, _T_142[20]) @[Cat.scala 29:58]
node _T_163 = cat(_T_162, _T_142[21]) @[Cat.scala 29:58]
node _T_164 = cat(_T_163, _T_142[22]) @[Cat.scala 29:58]
node _T_165 = cat(_T_164, _T_142[23]) @[Cat.scala 29:58]
node _T_166 = cat(_T_165, _T_142[24]) @[Cat.scala 29:58]
node _T_167 = cat(_T_166, _T_142[25]) @[Cat.scala 29:58]
node _T_168 = cat(_T_167, _T_142[26]) @[Cat.scala 29:58]
node _T_169 = cat(_T_168, _T_142[27]) @[Cat.scala 29:58]
node _T_170 = cat(_T_169, _T_142[28]) @[Cat.scala 29:58]
node _T_171 = cat(_T_170, _T_142[29]) @[Cat.scala 29:58]
node _T_172 = cat(_T_171, _T_142[30]) @[Cat.scala 29:58]
node _T_173 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 72:99]
node _T_174 = and(_T_172, _T_173) @[el2_exu_alu_ctl.scala 72:90]
node _T_175 = or(_T_141, _T_174) @[el2_exu_alu_ctl.scala 72:68]
node _T_176 = cat(_T_175, io.a_in) @[Cat.scala 29:58]
shift_extend <= _T_176 @[el2_exu_alu_ctl.scala 72:16]
wire shift_long : UInt<63>
shift_long <= UInt<1>("h00")
node _T_177 = dshr(shift_extend, shift_amount) @[el2_exu_alu_ctl.scala 75:32]
shift_long <= _T_177 @[el2_exu_alu_ctl.scala 75:14]
node _T_178 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 77:27]
node _T_179 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 77:46]
node sout = and(_T_178, _T_179) @[el2_exu_alu_ctl.scala 77:34]
node _T_180 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 80:41]
node sel_shift = or(_T_180, io.ap.sra) @[el2_exu_alu_ctl.scala 80:53]
node _T_181 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 81:41]
node _T_182 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 81:56]
node sel_adder = and(_T_181, _T_182) @[el2_exu_alu_ctl.scala 81:54]
node _T_183 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 82:41]
node _T_184 = or(_T_183, io.pp_in.pja) @[el2_exu_alu_ctl.scala 82:58]
node sel_pc = or(_T_184, io.pp_in.pret) @[el2_exu_alu_ctl.scala 82:73]
node _T_185 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 83:47]
node csr_write_data = mux(_T_185, io.b_in, io.a_in) @[el2_exu_alu_ctl.scala 83:32]
node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 85:40]
node _T_186 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_187 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_188 = bits(_T_186, 12, 1) @[el2_lib.scala 201:24]
node _T_189 = bits(_T_187, 12, 1) @[el2_lib.scala 201:40]
node _T_190 = add(_T_188, _T_189) @[el2_lib.scala 201:31]
node _T_191 = bits(_T_186, 31, 13) @[el2_lib.scala 202:20]
node _T_192 = add(_T_191, UInt<1>("h01")) @[el2_lib.scala 202:27]
node _T_193 = tail(_T_192, 1) @[el2_lib.scala 202:27]
node _T_194 = bits(_T_186, 31, 13) @[el2_lib.scala 203:20]
node _T_195 = sub(_T_194, UInt<1>("h01")) @[el2_lib.scala 203:27]
node _T_196 = tail(_T_195, 1) @[el2_lib.scala 203:27]
node _T_197 = bits(_T_187, 12, 12) @[el2_lib.scala 204:22]
node _T_198 = bits(_T_190, 12, 12) @[el2_lib.scala 205:38]
node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_lib.scala 205:27]
node _T_200 = xor(_T_197, _T_199) @[el2_lib.scala 205:25]
node _T_201 = bits(_T_200, 0, 0) @[el2_lib.scala 205:63]
node _T_202 = bits(_T_186, 31, 13) @[el2_lib.scala 205:75]
node _T_203 = eq(_T_197, UInt<1>("h00")) @[el2_lib.scala 206:8]
node _T_204 = bits(_T_190, 12, 12) @[el2_lib.scala 206:26]
node _T_205 = and(_T_203, _T_204) @[el2_lib.scala 206:14]
node _T_206 = bits(_T_205, 0, 0) @[el2_lib.scala 206:51]
node _T_207 = bits(_T_190, 12, 12) @[el2_lib.scala 207:26]
node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_lib.scala 207:15]
node _T_209 = and(_T_197, _T_208) @[el2_lib.scala 207:13]
node _T_210 = bits(_T_209, 0, 0) @[el2_lib.scala 207:51]
node _T_211 = mux(_T_201, _T_202, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_212 = mux(_T_206, _T_193, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_213 = mux(_T_210, _T_196, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_214 = or(_T_211, _T_212) @[Mux.scala 27:72]
node _T_215 = or(_T_214, _T_213) @[Mux.scala 27:72]
wire _T_216 : UInt<19> @[Mux.scala 27:72]
_T_216 <= _T_215 @[Mux.scala 27:72]
node _T_217 = bits(_T_190, 11, 0) @[el2_lib.scala 207:83]
node _T_218 = cat(_T_216, _T_217) @[Cat.scala 29:58]
node pcout = cat(_T_218, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_219 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 91:32]
node _T_220 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 92:15]
node _T_221 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 92:41]
node _T_222 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 93:15]
node _T_223 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 93:41]
node _T_224 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 94:12]
node _T_225 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 95:21]
node _T_226 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 95:51]
node _T_227 = bits(slt_one, 0, 0) @[el2_exu_alu_ctl.scala 96:13]
node _T_228 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58]
node _T_229 = mux(_T_227, _T_228, _T_219) @[Mux.scala 98:16]
node _T_230 = mux(_T_225, _T_226, _T_229) @[Mux.scala 98:16]
node _T_231 = mux(_T_224, pcout, _T_230) @[Mux.scala 98:16]
node _T_232 = mux(_T_222, _T_223, _T_231) @[Mux.scala 98:16]
node _T_233 = mux(_T_220, _T_221, _T_232) @[Mux.scala 98:16]
result <= _T_233 @[el2_exu_alu_ctl.scala 91:16]
node _T_234 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 100:45]
node _T_235 = or(_T_234, io.pp_in.pja) @[el2_exu_alu_ctl.scala 101:20]
node any_jal = or(_T_235, io.pp_in.pret) @[el2_exu_alu_ctl.scala 102:20]
node _T_236 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 105:40]
node _T_237 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 105:59]
node _T_238 = or(_T_236, _T_237) @[el2_exu_alu_ctl.scala 105:46]
node _T_239 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 105:85]
node _T_240 = or(_T_238, _T_239) @[el2_exu_alu_ctl.scala 105:72]
node _T_241 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 105:104]
node _T_242 = or(_T_240, _T_241) @[el2_exu_alu_ctl.scala 105:91]
node actual_taken = or(_T_242, any_jal) @[el2_exu_alu_ctl.scala 105:110]
node _T_243 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 110:42]
node _T_244 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 110:63]
node _T_245 = and(_T_243, _T_244) @[el2_exu_alu_ctl.scala 110:61]
node _T_246 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 110:79]
node _T_247 = and(_T_245, _T_246) @[el2_exu_alu_ctl.scala 110:77]
node _T_248 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 110:104]
node _T_249 = and(_T_248, actual_taken) @[el2_exu_alu_ctl.scala 110:123]
node _T_250 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 110:141]
node _T_251 = and(_T_249, _T_250) @[el2_exu_alu_ctl.scala 110:139]
node _T_252 = or(_T_247, _T_251) @[el2_exu_alu_ctl.scala 110:89]
io.pred_correct_out <= _T_252 @[el2_exu_alu_ctl.scala 110:26]
node _T_253 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 112:37]
node _T_254 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 112:49]
node _T_255 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 112:62]
node _T_256 = mux(_T_253, _T_254, _T_255) @[el2_exu_alu_ctl.scala 112:28]
io.flush_path_out <= _T_256 @[el2_exu_alu_ctl.scala 112:22]
node _T_257 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 115:47]
node _T_258 = and(io.ap.predict_t, _T_257) @[el2_exu_alu_ctl.scala 115:45]
node _T_259 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 115:82]
node cond_mispredict = or(_T_258, _T_259) @[el2_exu_alu_ctl.scala 115:62]
node _T_260 = bits(io.pp_in.prett, 31, 1) @[el2_exu_alu_ctl.scala 118:61]
node _T_261 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 118:76]
node _T_262 = neq(_T_260, _T_261) @[el2_exu_alu_ctl.scala 118:68]
node target_mispredict = and(io.pp_in.pret, _T_262) @[el2_exu_alu_ctl.scala 118:44]
node _T_263 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 120:42]
node _T_264 = or(_T_263, target_mispredict) @[el2_exu_alu_ctl.scala 120:60]
node _T_265 = and(_T_264, io.valid_in) @[el2_exu_alu_ctl.scala 120:81]
node _T_266 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 120:97]
node _T_267 = and(_T_265, _T_266) @[el2_exu_alu_ctl.scala 120:95]
node _T_268 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 120:119]
node _T_269 = and(_T_267, _T_268) @[el2_exu_alu_ctl.scala 120:117]
io.flush_upper_out <= _T_269 @[el2_exu_alu_ctl.scala 120:26]
node _T_270 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 122:42]
node _T_271 = or(_T_270, target_mispredict) @[el2_exu_alu_ctl.scala 122:60]
node _T_272 = and(_T_271, io.valid_in) @[el2_exu_alu_ctl.scala 122:81]
node _T_273 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:97]
node _T_274 = and(_T_272, _T_273) @[el2_exu_alu_ctl.scala 122:95]
node _T_275 = or(_T_274, io.flush_lower_r) @[el2_exu_alu_ctl.scala 122:117]
io.flush_final_out <= _T_275 @[el2_exu_alu_ctl.scala 122:26]
wire newhist : UInt<2>
newhist <= UInt<1>("h00")
node _T_276 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 126:35]
node _T_277 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 126:55]
node _T_278 = and(_T_276, _T_277) @[el2_exu_alu_ctl.scala 126:39]
node _T_279 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 126:77]
node _T_280 = not(_T_279) @[el2_exu_alu_ctl.scala 126:63]
node _T_281 = and(_T_280, actual_taken) @[el2_exu_alu_ctl.scala 126:81]
node _T_282 = or(_T_278, _T_281) @[el2_exu_alu_ctl.scala 126:60]
node _T_283 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 127:20]
node _T_284 = not(_T_283) @[el2_exu_alu_ctl.scala 127:6]
node _T_285 = not(actual_taken) @[el2_exu_alu_ctl.scala 127:26]
node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 127:24]
node _T_287 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 127:58]
node _T_288 = and(_T_287, actual_taken) @[el2_exu_alu_ctl.scala 127:62]
node _T_289 = or(_T_286, _T_288) @[el2_exu_alu_ctl.scala 127:42]
node _T_290 = cat(_T_282, _T_289) @[Cat.scala 29:58]
newhist <= _T_290 @[el2_exu_alu_ctl.scala 126:14]
io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 129:30]
io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 129:30]
node _T_291 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 130:33]
node _T_292 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 130:53]
node _T_293 = and(_T_291, _T_292) @[el2_exu_alu_ctl.scala 130:51]
node _T_294 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 130:90]
node _T_295 = and(_T_293, _T_294) @[el2_exu_alu_ctl.scala 130:71]
io.predict_p_out.misp <= _T_295 @[el2_exu_alu_ctl.scala 130:30]
io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 131:30]
io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 132:30]

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el2_exu_alu_ctl.v Normal file
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@ -0,0 +1,301 @@
module el2_exu_alu_ctl(
input clock,
input reset,
input io_scan_mode,
input io_flush_upper_x,
input io_flush_lower_r,
input io_enable,
input io_valid_in,
input io_ap_land,
input io_ap_lor,
input io_ap_lxor,
input io_ap_sll,
input io_ap_srl,
input io_ap_sra,
input io_ap_beq,
input io_ap_bne,
input io_ap_blt,
input io_ap_bge,
input io_ap_add,
input io_ap_sub,
input io_ap_slt,
input io_ap_unsign,
input io_ap_jal,
input io_ap_predict_t,
input io_ap_predict_nt,
input io_ap_csr_write,
input io_ap_csr_imm,
input io_csr_ren_in,
input [31:0] io_a_in,
input [31:0] io_b_in,
input [30:0] io_pc_in,
input io_pp_in_misp,
input io_pp_in_ataken,
input io_pp_in_boffset,
input io_pp_in_pc4,
input [1:0] io_pp_in_hist,
input [11:0] io_pp_in_toffset,
input io_pp_in_valid,
input io_pp_in_br_error,
input io_pp_in_br_start_error,
input [31:0] io_pp_in_prett,
input io_pp_in_pcall,
input io_pp_in_pret,
input io_pp_in_pja,
input io_pp_in_way,
input [11:0] io_brimm_in,
output [31:0] io_result_ff,
output io_flush_upper_out,
output io_flush_final_out,
output [30:0] io_flush_path_out,
output [30:0] io_pc_ff,
output io_pred_correct_out,
output io_predict_p_out_misp,
output io_predict_p_out_ataken,
output io_predict_p_out_boffset,
output io_predict_p_out_pc4,
output [1:0] io_predict_p_out_hist,
output [11:0] io_predict_p_out_toffset,
output io_predict_p_out_valid,
output io_predict_p_out_br_error,
output io_predict_p_out_br_start_error,
output [31:0] io_predict_p_out_prett,
output io_predict_p_out_pcall,
output io_predict_p_out_pret,
output io_predict_p_out_pja,
output io_predict_p_out_way
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [30:0] _T; // @[Reg.scala 27:20]
reg [31:0] _T_1; // @[Reg.scala 27:20]
wire _T_180 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 80:41]
wire sel_shift = _T_180 | io_ap_sra; // @[el2_exu_alu_ctl.scala 80:53]
wire [9:0] _T_87 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [18:0] _T_96 = {_T_87,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [27:0] _T_105 = {_T_96,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [30:0] _T_108 = {_T_105,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
wire [9:0] _T_119 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [18:0] _T_128 = {_T_119,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [27:0] _T_137 = {_T_128,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_140 = {_T_137,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
wire [30:0] _T_141 = _T_108 & _T_140; // @[el2_exu_alu_ctl.scala 72:44]
wire [4:0] _T_146 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [9:0] _T_151 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [18:0] _T_160 = {_T_151,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [27:0] _T_169 = {_T_160,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_172 = {_T_169,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
wire [30:0] _T_174 = _T_172 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 72:90]
wire [30:0] _T_175 = _T_141 | _T_174; // @[el2_exu_alu_ctl.scala 72:68]
wire [62:0] shift_extend = {_T_175,io_a_in}; // @[Cat.scala 29:58]
wire [5:0] _T_56 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_58 = 6'h20 - _T_56; // @[el2_exu_alu_ctl.scala 64:38]
wire [5:0] _T_65 = io_ap_sll ? _T_58 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_66 = io_ap_srl ? _T_56 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_68 = _T_65 | _T_66; // @[Mux.scala 27:72]
wire [5:0] _T_67 = io_ap_sra ? _T_56 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_68 | _T_67; // @[Mux.scala 27:72]
wire [62:0] shift_long = shift_extend >> shift_amount; // @[el2_exu_alu_ctl.scala 75:32]
wire [4:0] _T_76 = _T_146 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 69:55]
wire [62:0] _T_77 = 63'hffffffff << _T_76; // @[el2_exu_alu_ctl.scala 69:33]
wire [31:0] shift_mask = _T_77[31:0]; // @[el2_exu_alu_ctl.scala 69:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 77:34]
wire _T_181 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 81:41]
wire _T_182 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 81:56]
wire sel_adder = _T_181 & _T_182; // @[el2_exu_alu_ctl.scala 81:54]
wire [32:0] _T_5 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [31:0] _T_6 = ~io_b_in; // @[el2_exu_alu_ctl.scala 43:63]
wire [32:0] _T_7 = {1'h0,_T_6}; // @[Cat.scala 29:58]
wire [32:0] _T_9 = _T_5 + _T_7; // @[el2_exu_alu_ctl.scala 43:48]
wire [32:0] _T_11 = _T_9 + 33'h1; // @[el2_exu_alu_ctl.scala 43:73]
wire [32:0] _T_18 = io_ap_sub ? _T_11 : 33'h0; // @[Mux.scala 27:72]
wire _T_13 = ~io_ap_sub; // @[el2_exu_alu_ctl.scala 44:5]
wire [32:0] _T_15 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_17 = _T_5 + _T_15; // @[el2_exu_alu_ctl.scala 44:48]
wire [32:0] _T_19 = _T_13 ? _T_17 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] aout = _T_18 | _T_19; // @[Mux.scala 27:72]
wire _T_183 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 82:41]
wire _T_184 = _T_183 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 82:58]
wire sel_pc = _T_184 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 82:73]
wire [12:0] _T_187 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_186 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_190 = _T_186[12:1] + _T_187[12:1]; // @[el2_lib.scala 201:31]
wire _T_199 = ~_T_190[12]; // @[el2_lib.scala 205:27]
wire _T_200 = _T_187[12] ^ _T_199; // @[el2_lib.scala 205:25]
wire [18:0] _T_211 = _T_200 ? _T_186[31:13] : 19'h0; // @[Mux.scala 27:72]
wire _T_203 = ~_T_187[12]; // @[el2_lib.scala 206:8]
wire _T_205 = _T_203 & _T_190[12]; // @[el2_lib.scala 206:14]
wire [18:0] _T_193 = _T_186[31:13] + 19'h1; // @[el2_lib.scala 202:27]
wire [18:0] _T_212 = _T_205 ? _T_193 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_214 = _T_211 | _T_212; // @[Mux.scala 27:72]
wire _T_209 = _T_187[12] & _T_199; // @[el2_lib.scala 207:13]
wire [18:0] _T_196 = _T_186[31:13] - 19'h1; // @[el2_lib.scala 203:27]
wire [18:0] _T_213 = _T_209 ? _T_196 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_215 = _T_214 | _T_213; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_215,_T_190[11:0],1'h0}; // @[Cat.scala 29:58]
wire _T_35 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 53:30]
wire neg = aout[31]; // @[el2_exu_alu_ctl.scala 52:34]
wire _T_23 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 48:14]
wire [31:0] bm = io_ap_sub ? _T_6 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
wire _T_25 = ~bm[31]; // @[el2_exu_alu_ctl.scala 48:29]
wire _T_26 = _T_23 & _T_25; // @[el2_exu_alu_ctl.scala 48:27]
wire _T_28 = _T_26 & neg; // @[el2_exu_alu_ctl.scala 48:37]
wire _T_31 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 48:66]
wire _T_33 = ~neg; // @[el2_exu_alu_ctl.scala 48:78]
wire _T_34 = _T_31 & _T_33; // @[el2_exu_alu_ctl.scala 48:76]
wire ov = _T_28 | _T_34; // @[el2_exu_alu_ctl.scala 48:50]
wire _T_36 = neg ^ ov; // @[el2_exu_alu_ctl.scala 53:51]
wire _T_37 = _T_35 & _T_36; // @[el2_exu_alu_ctl.scala 53:44]
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 46:18]
wire _T_38 = ~cout; // @[el2_exu_alu_ctl.scala 53:78]
wire _T_39 = io_ap_unsign & _T_38; // @[el2_exu_alu_ctl.scala 53:76]
wire lt = _T_37 | _T_39; // @[el2_exu_alu_ctl.scala 53:58]
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 85:40]
wire [31:0] _T_228 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_47 = io_csr_ren_in ? io_b_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_42 = io_a_in & io_b_in; // @[el2_exu_alu_ctl.scala 59:39]
wire [31:0] _T_48 = io_ap_land ? _T_42 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_51 = _T_47 | _T_48; // @[Mux.scala 27:72]
wire [31:0] _T_44 = io_a_in | io_b_in; // @[el2_exu_alu_ctl.scala 60:39]
wire [31:0] _T_49 = io_ap_lor ? _T_44 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_52 = _T_51 | _T_49; // @[Mux.scala 27:72]
wire [31:0] _T_46 = io_a_in ^ io_b_in; // @[el2_exu_alu_ctl.scala 61:39]
wire [31:0] _T_50 = io_ap_lxor ? _T_46 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] lout = _T_52 | _T_50; // @[Mux.scala 27:72]
wire eq = io_a_in == io_b_in; // @[el2_exu_alu_ctl.scala 50:38]
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 51:29]
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 54:29]
wire _T_236 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 105:40]
wire _T_237 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 105:59]
wire _T_238 = _T_236 | _T_237; // @[el2_exu_alu_ctl.scala 105:46]
wire _T_239 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 105:85]
wire _T_240 = _T_238 | _T_239; // @[el2_exu_alu_ctl.scala 105:72]
wire _T_241 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 105:104]
wire _T_242 = _T_240 | _T_241; // @[el2_exu_alu_ctl.scala 105:91]
wire actual_taken = _T_242 | sel_pc; // @[el2_exu_alu_ctl.scala 105:110]
wire _T_243 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 110:42]
wire _T_244 = ~actual_taken; // @[el2_exu_alu_ctl.scala 110:63]
wire _T_245 = _T_243 & _T_244; // @[el2_exu_alu_ctl.scala 110:61]
wire _T_246 = ~sel_pc; // @[el2_exu_alu_ctl.scala 110:79]
wire _T_247 = _T_245 & _T_246; // @[el2_exu_alu_ctl.scala 110:77]
wire _T_248 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 110:104]
wire _T_249 = _T_248 & actual_taken; // @[el2_exu_alu_ctl.scala 110:123]
wire _T_251 = _T_249 & _T_246; // @[el2_exu_alu_ctl.scala 110:139]
wire _T_258 = io_ap_predict_t & _T_244; // @[el2_exu_alu_ctl.scala 115:45]
wire _T_259 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 115:82]
wire cond_mispredict = _T_258 | _T_259; // @[el2_exu_alu_ctl.scala 115:62]
wire _T_262 = io_pp_in_prett[31:1] != aout[31:1]; // @[el2_exu_alu_ctl.scala 118:68]
wire target_mispredict = io_pp_in_pret & _T_262; // @[el2_exu_alu_ctl.scala 118:44]
wire _T_263 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 120:42]
wire _T_264 = _T_263 | target_mispredict; // @[el2_exu_alu_ctl.scala 120:60]
wire _T_265 = _T_264 & io_valid_in; // @[el2_exu_alu_ctl.scala 120:81]
wire _T_266 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 120:97]
wire _T_267 = _T_265 & _T_266; // @[el2_exu_alu_ctl.scala 120:95]
wire _T_268 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 120:119]
wire _T_278 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 126:39]
wire _T_280 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 126:63]
wire _T_281 = _T_280 & actual_taken; // @[el2_exu_alu_ctl.scala 126:81]
wire _T_282 = _T_278 | _T_281; // @[el2_exu_alu_ctl.scala 126:60]
wire _T_284 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 127:6]
wire _T_286 = _T_284 & _T_244; // @[el2_exu_alu_ctl.scala 127:24]
wire _T_288 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 127:62]
wire _T_289 = _T_286 | _T_288; // @[el2_exu_alu_ctl.scala 127:42]
wire _T_293 = _T_266 & _T_268; // @[el2_exu_alu_ctl.scala 130:51]
wire _T_294 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 130:90]
assign io_result_ff = _T_1; // @[el2_exu_alu_ctl.scala 37:16]
assign io_flush_upper_out = _T_267 & _T_268; // @[el2_exu_alu_ctl.scala 120:26]
assign io_flush_final_out = _T_267 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 122:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 112:22]
assign io_pc_ff = _T; // @[el2_exu_alu_ctl.scala 35:12]
assign io_pred_correct_out = _T_247 | _T_251; // @[el2_exu_alu_ctl.scala 110:26]
assign io_predict_p_out_misp = _T_293 & _T_294; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 130:30]
assign io_predict_p_out_ataken = _T_242 | sel_pc; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 131:30]
assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_hist = {_T_282,_T_289}; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 132:30]
assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 129:30]
assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 129:30]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
_T_1 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
_T <= 31'h0;
end else if (io_enable) begin
_T <= io_pc_in;
end
if (reset) begin
_T_1 <= 32'h0;
end else if (io_enable) begin
if (sel_shift) begin
_T_1 <= sout;
end else if (sel_adder) begin
_T_1 <= aout[31:0];
end else if (sel_pc) begin
_T_1 <= pcout;
end else if (io_ap_csr_write) begin
if (io_ap_csr_imm) begin
_T_1 <= io_b_in;
end else begin
_T_1 <= io_a_in;
end
end else if (slt_one) begin
_T_1 <= _T_228;
end else begin
_T_1 <= lout;
end
end
end
endmodule

25
el2_exu_div_ctl.anno.json Normal file
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@ -0,0 +1,25 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_ctl|el2_exu_div_ctl>io_finish_dly",
"sources":[
"~el2_exu_div_ctl|el2_exu_div_ctl>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_div_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1782
el2_exu_div_ctl.fir Normal file
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File diff suppressed because it is too large Load Diff

790
el2_exu_div_ctl.v Normal file
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@ -0,0 +1,790 @@
module el2_exu_div_ctl(
input clock,
input reset,
input io_scan_mode,
input io_dp_valid,
input io_dp_unsign,
input io_dp_rem,
input [31:0] io_dividend,
input [31:0] io_divisor,
input io_cancel,
output [31:0] io_out,
output io_finish_dly
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 56:30]
reg valid_ff_x; // @[Reg.scala 27:20]
wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 56:28]
reg [32:0] q_ff; // @[Reg.scala 27:20]
wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 62:33]
reg [32:0] m_ff; // @[Reg.scala 27:20]
wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 62:56]
wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 62:42]
wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 62:79]
wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 62:65]
reg rem_ff; // @[Reg.scala 27:20]
wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 62:90]
wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 62:88]
wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 62:98]
wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 63:16]
wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 63:25]
wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 63:48]
wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 63:58]
wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 62:109]
wire pat1 = q_ff[3]; // @[el2_exu_div_ctl.scala 66:57]
wire _T_22 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 67:69]
wire _T_24 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 67:69]
wire _T_26 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 67:69]
wire _T_27 = _T_22 & _T_24; // @[el2_exu_div_ctl.scala 67:94]
wire pat2 = _T_27 & _T_26; // @[el2_exu_div_ctl.scala 67:94]
wire _T_28 = pat1 & pat2; // @[el2_exu_div_ctl.scala 68:10]
wire _T_33 = pat1 & _T_27; // @[el2_exu_div_ctl.scala 68:10]
wire _T_35 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 74:45]
wire _T_36 = _T_33 & _T_35; // @[el2_exu_div_ctl.scala 74:43]
wire pat1_2 = q_ff[2]; // @[el2_exu_div_ctl.scala 66:57]
wire _T_44 = pat1_2 & pat2; // @[el2_exu_div_ctl.scala 68:10]
wire _T_45 = _T_36 | _T_44; // @[el2_exu_div_ctl.scala 74:54]
wire pat1_3 = pat1 & pat1_2; // @[el2_exu_div_ctl.scala 66:94]
wire _T_52 = pat1_3 & _T_27; // @[el2_exu_div_ctl.scala 68:10]
wire _T_53 = _T_45 | _T_52; // @[el2_exu_div_ctl.scala 74:86]
wire _T_58 = pat1_2 & _T_27; // @[el2_exu_div_ctl.scala 68:10]
wire _T_61 = _T_58 & _T_35; // @[el2_exu_div_ctl.scala 76:43]
wire pat1_5 = q_ff[1]; // @[el2_exu_div_ctl.scala 66:57]
wire _T_69 = pat1_5 & pat2; // @[el2_exu_div_ctl.scala 68:10]
wire _T_70 = _T_61 | _T_69; // @[el2_exu_div_ctl.scala 76:54]
wire pat2_6 = _T_22 & _T_26; // @[el2_exu_div_ctl.scala 67:94]
wire _T_75 = pat1 & pat2_6; // @[el2_exu_div_ctl.scala 68:10]
wire _T_78 = _T_75 & _T_35; // @[el2_exu_div_ctl.scala 76:116]
wire _T_79 = _T_70 | _T_78; // @[el2_exu_div_ctl.scala 76:89]
wire _T_82 = ~pat1_2; // @[el2_exu_div_ctl.scala 66:69]
wire pat1_7 = pat1 & _T_82; // @[el2_exu_div_ctl.scala 66:94]
wire _T_90 = _T_27 & m_ff[1]; // @[el2_exu_div_ctl.scala 67:94]
wire pat2_7 = _T_90 & m_ff[0]; // @[el2_exu_div_ctl.scala 67:94]
wire _T_91 = pat1_7 & pat2_7; // @[el2_exu_div_ctl.scala 68:10]
wire _T_92 = _T_79 | _T_91; // @[el2_exu_div_ctl.scala 76:127]
wire _T_94 = ~pat1; // @[el2_exu_div_ctl.scala 66:69]
wire _T_97 = _T_94 & pat1_2; // @[el2_exu_div_ctl.scala 66:94]
wire pat1_8 = _T_97 & pat1_5; // @[el2_exu_div_ctl.scala 66:94]
wire _T_102 = pat1_8 & _T_27; // @[el2_exu_div_ctl.scala 68:10]
wire _T_103 = _T_92 | _T_102; // @[el2_exu_div_ctl.scala 77:54]
wire _T_107 = pat1_3 & _T_22; // @[el2_exu_div_ctl.scala 68:10]
wire _T_110 = _T_107 & _T_35; // @[el2_exu_div_ctl.scala 77:115]
wire _T_111 = _T_103 | _T_110; // @[el2_exu_div_ctl.scala 77:89]
wire _T_119 = _T_22 & m_ff[2]; // @[el2_exu_div_ctl.scala 67:94]
wire pat2_10 = _T_119 & _T_26; // @[el2_exu_div_ctl.scala 67:94]
wire _T_120 = pat1_3 & pat2_10; // @[el2_exu_div_ctl.scala 68:10]
wire _T_121 = _T_111 | _T_120; // @[el2_exu_div_ctl.scala 77:127]
wire pat1_11 = pat1 & pat1_5; // @[el2_exu_div_ctl.scala 66:94]
wire _T_128 = pat1_11 & pat2_6; // @[el2_exu_div_ctl.scala 68:10]
wire _T_129 = _T_121 | _T_128; // @[el2_exu_div_ctl.scala 78:54]
wire pat1_12 = pat1_3 & pat1_5; // @[el2_exu_div_ctl.scala 66:94]
wire _T_137 = pat1_12 & _T_119; // @[el2_exu_div_ctl.scala 68:10]
wire _T_138 = _T_129 | _T_137; // @[el2_exu_div_ctl.scala 78:88]
wire _T_142 = pat1_2 & pat1_5; // @[el2_exu_div_ctl.scala 66:94]
wire pat1_13 = _T_142 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_147 = pat1_13 & pat2_6; // @[el2_exu_div_ctl.scala 68:10]
wire pat1_14 = pat1_7 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_157 = _T_22 & m_ff[1]; // @[el2_exu_div_ctl.scala 67:94]
wire pat2_14 = _T_157 & m_ff[0]; // @[el2_exu_div_ctl.scala 67:94]
wire _T_158 = pat1_14 & pat2_14; // @[el2_exu_div_ctl.scala 68:10]
wire _T_159 = _T_147 | _T_158; // @[el2_exu_div_ctl.scala 80:57]
wire _T_164 = pat1_2 & pat2_6; // @[el2_exu_div_ctl.scala 68:10]
wire _T_167 = _T_164 & _T_35; // @[el2_exu_div_ctl.scala 80:124]
wire _T_168 = _T_159 | _T_167; // @[el2_exu_div_ctl.scala 80:97]
wire _T_173 = pat1_5 & _T_27; // @[el2_exu_div_ctl.scala 68:10]
wire _T_176 = _T_173 & _T_35; // @[el2_exu_div_ctl.scala 81:43]
wire _T_177 = _T_168 | _T_176; // @[el2_exu_div_ctl.scala 80:139]
wire _T_185 = q_ff[0] & pat2; // @[el2_exu_div_ctl.scala 68:10]
wire _T_186 = _T_177 | _T_185; // @[el2_exu_div_ctl.scala 81:57]
wire _T_191 = ~pat1_5; // @[el2_exu_div_ctl.scala 66:69]
wire pat1_18 = _T_97 & _T_191; // @[el2_exu_div_ctl.scala 66:94]
wire _T_201 = pat1_18 & pat2_7; // @[el2_exu_div_ctl.scala 68:10]
wire _T_202 = _T_186 | _T_201; // @[el2_exu_div_ctl.scala 81:97]
wire _T_209 = pat1_8 & _T_22; // @[el2_exu_div_ctl.scala 68:10]
wire _T_212 = _T_209 & _T_35; // @[el2_exu_div_ctl.scala 82:46]
wire _T_213 = _T_202 | _T_212; // @[el2_exu_div_ctl.scala 81:139]
wire pat2_20 = _T_24 & _T_26; // @[el2_exu_div_ctl.scala 67:94]
wire _T_218 = pat1 & pat2_20; // @[el2_exu_div_ctl.scala 68:10]
wire _T_221 = _T_218 & _T_35; // @[el2_exu_div_ctl.scala 82:85]
wire _T_222 = _T_213 | _T_221; // @[el2_exu_div_ctl.scala 82:57]
wire pat2_21 = _T_119 & m_ff[1]; // @[el2_exu_div_ctl.scala 67:94]
wire _T_231 = pat1_7 & pat2_21; // @[el2_exu_div_ctl.scala 68:10]
wire _T_232 = _T_222 | _T_231; // @[el2_exu_div_ctl.scala 82:97]
wire _T_244 = pat1_8 & pat2_10; // @[el2_exu_div_ctl.scala 68:10]
wire _T_245 = _T_232 | _T_244; // @[el2_exu_div_ctl.scala 82:139]
wire pat1_23 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_255 = pat1_23 & pat2_6; // @[el2_exu_div_ctl.scala 68:10]
wire _T_256 = _T_245 | _T_255; // @[el2_exu_div_ctl.scala 83:57]
wire pat1_24 = pat1_7 & _T_191; // @[el2_exu_div_ctl.scala 66:94]
wire pat2_24 = _T_119 & m_ff[0]; // @[el2_exu_div_ctl.scala 67:94]
wire _T_268 = pat1_24 & pat2_24; // @[el2_exu_div_ctl.scala 68:10]
wire _T_269 = _T_256 | _T_268; // @[el2_exu_div_ctl.scala 83:97]
wire _T_274 = _T_82 & pat1_5; // @[el2_exu_div_ctl.scala 66:94]
wire pat1_25 = _T_274 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_279 = pat1_25 & _T_27; // @[el2_exu_div_ctl.scala 68:10]
wire _T_280 = _T_269 | _T_279; // @[el2_exu_div_ctl.scala 83:139]
wire _T_284 = pat1_3 & _T_26; // @[el2_exu_div_ctl.scala 68:10]
wire _T_287 = _T_284 & _T_35; // @[el2_exu_div_ctl.scala 84:84]
wire _T_288 = _T_280 | _T_287; // @[el2_exu_div_ctl.scala 84:57]
wire pat1_27 = pat1_8 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_299 = pat1_27 & _T_119; // @[el2_exu_div_ctl.scala 68:10]
wire _T_300 = _T_288 | _T_299; // @[el2_exu_div_ctl.scala 84:97]
wire pat2_28 = m_ff[3] & _T_24; // @[el2_exu_div_ctl.scala 67:94]
wire _T_306 = pat1_3 & pat2_28; // @[el2_exu_div_ctl.scala 68:10]
wire _T_307 = _T_300 | _T_306; // @[el2_exu_div_ctl.scala 84:139]
wire pat2_29 = pat2_28 & _T_26; // @[el2_exu_div_ctl.scala 67:94]
wire _T_316 = pat1_11 & pat2_29; // @[el2_exu_div_ctl.scala 68:10]
wire _T_317 = _T_307 | _T_316; // @[el2_exu_div_ctl.scala 85:57]
wire pat1_30 = pat1 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_324 = pat1_30 & pat2_20; // @[el2_exu_div_ctl.scala 68:10]
wire _T_325 = _T_317 | _T_324; // @[el2_exu_div_ctl.scala 85:97]
wire pat1_31 = pat1 & _T_191; // @[el2_exu_div_ctl.scala 66:94]
wire pat2_31 = pat2_21 & m_ff[0]; // @[el2_exu_div_ctl.scala 67:94]
wire _T_336 = pat1_31 & pat2_31; // @[el2_exu_div_ctl.scala 68:10]
wire _T_337 = _T_325 | _T_336; // @[el2_exu_div_ctl.scala 85:139]
wire _T_342 = pat1_12 & m_ff[3]; // @[el2_exu_div_ctl.scala 68:10]
wire _T_345 = _T_342 & _T_35; // @[el2_exu_div_ctl.scala 86:86]
wire _T_346 = _T_337 | _T_345; // @[el2_exu_div_ctl.scala 86:57]
wire pat2_33 = m_ff[3] & _T_26; // @[el2_exu_div_ctl.scala 67:94]
wire _T_354 = pat1_12 & pat2_33; // @[el2_exu_div_ctl.scala 68:10]
wire _T_355 = _T_346 | _T_354; // @[el2_exu_div_ctl.scala 86:97]
wire pat1_34 = pat1_3 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_363 = pat1_34 & pat2_33; // @[el2_exu_div_ctl.scala 68:10]
wire _T_364 = _T_355 | _T_363; // @[el2_exu_div_ctl.scala 86:139]
wire pat1_35 = pat1_7 & pat1_5; // @[el2_exu_div_ctl.scala 66:94]
wire _T_373 = pat1_35 & _T_157; // @[el2_exu_div_ctl.scala 68:10]
wire _T_374 = _T_364 | _T_373; // @[el2_exu_div_ctl.scala 87:57]
wire pat1_36 = pat1_11 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_380 = pat1_36 & _T_24; // @[el2_exu_div_ctl.scala 68:10]
wire _T_381 = _T_374 | _T_380; // @[el2_exu_div_ctl.scala 87:97]
wire pat1_37 = pat1_12 & q_ff[0]; // @[el2_exu_div_ctl.scala 66:94]
wire _T_388 = pat1_37 & m_ff[3]; // @[el2_exu_div_ctl.scala 68:10]
wire _T_389 = _T_381 | _T_388; // @[el2_exu_div_ctl.scala 87:139]
wire _T_393 = pat1_11 & _T_24; // @[el2_exu_div_ctl.scala 68:10]
wire _T_396 = _T_393 & _T_35; // @[el2_exu_div_ctl.scala 88:83]
wire _T_397 = _T_389 | _T_396; // @[el2_exu_div_ctl.scala 88:57]
wire [3:0] smallnum = {_T_28,_T_53,_T_138,_T_397}; // @[Cat.scala 29:58]
reg sign_ff; // @[Reg.scala 27:20]
wire _T_401 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 98:34]
wire [32:0] short_dividend = {_T_401,q_ff[31:0]}; // @[Cat.scala 29:58]
wire _T_406 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 103:7]
wire _T_409 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 103:60]
wire _T_414 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 104:59]
wire _T_415 = _T_406 & _T_409; // @[Mux.scala 27:72]
wire _T_416 = short_dividend[32] & _T_414; // @[Mux.scala 27:72]
wire _T_417 = _T_415 | _T_416; // @[Mux.scala 27:72]
wire _T_424 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 107:60]
wire _T_429 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 108:59]
wire _T_430 = _T_406 & _T_424; // @[Mux.scala 27:72]
wire _T_431 = short_dividend[32] & _T_429; // @[Mux.scala 27:72]
wire _T_432 = _T_430 | _T_431; // @[Mux.scala 27:72]
wire _T_439 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 111:59]
wire _T_444 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 112:58]
wire _T_445 = _T_406 & _T_439; // @[Mux.scala 27:72]
wire _T_446 = short_dividend[32] & _T_444; // @[Mux.scala 27:72]
wire _T_447 = _T_445 | _T_446; // @[Mux.scala 27:72]
wire [2:0] a_cls = {_T_417,_T_432,_T_447}; // @[Cat.scala 29:58]
wire _T_452 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 117:7]
wire _T_455 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 117:40]
wire _T_460 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 118:39]
wire _T_461 = _T_452 & _T_455; // @[Mux.scala 27:72]
wire _T_462 = m_ff[32] & _T_460; // @[Mux.scala 27:72]
wire _T_463 = _T_461 | _T_462; // @[Mux.scala 27:72]
wire _T_470 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 121:40]
wire _T_475 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 122:39]
wire _T_476 = _T_452 & _T_470; // @[Mux.scala 27:72]
wire _T_477 = m_ff[32] & _T_475; // @[Mux.scala 27:72]
wire _T_478 = _T_476 | _T_477; // @[Mux.scala 27:72]
wire _T_485 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 125:39]
wire _T_490 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 126:38]
wire _T_491 = _T_452 & _T_485; // @[Mux.scala 27:72]
wire _T_492 = m_ff[32] & _T_490; // @[Mux.scala 27:72]
wire _T_493 = _T_491 | _T_492; // @[Mux.scala 27:72]
wire [2:0] b_cls = {_T_463,_T_478,_T_493}; // @[Cat.scala 29:58]
wire _T_497 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 130:19]
wire _T_500 = _T_497 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:34]
wire _T_502 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 131:21]
wire _T_505 = _T_502 & b_cls[2]; // @[el2_exu_div_ctl.scala 131:36]
wire _T_506 = _T_500 | _T_505; // @[el2_exu_div_ctl.scala 130:65]
wire _T_508 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 132:21]
wire _T_511 = _T_508 & b_cls[2]; // @[el2_exu_div_ctl.scala 132:36]
wire _T_512 = _T_506 | _T_511; // @[el2_exu_div_ctl.scala 131:67]
wire _T_516 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 133:50]
wire _T_517 = _T_502 & _T_516; // @[el2_exu_div_ctl.scala 133:36]
wire _T_518 = _T_512 | _T_517; // @[el2_exu_div_ctl.scala 132:67]
wire _T_523 = _T_508 & _T_516; // @[el2_exu_div_ctl.scala 134:36]
wire _T_524 = _T_518 | _T_523; // @[el2_exu_div_ctl.scala 133:67]
wire _T_528 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 135:50]
wire _T_529 = _T_508 & _T_528; // @[el2_exu_div_ctl.scala 135:36]
wire _T_530 = _T_524 | _T_529; // @[el2_exu_div_ctl.scala 134:67]
wire _T_535 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 137:36]
wire _T_540 = _T_497 & _T_516; // @[el2_exu_div_ctl.scala 138:36]
wire _T_541 = _T_535 | _T_540; // @[el2_exu_div_ctl.scala 137:67]
wire _T_546 = _T_502 & _T_528; // @[el2_exu_div_ctl.scala 139:36]
wire _T_547 = _T_541 | _T_546; // @[el2_exu_div_ctl.scala 138:67]
wire _T_551 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 140:50]
wire _T_552 = _T_508 & _T_551; // @[el2_exu_div_ctl.scala 140:36]
wire _T_553 = _T_547 | _T_552; // @[el2_exu_div_ctl.scala 139:67]
wire _T_558 = a_cls[2] & _T_516; // @[el2_exu_div_ctl.scala 142:36]
wire _T_563 = _T_497 & _T_528; // @[el2_exu_div_ctl.scala 143:36]
wire _T_564 = _T_558 | _T_563; // @[el2_exu_div_ctl.scala 142:67]
wire _T_569 = _T_502 & _T_551; // @[el2_exu_div_ctl.scala 144:36]
wire _T_570 = _T_564 | _T_569; // @[el2_exu_div_ctl.scala 143:67]
wire _T_575 = a_cls[2] & _T_528; // @[el2_exu_div_ctl.scala 146:36]
wire _T_580 = _T_497 & _T_551; // @[el2_exu_div_ctl.scala 147:36]
wire _T_581 = _T_575 | _T_580; // @[el2_exu_div_ctl.scala 146:67]
wire [3:0] shortq_raw = {_T_530,_T_553,_T_570,_T_581}; // @[Cat.scala 29:58]
wire _T_586 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 150:35]
wire _T_587 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 150:78]
wire shortq_enable = _T_586 & _T_587; // @[el2_exu_div_ctl.scala 150:64]
wire [3:0] _T_589 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] shortq_shift = _T_589 & shortq_raw; // @[el2_exu_div_ctl.scala 151:44]
reg [3:0] shortq_shift_xx; // @[Reg.scala 27:20]
wire [4:0] _T_598 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_599 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_600 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [3:0] _T_601 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_602 = _T_598 | _T_599; // @[Mux.scala 27:72]
wire [4:0] _T_603 = _T_602 | _T_600; // @[Mux.scala 27:72]
wire [4:0] _GEN_15 = {{1'd0}, _T_601}; // @[Mux.scala 27:72]
wire [4:0] shortq_shift_ff = _T_603 | _GEN_15; // @[Mux.scala 27:72]
reg [5:0] count; // @[Reg.scala 27:20]
wire _T_606 = count == 6'h20; // @[el2_exu_div_ctl.scala 164:55]
wire _T_607 = count == 6'h21; // @[el2_exu_div_ctl.scala 164:76]
wire _T_608 = _T_9 ? _T_606 : _T_607; // @[el2_exu_div_ctl.scala 164:39]
wire finish = smallnum_case | _T_608; // @[el2_exu_div_ctl.scala 164:34]
reg run_state; // @[Reg.scala 27:20]
wire _T_609 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 165:32]
wire _T_610 = _T_609 | finish; // @[el2_exu_div_ctl.scala 165:44]
reg finish_ff; // @[Reg.scala 27:20]
wire div_clken = _T_610 | finish_ff; // @[el2_exu_div_ctl.scala 165:53]
wire _T_612 = ~finish; // @[el2_exu_div_ctl.scala 166:48]
wire _T_613 = _T_609 & _T_612; // @[el2_exu_div_ctl.scala 166:46]
wire run_in = _T_613 & _T; // @[el2_exu_div_ctl.scala 166:56]
wire _T_616 = run_state & _T_612; // @[el2_exu_div_ctl.scala 167:35]
wire _T_618 = _T_616 & _T; // @[el2_exu_div_ctl.scala 167:45]
wire _T_619 = ~shortq_enable; // @[el2_exu_div_ctl.scala 167:60]
wire _T_620 = _T_618 & _T_619; // @[el2_exu_div_ctl.scala 167:58]
wire [5:0] _T_622 = _T_620 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [5:0] _T_623 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [5:0] _T_625 = count + _T_623; // @[el2_exu_div_ctl.scala 167:86]
wire [5:0] _T_627 = _T_625 + 6'h1; // @[el2_exu_div_ctl.scala 167:113]
wire [5:0] count_in = _T_622 & _T_627; // @[el2_exu_div_ctl.scala 167:77]
wire _T_631 = ~io_dp_unsign; // @[el2_exu_div_ctl.scala 171:20]
wire _T_632 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 171:48]
wire sign_eff = _T_631 & _T_632; // @[el2_exu_div_ctl.scala 171:34]
wire _T_633 = ~run_state; // @[el2_exu_div_ctl.scala 175:6]
wire [32:0] _T_635 = {1'h0,io_dividend}; // @[Cat.scala 29:58]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire _T_636 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 176:30]
wire _T_637 = run_state & _T_636; // @[el2_exu_div_ctl.scala 176:16]
reg dividend_neg_ff; // @[Reg.scala 27:20]
wire _T_660 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 180:32]
wire _T_845 = |q_ff[30:0]; // @[el2_lib.scala 234:32]
wire _T_847 = ~q_ff[31]; // @[el2_lib.scala 235:32]
wire _T_849 = _T_845 ? _T_847 : q_ff[31]; // @[el2_lib.scala 235:25]
wire _T_839 = |q_ff[29:0]; // @[el2_lib.scala 234:32]
wire _T_841 = ~q_ff[30]; // @[el2_lib.scala 235:32]
wire _T_843 = _T_839 ? _T_841 : q_ff[30]; // @[el2_lib.scala 235:25]
wire _T_833 = |q_ff[28:0]; // @[el2_lib.scala 234:32]
wire _T_835 = ~q_ff[29]; // @[el2_lib.scala 235:32]
wire _T_837 = _T_833 ? _T_835 : q_ff[29]; // @[el2_lib.scala 235:25]
wire _T_827 = |q_ff[27:0]; // @[el2_lib.scala 234:32]
wire _T_829 = ~q_ff[28]; // @[el2_lib.scala 235:32]
wire _T_831 = _T_827 ? _T_829 : q_ff[28]; // @[el2_lib.scala 235:25]
wire _T_821 = |q_ff[26:0]; // @[el2_lib.scala 234:32]
wire _T_823 = ~q_ff[27]; // @[el2_lib.scala 235:32]
wire _T_825 = _T_821 ? _T_823 : q_ff[27]; // @[el2_lib.scala 235:25]
wire _T_815 = |q_ff[25:0]; // @[el2_lib.scala 234:32]
wire _T_817 = ~q_ff[26]; // @[el2_lib.scala 235:32]
wire _T_819 = _T_815 ? _T_817 : q_ff[26]; // @[el2_lib.scala 235:25]
wire _T_809 = |q_ff[24:0]; // @[el2_lib.scala 234:32]
wire _T_811 = ~q_ff[25]; // @[el2_lib.scala 235:32]
wire _T_813 = _T_809 ? _T_811 : q_ff[25]; // @[el2_lib.scala 235:25]
wire _T_803 = |q_ff[23:0]; // @[el2_lib.scala 234:32]
wire _T_805 = ~q_ff[24]; // @[el2_lib.scala 235:32]
wire _T_807 = _T_803 ? _T_805 : q_ff[24]; // @[el2_lib.scala 235:25]
wire _T_797 = |q_ff[22:0]; // @[el2_lib.scala 234:32]
wire _T_799 = ~q_ff[23]; // @[el2_lib.scala 235:32]
wire _T_801 = _T_797 ? _T_799 : q_ff[23]; // @[el2_lib.scala 235:25]
wire _T_791 = |q_ff[21:0]; // @[el2_lib.scala 234:32]
wire _T_793 = ~q_ff[22]; // @[el2_lib.scala 235:32]
wire _T_795 = _T_791 ? _T_793 : q_ff[22]; // @[el2_lib.scala 235:25]
wire _T_785 = |q_ff[20:0]; // @[el2_lib.scala 234:32]
wire _T_787 = ~q_ff[21]; // @[el2_lib.scala 235:32]
wire _T_789 = _T_785 ? _T_787 : q_ff[21]; // @[el2_lib.scala 235:25]
wire _T_779 = |q_ff[19:0]; // @[el2_lib.scala 234:32]
wire _T_781 = ~q_ff[20]; // @[el2_lib.scala 235:32]
wire _T_783 = _T_779 ? _T_781 : q_ff[20]; // @[el2_lib.scala 235:25]
wire _T_773 = |q_ff[18:0]; // @[el2_lib.scala 234:32]
wire _T_775 = ~q_ff[19]; // @[el2_lib.scala 235:32]
wire _T_777 = _T_773 ? _T_775 : q_ff[19]; // @[el2_lib.scala 235:25]
wire _T_767 = |q_ff[17:0]; // @[el2_lib.scala 234:32]
wire _T_769 = ~q_ff[18]; // @[el2_lib.scala 235:32]
wire _T_771 = _T_767 ? _T_769 : q_ff[18]; // @[el2_lib.scala 235:25]
wire _T_761 = |q_ff[16:0]; // @[el2_lib.scala 234:32]
wire _T_763 = ~q_ff[17]; // @[el2_lib.scala 235:32]
wire _T_765 = _T_761 ? _T_763 : q_ff[17]; // @[el2_lib.scala 235:25]
wire _T_755 = |q_ff[15:0]; // @[el2_lib.scala 234:32]
wire _T_757 = ~q_ff[16]; // @[el2_lib.scala 235:32]
wire _T_759 = _T_755 ? _T_757 : q_ff[16]; // @[el2_lib.scala 235:25]
wire [7:0] _T_870 = {_T_801,_T_795,_T_789,_T_783,_T_777,_T_771,_T_765,_T_759}; // @[el2_lib.scala 237:14]
wire _T_749 = |q_ff[14:0]; // @[el2_lib.scala 234:32]
wire _T_751 = ~q_ff[15]; // @[el2_lib.scala 235:32]
wire _T_753 = _T_749 ? _T_751 : q_ff[15]; // @[el2_lib.scala 235:25]
wire _T_743 = |q_ff[13:0]; // @[el2_lib.scala 234:32]
wire _T_745 = ~q_ff[14]; // @[el2_lib.scala 235:32]
wire _T_747 = _T_743 ? _T_745 : q_ff[14]; // @[el2_lib.scala 235:25]
wire _T_737 = |q_ff[12:0]; // @[el2_lib.scala 234:32]
wire _T_739 = ~q_ff[13]; // @[el2_lib.scala 235:32]
wire _T_741 = _T_737 ? _T_739 : q_ff[13]; // @[el2_lib.scala 235:25]
wire _T_731 = |q_ff[11:0]; // @[el2_lib.scala 234:32]
wire _T_733 = ~q_ff[12]; // @[el2_lib.scala 235:32]
wire _T_735 = _T_731 ? _T_733 : q_ff[12]; // @[el2_lib.scala 235:25]
wire _T_725 = |q_ff[10:0]; // @[el2_lib.scala 234:32]
wire _T_727 = ~q_ff[11]; // @[el2_lib.scala 235:32]
wire _T_729 = _T_725 ? _T_727 : q_ff[11]; // @[el2_lib.scala 235:25]
wire _T_719 = |q_ff[9:0]; // @[el2_lib.scala 234:32]
wire _T_721 = ~q_ff[10]; // @[el2_lib.scala 235:32]
wire _T_723 = _T_719 ? _T_721 : q_ff[10]; // @[el2_lib.scala 235:25]
wire _T_713 = |q_ff[8:0]; // @[el2_lib.scala 234:32]
wire _T_715 = ~q_ff[9]; // @[el2_lib.scala 235:32]
wire _T_717 = _T_713 ? _T_715 : q_ff[9]; // @[el2_lib.scala 235:25]
wire _T_707 = |q_ff[7:0]; // @[el2_lib.scala 234:32]
wire _T_709 = ~q_ff[8]; // @[el2_lib.scala 235:32]
wire _T_711 = _T_707 ? _T_709 : q_ff[8]; // @[el2_lib.scala 235:25]
wire _T_701 = |q_ff[6:0]; // @[el2_lib.scala 234:32]
wire _T_703 = ~q_ff[7]; // @[el2_lib.scala 235:32]
wire _T_705 = _T_701 ? _T_703 : q_ff[7]; // @[el2_lib.scala 235:25]
wire _T_695 = |q_ff[5:0]; // @[el2_lib.scala 234:32]
wire _T_697 = ~q_ff[6]; // @[el2_lib.scala 235:32]
wire _T_699 = _T_695 ? _T_697 : q_ff[6]; // @[el2_lib.scala 235:25]
wire _T_689 = |q_ff[4:0]; // @[el2_lib.scala 234:32]
wire _T_691 = ~q_ff[5]; // @[el2_lib.scala 235:32]
wire _T_693 = _T_689 ? _T_691 : q_ff[5]; // @[el2_lib.scala 235:25]
wire _T_683 = |q_ff[3:0]; // @[el2_lib.scala 234:32]
wire _T_685 = ~q_ff[4]; // @[el2_lib.scala 235:32]
wire _T_687 = _T_683 ? _T_685 : q_ff[4]; // @[el2_lib.scala 235:25]
wire _T_677 = |q_ff[2:0]; // @[el2_lib.scala 234:32]
wire _T_679 = ~q_ff[3]; // @[el2_lib.scala 235:32]
wire _T_681 = _T_677 ? _T_679 : q_ff[3]; // @[el2_lib.scala 235:25]
wire _T_671 = |q_ff[1:0]; // @[el2_lib.scala 234:32]
wire _T_673 = ~q_ff[2]; // @[el2_lib.scala 235:32]
wire _T_675 = _T_671 ? _T_673 : q_ff[2]; // @[el2_lib.scala 235:25]
wire _T_665 = |q_ff[0]; // @[el2_lib.scala 234:32]
wire _T_667 = ~q_ff[1]; // @[el2_lib.scala 235:32]
wire _T_669 = _T_665 ? _T_667 : q_ff[1]; // @[el2_lib.scala 235:25]
wire [6:0] _T_855 = {_T_705,_T_699,_T_693,_T_687,_T_681,_T_675,_T_669}; // @[el2_lib.scala 237:14]
wire [14:0] _T_863 = {_T_753,_T_747,_T_741,_T_735,_T_729,_T_723,_T_717,_T_711,_T_855}; // @[el2_lib.scala 237:14]
wire [30:0] _T_879 = {_T_849,_T_843,_T_837,_T_831,_T_825,_T_819,_T_813,_T_807,_T_870,_T_863}; // @[el2_lib.scala 237:14]
wire [31:0] _T_881 = {_T_879,q_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] dividend_eff = _T_660 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 180:22]
wire [32:0] _T_917 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
wire _T_929 = _T_607 & rem_ff; // @[el2_exu_div_ctl.scala 196:41]
reg [32:0] a_ff; // @[Reg.scala 27:20]
wire rem_correct = _T_929 & a_ff[32]; // @[el2_exu_div_ctl.scala 196:50]
wire [32:0] _T_902 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
wire _T_890 = ~rem_correct; // @[el2_exu_div_ctl.scala 187:6]
wire _T_891 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 187:21]
wire _T_892 = _T_890 & _T_891; // @[el2_exu_div_ctl.scala 187:19]
wire [32:0] _T_896 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
wire [32:0] _T_903 = _T_892 ? _T_896 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_905 = _T_902 | _T_903; // @[Mux.scala 27:72]
wire _T_898 = _T_890 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 188:19]
wire [55:0] _T_887 = {24'h0,dividend_eff}; // @[Cat.scala 29:58]
wire [86:0] _GEN_16 = {{31'd0}, _T_887}; // @[el2_exu_div_ctl.scala 184:47]
wire [86:0] _T_888 = _GEN_16 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 184:47]
wire [55:0] a_eff_shift = _T_888[55:0]; // @[el2_exu_div_ctl.scala 184:15]
wire [32:0] _T_901 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58]
wire [32:0] _T_904 = _T_898 ? _T_901 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] a_eff = _T_905 | _T_904; // @[Mux.scala 27:72]
wire [32:0] a_shift = _T_917 & a_eff; // @[el2_exu_div_ctl.scala 191:33]
wire _T_926 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 195:21]
reg divisor_neg_ff; // @[Reg.scala 27:20]
wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 193:48]
wire add = _T_926 ^ m_already_comp; // @[el2_exu_div_ctl.scala 195:36]
wire [32:0] _T_885 = ~m_ff; // @[el2_exu_div_ctl.scala 183:35]
wire [32:0] m_eff = add ? m_ff : _T_885; // @[el2_exu_div_ctl.scala 183:15]
wire [32:0] _T_919 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 192:41]
wire _T_920 = ~add; // @[el2_exu_div_ctl.scala 192:65]
wire [32:0] _T_921 = {32'h0,_T_920}; // @[Cat.scala 29:58]
wire [32:0] _T_923 = _T_919 + _T_921; // @[el2_exu_div_ctl.scala 192:49]
wire [32:0] a_in = _T_917 & _T_923; // @[el2_exu_div_ctl.scala 192:30]
wire _T_641 = ~a_in[32]; // @[el2_exu_div_ctl.scala 176:85]
wire [32:0] _T_642 = {dividend_eff,_T_641}; // @[Cat.scala 29:58]
wire [63:0] _GEN_17 = {{31'd0}, _T_642}; // @[el2_exu_div_ctl.scala 176:96]
wire [63:0] _T_643 = _GEN_17 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 176:96]
wire _T_645 = ~_T_636; // @[el2_exu_div_ctl.scala 177:18]
wire _T_646 = run_state & _T_645; // @[el2_exu_div_ctl.scala 177:16]
wire [32:0] _T_651 = {q_ff[31:0],_T_641}; // @[Cat.scala 29:58]
wire [32:0] _T_652 = _T_633 ? _T_635 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _T_653 = _T_637 ? _T_643 : 64'h0; // @[Mux.scala 27:72]
wire [32:0] _T_654 = _T_646 ? _T_651 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _GEN_18 = {{31'd0}, _T_652}; // @[Mux.scala 27:72]
wire [63:0] _T_655 = _GEN_18 | _T_653; // @[Mux.scala 27:72]
wire [63:0] _GEN_19 = {{31'd0}, _T_654}; // @[Mux.scala 27:72]
wire [63:0] _T_656 = _T_655 | _GEN_19; // @[Mux.scala 27:72]
wire _T_659 = run_state & _T_619; // @[el2_exu_div_ctl.scala 179:48]
wire qff_enable = io_dp_valid | _T_659; // @[el2_exu_div_ctl.scala 179:35]
wire _T_910 = count != 6'h21; // @[el2_exu_div_ctl.scala 190:73]
wire _T_911 = _T_659 & _T_910; // @[el2_exu_div_ctl.scala 190:64]
wire _T_912 = io_dp_valid | _T_911; // @[el2_exu_div_ctl.scala 190:34]
wire aff_enable = _T_912 | rem_correct; // @[el2_exu_div_ctl.scala 190:89]
wire _T_932 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 197:50]
wire _T_933 = sign_ff & _T_932; // @[el2_exu_div_ctl.scala 197:31]
wire [31:0] q_ff_eff = _T_933 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 197:21]
wire _T_1161 = |a_ff[0]; // @[el2_lib.scala 234:32]
wire _T_1163 = ~a_ff[1]; // @[el2_lib.scala 235:32]
wire _T_1165 = _T_1161 ? _T_1163 : a_ff[1]; // @[el2_lib.scala 235:25]
wire _T_1167 = |a_ff[1:0]; // @[el2_lib.scala 234:32]
wire _T_1169 = ~a_ff[2]; // @[el2_lib.scala 235:32]
wire _T_1171 = _T_1167 ? _T_1169 : a_ff[2]; // @[el2_lib.scala 235:25]
wire _T_1173 = |a_ff[2:0]; // @[el2_lib.scala 234:32]
wire _T_1175 = ~a_ff[3]; // @[el2_lib.scala 235:32]
wire _T_1177 = _T_1173 ? _T_1175 : a_ff[3]; // @[el2_lib.scala 235:25]
wire _T_1179 = |a_ff[3:0]; // @[el2_lib.scala 234:32]
wire _T_1181 = ~a_ff[4]; // @[el2_lib.scala 235:32]
wire _T_1183 = _T_1179 ? _T_1181 : a_ff[4]; // @[el2_lib.scala 235:25]
wire _T_1185 = |a_ff[4:0]; // @[el2_lib.scala 234:32]
wire _T_1187 = ~a_ff[5]; // @[el2_lib.scala 235:32]
wire _T_1189 = _T_1185 ? _T_1187 : a_ff[5]; // @[el2_lib.scala 235:25]
wire _T_1191 = |a_ff[5:0]; // @[el2_lib.scala 234:32]
wire _T_1193 = ~a_ff[6]; // @[el2_lib.scala 235:32]
wire _T_1195 = _T_1191 ? _T_1193 : a_ff[6]; // @[el2_lib.scala 235:25]
wire _T_1197 = |a_ff[6:0]; // @[el2_lib.scala 234:32]
wire _T_1199 = ~a_ff[7]; // @[el2_lib.scala 235:32]
wire _T_1201 = _T_1197 ? _T_1199 : a_ff[7]; // @[el2_lib.scala 235:25]
wire _T_1203 = |a_ff[7:0]; // @[el2_lib.scala 234:32]
wire _T_1205 = ~a_ff[8]; // @[el2_lib.scala 235:32]
wire _T_1207 = _T_1203 ? _T_1205 : a_ff[8]; // @[el2_lib.scala 235:25]
wire _T_1209 = |a_ff[8:0]; // @[el2_lib.scala 234:32]
wire _T_1211 = ~a_ff[9]; // @[el2_lib.scala 235:32]
wire _T_1213 = _T_1209 ? _T_1211 : a_ff[9]; // @[el2_lib.scala 235:25]
wire _T_1215 = |a_ff[9:0]; // @[el2_lib.scala 234:32]
wire _T_1217 = ~a_ff[10]; // @[el2_lib.scala 235:32]
wire _T_1219 = _T_1215 ? _T_1217 : a_ff[10]; // @[el2_lib.scala 235:25]
wire _T_1221 = |a_ff[10:0]; // @[el2_lib.scala 234:32]
wire _T_1223 = ~a_ff[11]; // @[el2_lib.scala 235:32]
wire _T_1225 = _T_1221 ? _T_1223 : a_ff[11]; // @[el2_lib.scala 235:25]
wire _T_1227 = |a_ff[11:0]; // @[el2_lib.scala 234:32]
wire _T_1229 = ~a_ff[12]; // @[el2_lib.scala 235:32]
wire _T_1231 = _T_1227 ? _T_1229 : a_ff[12]; // @[el2_lib.scala 235:25]
wire _T_1233 = |a_ff[12:0]; // @[el2_lib.scala 234:32]
wire _T_1235 = ~a_ff[13]; // @[el2_lib.scala 235:32]
wire _T_1237 = _T_1233 ? _T_1235 : a_ff[13]; // @[el2_lib.scala 235:25]
wire _T_1239 = |a_ff[13:0]; // @[el2_lib.scala 234:32]
wire _T_1241 = ~a_ff[14]; // @[el2_lib.scala 235:32]
wire _T_1243 = _T_1239 ? _T_1241 : a_ff[14]; // @[el2_lib.scala 235:25]
wire _T_1245 = |a_ff[14:0]; // @[el2_lib.scala 234:32]
wire _T_1247 = ~a_ff[15]; // @[el2_lib.scala 235:32]
wire _T_1249 = _T_1245 ? _T_1247 : a_ff[15]; // @[el2_lib.scala 235:25]
wire _T_1251 = |a_ff[15:0]; // @[el2_lib.scala 234:32]
wire _T_1253 = ~a_ff[16]; // @[el2_lib.scala 235:32]
wire _T_1255 = _T_1251 ? _T_1253 : a_ff[16]; // @[el2_lib.scala 235:25]
wire _T_1257 = |a_ff[16:0]; // @[el2_lib.scala 234:32]
wire _T_1259 = ~a_ff[17]; // @[el2_lib.scala 235:32]
wire _T_1261 = _T_1257 ? _T_1259 : a_ff[17]; // @[el2_lib.scala 235:25]
wire _T_1263 = |a_ff[17:0]; // @[el2_lib.scala 234:32]
wire _T_1265 = ~a_ff[18]; // @[el2_lib.scala 235:32]
wire _T_1267 = _T_1263 ? _T_1265 : a_ff[18]; // @[el2_lib.scala 235:25]
wire _T_1269 = |a_ff[18:0]; // @[el2_lib.scala 234:32]
wire _T_1271 = ~a_ff[19]; // @[el2_lib.scala 235:32]
wire _T_1273 = _T_1269 ? _T_1271 : a_ff[19]; // @[el2_lib.scala 235:25]
wire _T_1275 = |a_ff[19:0]; // @[el2_lib.scala 234:32]
wire _T_1277 = ~a_ff[20]; // @[el2_lib.scala 235:32]
wire _T_1279 = _T_1275 ? _T_1277 : a_ff[20]; // @[el2_lib.scala 235:25]
wire _T_1281 = |a_ff[20:0]; // @[el2_lib.scala 234:32]
wire _T_1283 = ~a_ff[21]; // @[el2_lib.scala 235:32]
wire _T_1285 = _T_1281 ? _T_1283 : a_ff[21]; // @[el2_lib.scala 235:25]
wire _T_1287 = |a_ff[21:0]; // @[el2_lib.scala 234:32]
wire _T_1289 = ~a_ff[22]; // @[el2_lib.scala 235:32]
wire _T_1291 = _T_1287 ? _T_1289 : a_ff[22]; // @[el2_lib.scala 235:25]
wire _T_1293 = |a_ff[22:0]; // @[el2_lib.scala 234:32]
wire _T_1295 = ~a_ff[23]; // @[el2_lib.scala 235:32]
wire _T_1297 = _T_1293 ? _T_1295 : a_ff[23]; // @[el2_lib.scala 235:25]
wire _T_1299 = |a_ff[23:0]; // @[el2_lib.scala 234:32]
wire _T_1301 = ~a_ff[24]; // @[el2_lib.scala 235:32]
wire _T_1303 = _T_1299 ? _T_1301 : a_ff[24]; // @[el2_lib.scala 235:25]
wire _T_1305 = |a_ff[24:0]; // @[el2_lib.scala 234:32]
wire _T_1307 = ~a_ff[25]; // @[el2_lib.scala 235:32]
wire _T_1309 = _T_1305 ? _T_1307 : a_ff[25]; // @[el2_lib.scala 235:25]
wire _T_1311 = |a_ff[25:0]; // @[el2_lib.scala 234:32]
wire _T_1313 = ~a_ff[26]; // @[el2_lib.scala 235:32]
wire _T_1315 = _T_1311 ? _T_1313 : a_ff[26]; // @[el2_lib.scala 235:25]
wire _T_1317 = |a_ff[26:0]; // @[el2_lib.scala 234:32]
wire _T_1319 = ~a_ff[27]; // @[el2_lib.scala 235:32]
wire _T_1321 = _T_1317 ? _T_1319 : a_ff[27]; // @[el2_lib.scala 235:25]
wire _T_1323 = |a_ff[27:0]; // @[el2_lib.scala 234:32]
wire _T_1325 = ~a_ff[28]; // @[el2_lib.scala 235:32]
wire _T_1327 = _T_1323 ? _T_1325 : a_ff[28]; // @[el2_lib.scala 235:25]
wire _T_1329 = |a_ff[28:0]; // @[el2_lib.scala 234:32]
wire _T_1331 = ~a_ff[29]; // @[el2_lib.scala 235:32]
wire _T_1333 = _T_1329 ? _T_1331 : a_ff[29]; // @[el2_lib.scala 235:25]
wire _T_1335 = |a_ff[29:0]; // @[el2_lib.scala 234:32]
wire _T_1337 = ~a_ff[30]; // @[el2_lib.scala 235:32]
wire _T_1339 = _T_1335 ? _T_1337 : a_ff[30]; // @[el2_lib.scala 235:25]
wire _T_1341 = |a_ff[30:0]; // @[el2_lib.scala 234:32]
wire _T_1343 = ~a_ff[31]; // @[el2_lib.scala 235:32]
wire _T_1345 = _T_1341 ? _T_1343 : a_ff[31]; // @[el2_lib.scala 235:25]
wire [6:0] _T_1351 = {_T_1201,_T_1195,_T_1189,_T_1183,_T_1177,_T_1171,_T_1165}; // @[el2_lib.scala 237:14]
wire [14:0] _T_1359 = {_T_1249,_T_1243,_T_1237,_T_1231,_T_1225,_T_1219,_T_1213,_T_1207,_T_1351}; // @[el2_lib.scala 237:14]
wire [7:0] _T_1366 = {_T_1297,_T_1291,_T_1285,_T_1279,_T_1273,_T_1267,_T_1261,_T_1255}; // @[el2_lib.scala 237:14]
wire [30:0] _T_1375 = {_T_1345,_T_1339,_T_1333,_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1366,_T_1359}; // @[el2_lib.scala 237:14]
wire [31:0] _T_1377 = {_T_1375,a_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] a_ff_eff = _T_660 ? _T_1377 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 198:21]
reg smallnum_case_ff; // @[Reg.scala 27:20]
reg [3:0] smallnum_ff; // @[Reg.scala 27:20]
wire [31:0] _T_1380 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
wire _T_1382 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 203:6]
wire _T_1384 = _T_1382 & _T_9; // @[el2_exu_div_ctl.scala 203:24]
wire [31:0] _T_1386 = smallnum_case_ff ? _T_1380 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1387 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1388 = _T_1384 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1389 = _T_1386 | _T_1387; // @[Mux.scala 27:72]
wire _T_1393 = io_dp_valid & _T; // @[el2_exu_div_ctl.scala 211:40]
wire _T_1397 = finish & _T; // @[el2_exu_div_ctl.scala 212:37]
wire _T_1407 = io_dp_valid & div_clken; // @[el2_exu_div_ctl.scala 215:73]
wire [32:0] q_in = _T_656[32:0]; // @[el2_exu_div_ctl.scala 174:8]
wire _T_1436 = _T_631 & io_divisor[31]; // @[el2_exu_div_ctl.scala 225:40]
wire [32:0] _T_1437 = {_T_1436,io_divisor}; // @[Cat.scala 29:58]
assign io_out = _T_1389 | _T_1388; // @[el2_exu_div_ctl.scala 52:10 el2_exu_div_ctl.scala 200:10]
assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 53:17 el2_exu_div_ctl.scala 170:18]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
valid_ff_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
q_ff = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
m_ff = _RAND_2[32:0];
_RAND_3 = {1{`RANDOM}};
rem_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
sign_ff = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
shortq_shift_xx = _RAND_5[3:0];
_RAND_6 = {1{`RANDOM}};
count = _RAND_6[5:0];
_RAND_7 = {1{`RANDOM}};
run_state = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
finish_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
shortq_enable_ff = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
dividend_neg_ff = _RAND_10[0:0];
_RAND_11 = {2{`RANDOM}};
a_ff = _RAND_11[32:0];
_RAND_12 = {1{`RANDOM}};
divisor_neg_ff = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
smallnum_case_ff = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
smallnum_ff = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valid_ff_x = 1'h0;
end
if (reset) begin
q_ff = 33'h0;
end
if (reset) begin
m_ff = 33'h0;
end
if (reset) begin
rem_ff = 1'h0;
end
if (reset) begin
sign_ff = 1'h0;
end
if (reset) begin
shortq_shift_xx = 4'h0;
end
if (reset) begin
count = 6'h0;
end
if (reset) begin
run_state = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
dividend_neg_ff = 1'h0;
end
if (reset) begin
a_ff = 33'h0;
end
if (reset) begin
divisor_neg_ff = 1'h0;
end
if (reset) begin
smallnum_case_ff = 1'h0;
end
if (reset) begin
smallnum_ff = 4'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff_x <= 1'h0;
end else if (div_clken) begin
valid_ff_x <= _T_1393;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 33'h0;
end else if (qff_enable) begin
q_ff <= q_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
m_ff <= 33'h0;
end else if (io_dp_valid) begin
m_ff <= _T_1437;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rem_ff <= 1'h0;
end else if (_T_1407) begin
rem_ff <= io_dp_rem;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sign_ff <= 1'h0;
end else if (_T_1407) begin
sign_ff <= sign_eff;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_shift_xx <= 4'h0;
end else if (div_clken) begin
shortq_shift_xx <= shortq_shift;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count <= 6'h0;
end else if (div_clken) begin
count <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
run_state <= 1'h0;
end else if (div_clken) begin
run_state <= run_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (div_clken) begin
finish_ff <= _T_1397;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (div_clken) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
dividend_neg_ff <= 1'h0;
end else if (_T_1407) begin
dividend_neg_ff <= io_dividend[31];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 33'h0;
end else if (aff_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
divisor_neg_ff <= 1'h0;
end else if (_T_1407) begin
divisor_neg_ff <= io_divisor[31];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_case_ff <= 1'h0;
end else if (div_clken) begin
smallnum_case_ff <= smallnum_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_ff <= 4'h0;
end else if (div_clken) begin
smallnum_ff <= smallnum;
end
end
endmodule

18
el2_exu_mul_ctl.anno.json Normal file
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@ -0,0 +1,18 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_mul_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

55
el2_exu_mul_ctl.fir Normal file
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@ -0,0 +1,55 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_exu_mul_ctl :
module el2_exu_mul_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
wire rs1_ext_in : SInt<33>
rs1_ext_in <= asSInt(UInt<1>("h00"))
wire rs2_ext_in : SInt<33>
rs2_ext_in <= asSInt(UInt<1>("h00"))
wire prod_x : SInt<66>
prod_x <= asSInt(UInt<1>("h00"))
wire low_x : UInt<1>
low_x <= UInt<1>("h00")
node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 23:50]
node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 23:39]
node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 23:66]
rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 23:14]
node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 24:50]
node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 24:39]
node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 24:66]
rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 24:14]
node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 27:55]
reg _T_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_8 : @[Reg.scala 28:19]
_T_9 <= io.mul_p.low @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
low_x <= _T_9 @[el2_exu_mul_ctl.scala 27:9]
node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 28:56]
reg rs1_x : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20]
when _T_10 : @[Reg.scala 28:19]
rs1_x <= rs1_ext_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_11 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 29:56]
reg rs2_x : SInt, clock with : (reset => (reset, asSInt(UInt<1>("h00")))) @[Reg.scala 27:20]
when _T_11 : @[Reg.scala 28:19]
rs2_x <= rs2_ext_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_12 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 31:20]
prod_x <= _T_12 @[el2_exu_mul_ctl.scala 31:10]
node _T_13 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 32:36]
node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 32:29]
node _T_15 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 32:52]
node _T_16 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 32:67]
node _T_17 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 32:83]
node _T_18 = mux(_T_14, _T_15, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = or(_T_18, _T_19) @[Mux.scala 27:72]
wire _T_21 : UInt<32> @[Mux.scala 27:72]
_T_21 <= _T_20 @[Mux.scala 27:72]
io.result_x <= _T_21 @[el2_exu_mul_ctl.scala 32:15]

123
el2_exu_mul_ctl.v Normal file
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@ -0,0 +1,123 @@
module el2_exu_mul_ctl(
input clock,
input reset,
input io_scan_mode,
input io_mul_p_valid,
input io_mul_p_rs1_sign,
input io_mul_p_rs2_sign,
input io_mul_p_low,
input io_mul_p_bext,
input io_mul_p_bdep,
input io_mul_p_clmul,
input io_mul_p_clmulh,
input io_mul_p_clmulr,
input io_mul_p_grev,
input io_mul_p_shfl,
input io_mul_p_unshfl,
input io_mul_p_crc32_b,
input io_mul_p_crc32_h,
input io_mul_p_crc32_w,
input io_mul_p_crc32c_b,
input io_mul_p_crc32c_h,
input io_mul_p_crc32c_w,
input io_mul_p_bfp,
input [31:0] io_rs1_in,
input [31:0] io_rs2_in,
output [31:0] io_result_x
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 23:39]
wire [32:0] rs1_ext_in = {_T_1,io_rs1_in}; // @[el2_exu_mul_ctl.scala 23:66]
wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 24:39]
wire [32:0] rs2_ext_in = {_T_5,io_rs2_in}; // @[el2_exu_mul_ctl.scala 24:66]
reg low_x; // @[Reg.scala 27:20]
reg [32:0] rs1_x; // @[Reg.scala 27:20]
reg [32:0] rs2_x; // @[Reg.scala 27:20]
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 31:20]
wire _T_14 = ~low_x; // @[el2_exu_mul_ctl.scala 32:29]
wire [31:0] _T_18 = _T_14 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_19 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
assign io_result_x = _T_18 | _T_19; // @[el2_exu_mul_ctl.scala 32:15]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
low_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
rs1_x = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
rs2_x = _RAND_2[32:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
low_x = 1'h0;
end
if (reset) begin
rs1_x = 33'sh0;
end
if (reset) begin
rs2_x = 33'sh0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
low_x <= 1'h0;
end else if (io_mul_p_valid) begin
low_x <= io_mul_p_low;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rs1_x <= 33'sh0;
end else if (io_mul_p_valid) begin
rs1_x <= rs1_ext_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rs2_x <= 33'sh0;
end else if (io_mul_p_valid) begin
rs2_x <= rs2_ext_in;
end
end
endmodule

424
el2_lsu.anno.json Normal file
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@ -0,0 +1,424 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_rdata",
"sources":[
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_single_ecc_error_incr",
"sources":[
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"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
"sources":[
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"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
"sources":[
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rden",
"sources":[
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wren",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_",
"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
"sources":[
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_fastint_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_wr_data",
"sources":[
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_load",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
"sources":[
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_lsu_p_valid",
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
"~el2_lsu|el2_lsu>io_lsu_p_store",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_picm_rdaddr",
"sources":[
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
"sources":[
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
"sources":[
"~el2_lsu|el2_lsu>io_dma_dccm_req",
"~el2_lsu|el2_lsu>io_dma_mem_write",
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
"~el2_lsu|el2_lsu>io_dma_mem_addr",
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu|el2_lsu>io_lsu_p_dword",
"~el2_lsu|el2_lsu>io_lsu_p_half",
"~el2_lsu|el2_lsu>io_lsu_p_word",
"~el2_lsu|el2_lsu>io_dma_mem_sz",
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
"~el2_lsu|el2_lsu>io_picm_rd_data",
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

7528
el2_lsu.fir Normal file
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5102
el2_lsu.v Normal file
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111
el2_lsu_addrcheck.anno.json Normal file
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@ -0,0 +1,111 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_exc_mscause_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_nondccm_access_error_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_dccm_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_dccm_access_error_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_access_fault_d",
"sources":[
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_addrcheck"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

304
el2_lsu_addrcheck.fir Normal file
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@ -0,0 +1,304 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_addrcheck :
module rvrangecheck :
input clock : Clock
input reset : Reset
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
io.in_region <= _T_1 @[beh_lib.scala 113:19]
node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 117:30]
node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 117:45]
io.in_range <= _T_3 @[beh_lib.scala 117:19]
module rvrangecheck_1 :
input clock : Clock
input reset : Reset
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
io.in_region <= _T_1 @[beh_lib.scala 113:19]
node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 117:30]
node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 117:45]
io.in_range <= _T_3 @[beh_lib.scala 117:19]
module rvrangecheck_2 :
input clock : Clock
input reset : Reset
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
io.in_region <= _T_1 @[beh_lib.scala 113:19]
node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 117:30]
node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 117:45]
io.in_range <= _T_3 @[beh_lib.scala 117:19]
module rvrangecheck_3 :
input clock : Clock
input reset : Reset
output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
node _T = bits(io.addr, 31, 28) @[beh_lib.scala 113:30]
node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 113:52]
io.in_region <= _T_1 @[beh_lib.scala 113:19]
node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 117:30]
node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 117:45]
io.in_range <= _T_3 @[beh_lib.scala 117:19]
module el2_lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
wire start_addr_in_dccm_d : UInt<1>
start_addr_in_dccm_d <= UInt<1>("h00")
wire start_addr_in_dccm_region_d : UInt<1>
start_addr_in_dccm_region_d <= UInt<1>("h00")
wire end_addr_in_dccm_d : UInt<1>
end_addr_in_dccm_d <= UInt<1>("h00")
wire end_addr_in_dccm_region_d : UInt<1>
end_addr_in_dccm_region_d <= UInt<1>("h00")
inst rvrangecheck of rvrangecheck @[el2_lsu_addrcheck.scala 45:44]
rvrangecheck.clock <= clock
rvrangecheck.reset <= reset
rvrangecheck.io.addr <= io.start_addr_d @[el2_lsu_addrcheck.scala 46:41]
start_addr_in_dccm_d <= rvrangecheck.io.in_range @[el2_lsu_addrcheck.scala 47:41]
start_addr_in_dccm_region_d <= rvrangecheck.io.in_region @[el2_lsu_addrcheck.scala 48:41]
inst rvrangecheck_1 of rvrangecheck_1 @[el2_lsu_addrcheck.scala 51:44]
rvrangecheck_1.clock <= clock
rvrangecheck_1.reset <= reset
rvrangecheck_1.io.addr <= io.end_addr_d @[el2_lsu_addrcheck.scala 52:41]
end_addr_in_dccm_d <= rvrangecheck_1.io.in_range @[el2_lsu_addrcheck.scala 53:41]
end_addr_in_dccm_region_d <= rvrangecheck_1.io.in_region @[el2_lsu_addrcheck.scala 54:41]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 65:37]
node _T_1 = eq(_T, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 65:45]
addr_in_iccm <= _T_1 @[el2_lsu_addrcheck.scala 65:18]
inst start_addr_pic_rangecheck of rvrangecheck_2 @[el2_lsu_addrcheck.scala 74:41]
start_addr_pic_rangecheck.clock <= clock
start_addr_pic_rangecheck.reset <= reset
node _T_2 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 75:55]
start_addr_pic_rangecheck.io.addr <= _T_2 @[el2_lsu_addrcheck.scala 75:37]
inst end_addr_pic_rangecheck of rvrangecheck_3 @[el2_lsu_addrcheck.scala 80:39]
end_addr_pic_rangecheck.clock <= clock
end_addr_pic_rangecheck.reset <= reset
node _T_3 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:51]
end_addr_pic_rangecheck.io.addr <= _T_3 @[el2_lsu_addrcheck.scala 81:35]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 85:60]
node _T_4 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:48]
node _T_5 = eq(_T_4, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:54]
node _T_6 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:92]
node _T_7 = eq(_T_6, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:98]
node base_reg_dccm_or_pic = or(_T_5, _T_7) @[el2_lsu_addrcheck.scala 86:74]
node _T_8 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 87:57]
io.addr_in_dccm_d <= _T_8 @[el2_lsu_addrcheck.scala 87:32]
node _T_9 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 88:56]
io.addr_in_pic_d <= _T_9 @[el2_lsu_addrcheck.scala 88:32]
node _T_10 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 90:63]
node _T_11 = not(_T_10) @[el2_lsu_addrcheck.scala 90:33]
io.addr_external_d <= _T_11 @[el2_lsu_addrcheck.scala 90:30]
node _T_12 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 91:51]
node csr_idx = cat(_T_12, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_13 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 92:50]
node _T_14 = bits(_T_13, 0, 0) @[el2_lsu_addrcheck.scala 92:50]
node _T_15 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 92:92]
node _T_16 = or(_T_15, addr_in_iccm) @[el2_lsu_addrcheck.scala 92:121]
node _T_17 = not(_T_16) @[el2_lsu_addrcheck.scala 92:62]
node _T_18 = and(_T_14, _T_17) @[el2_lsu_addrcheck.scala 92:60]
node _T_19 = and(_T_18, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 92:137]
node _T_20 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 92:180]
node is_sideeffects_d = and(_T_19, _T_20) @[el2_lsu_addrcheck.scala 92:158]
node _T_21 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 93:69]
node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:75]
node _T_23 = and(io.lsu_pkt_d.word, _T_22) @[el2_lsu_addrcheck.scala 93:51]
node _T_24 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 93:124]
node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:128]
node _T_26 = and(io.lsu_pkt_d.half, _T_25) @[el2_lsu_addrcheck.scala 93:106]
node _T_27 = or(_T_23, _T_26) @[el2_lsu_addrcheck.scala 93:85]
node is_aligned_d = or(_T_27, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 93:138]
node _T_28 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_29 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_30 = cat(_T_29, _T_28) @[Cat.scala 29:58]
node _T_31 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_32 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_33 = cat(_T_32, _T_31) @[Cat.scala 29:58]
node _T_34 = cat(_T_33, _T_30) @[Cat.scala 29:58]
node _T_35 = orr(_T_34) @[el2_lsu_addrcheck.scala 97:99]
node _T_36 = not(_T_35) @[el2_lsu_addrcheck.scala 96:33]
node _T_37 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 98:50]
node _T_38 = or(_T_37, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:57]
node _T_39 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:108]
node _T_40 = eq(_T_38, _T_39) @[el2_lsu_addrcheck.scala 98:82]
node _T_41 = and(UInt<1>("h01"), _T_40) @[el2_lsu_addrcheck.scala 98:31]
node _T_42 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 99:50]
node _T_43 = or(_T_42, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:57]
node _T_44 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:108]
node _T_45 = eq(_T_43, _T_44) @[el2_lsu_addrcheck.scala 99:82]
node _T_46 = and(UInt<1>("h01"), _T_45) @[el2_lsu_addrcheck.scala 99:31]
node _T_47 = or(_T_41, _T_46) @[el2_lsu_addrcheck.scala 98:133]
node _T_48 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 100:50]
node _T_49 = or(_T_48, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:57]
node _T_50 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:108]
node _T_51 = eq(_T_49, _T_50) @[el2_lsu_addrcheck.scala 100:82]
node _T_52 = and(UInt<1>("h01"), _T_51) @[el2_lsu_addrcheck.scala 100:31]
node _T_53 = or(_T_47, _T_52) @[el2_lsu_addrcheck.scala 99:133]
node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 101:50]
node _T_55 = or(_T_54, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:57]
node _T_56 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:108]
node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 101:82]
node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 101:31]
node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 100:133]
node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 102:50]
node _T_61 = or(_T_60, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:57]
node _T_62 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:108]
node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 102:82]
node _T_64 = and(UInt<1>("h00"), _T_63) @[el2_lsu_addrcheck.scala 102:31]
node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 101:133]
node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 103:50]
node _T_67 = or(_T_66, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:57]
node _T_68 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:108]
node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 103:82]
node _T_70 = and(UInt<1>("h00"), _T_69) @[el2_lsu_addrcheck.scala 103:31]
node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 102:133]
node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 104:50]
node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:57]
node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:108]
node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 104:82]
node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 104:31]
node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 103:133]
node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 105:50]
node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:57]
node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:108]
node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 105:82]
node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 105:31]
node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 104:133]
node _T_84 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 107:49]
node _T_85 = or(_T_84, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:58]
node _T_86 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:109]
node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 107:83]
node _T_88 = and(UInt<1>("h01"), _T_87) @[el2_lsu_addrcheck.scala 107:32]
node _T_89 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 108:50]
node _T_90 = or(_T_89, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:59]
node _T_91 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:110]
node _T_92 = eq(_T_90, _T_91) @[el2_lsu_addrcheck.scala 108:84]
node _T_93 = and(UInt<1>("h01"), _T_92) @[el2_lsu_addrcheck.scala 108:33]
node _T_94 = or(_T_88, _T_93) @[el2_lsu_addrcheck.scala 107:134]
node _T_95 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 109:50]
node _T_96 = or(_T_95, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:59]
node _T_97 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:110]
node _T_98 = eq(_T_96, _T_97) @[el2_lsu_addrcheck.scala 109:84]
node _T_99 = and(UInt<1>("h01"), _T_98) @[el2_lsu_addrcheck.scala 109:33]
node _T_100 = or(_T_94, _T_99) @[el2_lsu_addrcheck.scala 108:135]
node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 110:50]
node _T_102 = or(_T_101, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:59]
node _T_103 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:110]
node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 110:84]
node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 110:33]
node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 109:135]
node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 111:50]
node _T_108 = or(_T_107, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:59]
node _T_109 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:110]
node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 111:84]
node _T_111 = and(UInt<1>("h00"), _T_110) @[el2_lsu_addrcheck.scala 111:33]
node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 110:135]
node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 112:50]
node _T_114 = or(_T_113, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:59]
node _T_115 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:110]
node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 112:84]
node _T_117 = and(UInt<1>("h00"), _T_116) @[el2_lsu_addrcheck.scala 112:33]
node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 111:135]
node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 113:50]
node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:59]
node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:110]
node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 113:84]
node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 113:33]
node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 112:135]
node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 114:50]
node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:59]
node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:110]
node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 114:84]
node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 114:33]
node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 113:135]
node _T_131 = and(_T_83, _T_130) @[el2_lsu_addrcheck.scala 106:7]
node non_dccm_access_ok = or(_T_36, _T_131) @[el2_lsu_addrcheck.scala 97:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 116:57]
node _T_132 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 117:70]
node _T_133 = neq(_T_132, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 117:76]
node _T_134 = not(io.lsu_pkt_d.word) @[el2_lsu_addrcheck.scala 117:92]
node _T_135 = or(_T_133, _T_134) @[el2_lsu_addrcheck.scala 117:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_135) @[el2_lsu_addrcheck.scala 117:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_136 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 122:87]
node _T_137 = not(_T_136) @[el2_lsu_addrcheck.scala 122:64]
node _T_138 = and(start_addr_in_dccm_region_d, _T_137) @[el2_lsu_addrcheck.scala 122:62]
node _T_139 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 124:57]
node _T_140 = not(_T_139) @[el2_lsu_addrcheck.scala 124:36]
node _T_141 = and(end_addr_in_dccm_region_d, _T_140) @[el2_lsu_addrcheck.scala 124:34]
node _T_142 = or(_T_138, _T_141) @[el2_lsu_addrcheck.scala 122:112]
node _T_143 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 126:29]
node _T_144 = or(_T_142, _T_143) @[el2_lsu_addrcheck.scala 124:85]
node _T_145 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 128:29]
node _T_146 = or(_T_144, _T_145) @[el2_lsu_addrcheck.scala 126:85]
unmapped_access_fault_d <= _T_146 @[el2_lsu_addrcheck.scala 122:29]
node _T_147 = not(start_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 130:33]
node _T_148 = not(non_dccm_access_ok) @[el2_lsu_addrcheck.scala 130:64]
node _T_149 = and(_T_147, _T_148) @[el2_lsu_addrcheck.scala 130:62]
mpu_access_fault_d <= _T_149 @[el2_lsu_addrcheck.scala 130:29]
node _T_150 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 142:49]
node _T_151 = or(_T_150, picm_access_fault_d) @[el2_lsu_addrcheck.scala 142:70]
node _T_152 = or(_T_151, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 142:92]
node _T_153 = and(_T_152, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 142:118]
node _T_154 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 142:141]
node _T_155 = and(_T_153, _T_154) @[el2_lsu_addrcheck.scala 142:139]
io.access_fault_d <= _T_155 @[el2_lsu_addrcheck.scala 142:21]
node _T_156 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:60]
node _T_157 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:100]
node _T_158 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:144]
node _T_159 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:185]
node _T_160 = mux(_T_159, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 143:164]
node _T_161 = mux(_T_158, UInt<4>("h05"), _T_160) @[el2_lsu_addrcheck.scala 143:120]
node _T_162 = mux(_T_157, UInt<4>("h03"), _T_161) @[el2_lsu_addrcheck.scala 143:80]
node access_fault_mscause_d = mux(_T_156, UInt<4>("h02"), _T_162) @[el2_lsu_addrcheck.scala 143:35]
node _T_163 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:53]
node _T_164 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:78]
node regcross_misaligned_fault_d = neq(_T_163, _T_164) @[el2_lsu_addrcheck.scala 144:61]
node _T_165 = not(is_aligned_d) @[el2_lsu_addrcheck.scala 145:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_165) @[el2_lsu_addrcheck.scala 145:57]
node _T_166 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 146:90]
node _T_167 = or(regcross_misaligned_fault_d, _T_166) @[el2_lsu_addrcheck.scala 146:57]
node _T_168 = and(_T_167, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 146:113]
node _T_169 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 146:136]
node _T_170 = and(_T_168, _T_169) @[el2_lsu_addrcheck.scala 146:134]
io.misaligned_fault_d <= _T_170 @[el2_lsu_addrcheck.scala 146:25]
node _T_171 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 147:111]
node _T_172 = mux(_T_171, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 147:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_172) @[el2_lsu_addrcheck.scala 147:39]
node _T_173 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 148:50]
node _T_174 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:84]
node _T_175 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:113]
node _T_176 = mux(_T_173, _T_174, _T_175) @[el2_lsu_addrcheck.scala 148:27]
io.exc_mscause_d <= _T_176 @[el2_lsu_addrcheck.scala 148:21]
node _T_177 = not(start_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:66]
node _T_178 = and(start_addr_in_dccm_region_d, _T_177) @[el2_lsu_addrcheck.scala 149:64]
node _T_179 = not(end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:120]
node _T_180 = and(end_addr_in_dccm_region_d, _T_179) @[el2_lsu_addrcheck.scala 149:118]
node _T_181 = or(_T_178, _T_180) @[el2_lsu_addrcheck.scala 149:88]
node _T_182 = and(_T_181, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 149:142]
node _T_183 = and(_T_182, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 149:163]
io.fir_dccm_access_error_d <= _T_183 @[el2_lsu_addrcheck.scala 149:31]
node _T_184 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 150:66]
node _T_185 = not(_T_184) @[el2_lsu_addrcheck.scala 150:36]
node _T_186 = and(_T_185, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 150:95]
node _T_187 = and(_T_186, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 150:116]
io.fir_nondccm_access_error_d <= _T_187 @[el2_lsu_addrcheck.scala 150:33]
reg _T_188 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 152:60]
_T_188 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 152:60]
io.is_sideeffects_m <= _T_188 @[el2_lsu_addrcheck.scala 152:50]

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el2_lsu_addrcheck.v Normal file
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@ -0,0 +1,243 @@
module rvrangecheck(
input [31:0] io_addr,
output io_in_range,
output io_in_region
);
assign io_in_range = io_addr[31:16] == 16'hf004; // @[beh_lib.scala 117:19]
assign io_in_region = io_addr[31:28] == 4'hf; // @[beh_lib.scala 113:19]
endmodule
module rvrangecheck_2(
input [31:0] io_addr,
output io_in_range,
output io_in_region
);
assign io_in_range = io_addr[31:15] == 17'h1e018; // @[beh_lib.scala 117:19]
assign io_in_region = io_addr[31:28] == 4'hf; // @[beh_lib.scala 113:19]
endmodule
module el2_lsu_addrcheck(
input clock,
input reset,
input io_lsu_c2_m_clk,
input [31:0] io_start_addr_d,
input [31:0] io_end_addr_d,
input io_lsu_pkt_d_fast_int,
input io_lsu_pkt_d_by,
input io_lsu_pkt_d_half,
input io_lsu_pkt_d_word,
input io_lsu_pkt_d_dword,
input io_lsu_pkt_d_load,
input io_lsu_pkt_d_store,
input io_lsu_pkt_d_unsign,
input io_lsu_pkt_d_dma,
input io_lsu_pkt_d_store_data_bypass_d,
input io_lsu_pkt_d_load_ldst_bypass_d,
input io_lsu_pkt_d_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input [31:0] io_dec_tlu_mrac_ff,
input [3:0] io_rs1_region_d,
input [31:0] io_rs1_d,
output io_is_sideeffects_m,
output io_addr_in_dccm_d,
output io_addr_in_pic_d,
output io_addr_external_d,
output io_access_fault_d,
output io_misaligned_fault_d,
output [3:0] io_exc_mscause_d,
output io_fir_dccm_access_error_d,
output io_fir_nondccm_access_error_d,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire [31:0] rvrangecheck_io_addr; // @[el2_lsu_addrcheck.scala 45:44]
wire rvrangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 45:44]
wire rvrangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 45:44]
wire [31:0] rvrangecheck_1_io_addr; // @[el2_lsu_addrcheck.scala 51:44]
wire rvrangecheck_1_io_in_range; // @[el2_lsu_addrcheck.scala 51:44]
wire rvrangecheck_1_io_in_region; // @[el2_lsu_addrcheck.scala 51:44]
wire [31:0] start_addr_pic_rangecheck_io_addr; // @[el2_lsu_addrcheck.scala 74:41]
wire start_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 74:41]
wire start_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 74:41]
wire [31:0] end_addr_pic_rangecheck_io_addr; // @[el2_lsu_addrcheck.scala 80:39]
wire end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 80:39]
wire end_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 80:39]
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 65:45]
wire start_addr_in_dccm_region_d = rvrangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 48:41]
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 85:60]
wire _T_5 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 86:54]
wire base_reg_dccm_or_pic = _T_5 | _T_5; // @[el2_lsu_addrcheck.scala 86:74]
wire start_addr_in_dccm_d = rvrangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 47:41]
wire end_addr_in_dccm_d = rvrangecheck_1_io_in_range; // @[el2_lsu_addrcheck.scala 53:41]
wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
wire [31:0] _T_13 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 92:50]
wire _T_16 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 92:121]
wire _T_17 = ~_T_16; // @[el2_lsu_addrcheck.scala 92:62]
wire _T_18 = _T_13[0] & _T_17; // @[el2_lsu_addrcheck.scala 92:60]
wire _T_19 = _T_18 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 92:137]
wire _T_20 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 92:180]
wire is_sideeffects_d = _T_19 & _T_20; // @[el2_lsu_addrcheck.scala 92:158]
wire _T_22 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 93:75]
wire _T_23 = io_lsu_pkt_d_word & _T_22; // @[el2_lsu_addrcheck.scala 93:51]
wire _T_25 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 93:128]
wire _T_26 = io_lsu_pkt_d_half & _T_25; // @[el2_lsu_addrcheck.scala 93:106]
wire _T_27 = _T_23 | _T_26; // @[el2_lsu_addrcheck.scala 93:85]
wire is_aligned_d = _T_27 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 93:138]
wire [31:0] _T_38 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 98:57]
wire _T_40 = _T_38 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 98:82]
wire [31:0] _T_43 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 99:57]
wire _T_45 = _T_43 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 99:82]
wire _T_47 = _T_40 | _T_45; // @[el2_lsu_addrcheck.scala 98:133]
wire [31:0] _T_49 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 100:57]
wire _T_51 = _T_49 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 100:82]
wire _T_53 = _T_47 | _T_51; // @[el2_lsu_addrcheck.scala 99:133]
wire [31:0] _T_55 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 101:57]
wire _T_57 = _T_55 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 101:82]
wire _T_59 = _T_53 | _T_57; // @[el2_lsu_addrcheck.scala 100:133]
wire [31:0] _T_85 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 107:58]
wire _T_87 = _T_85 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 107:83]
wire [31:0] _T_90 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 108:59]
wire _T_92 = _T_90 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 108:84]
wire _T_94 = _T_87 | _T_92; // @[el2_lsu_addrcheck.scala 107:134]
wire [31:0] _T_96 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 109:59]
wire _T_98 = _T_96 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 109:84]
wire _T_100 = _T_94 | _T_98; // @[el2_lsu_addrcheck.scala 108:135]
wire [31:0] _T_102 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 110:59]
wire _T_104 = _T_102 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 110:84]
wire _T_106 = _T_100 | _T_104; // @[el2_lsu_addrcheck.scala 109:135]
wire non_dccm_access_ok = _T_59 & _T_106; // @[el2_lsu_addrcheck.scala 106:7]
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 116:57]
wire _T_133 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 117:76]
wire _T_134 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 117:92]
wire _T_135 = _T_133 | _T_134; // @[el2_lsu_addrcheck.scala 117:90]
wire picm_access_fault_d = io_addr_in_pic_d & _T_135; // @[el2_lsu_addrcheck.scala 117:51]
wire _T_136 = start_addr_in_dccm_d | start_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 122:87]
wire _T_137 = ~_T_136; // @[el2_lsu_addrcheck.scala 122:64]
wire _T_138 = start_addr_in_dccm_region_d & _T_137; // @[el2_lsu_addrcheck.scala 122:62]
wire _T_139 = end_addr_in_dccm_d | end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 124:57]
wire _T_140 = ~_T_139; // @[el2_lsu_addrcheck.scala 124:36]
wire end_addr_in_dccm_region_d = rvrangecheck_1_io_in_region; // @[el2_lsu_addrcheck.scala 54:41]
wire _T_141 = end_addr_in_dccm_region_d & _T_140; // @[el2_lsu_addrcheck.scala 124:34]
wire _T_142 = _T_138 | _T_141; // @[el2_lsu_addrcheck.scala 122:112]
wire _T_143 = start_addr_in_dccm_d & end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 126:29]
wire _T_144 = _T_142 | _T_143; // @[el2_lsu_addrcheck.scala 124:85]
wire _T_145 = start_addr_pic_rangecheck_io_in_range & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 128:29]
wire unmapped_access_fault_d = _T_144 | _T_145; // @[el2_lsu_addrcheck.scala 126:85]
wire _T_147 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 130:33]
wire _T_148 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 130:64]
wire mpu_access_fault_d = _T_147 & _T_148; // @[el2_lsu_addrcheck.scala 130:62]
wire _T_150 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 142:49]
wire _T_151 = _T_150 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 142:70]
wire _T_152 = _T_151 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 142:92]
wire _T_153 = _T_152 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 142:118]
wire _T_154 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 142:141]
wire [3:0] _T_160 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 143:164]
wire [3:0] _T_161 = regpred_access_fault_d ? 4'h5 : _T_160; // @[el2_lsu_addrcheck.scala 143:120]
wire [3:0] _T_162 = mpu_access_fault_d ? 4'h3 : _T_161; // @[el2_lsu_addrcheck.scala 143:80]
wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_162; // @[el2_lsu_addrcheck.scala 143:35]
wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 144:61]
wire _T_165 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 145:59]
wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_165; // @[el2_lsu_addrcheck.scala 145:57]
wire _T_166 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 146:90]
wire _T_167 = regcross_misaligned_fault_d | _T_166; // @[el2_lsu_addrcheck.scala 146:57]
wire _T_168 = _T_167 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 146:113]
wire [3:0] _T_172 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 147:80]
wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_172; // @[el2_lsu_addrcheck.scala 147:39]
wire _T_177 = ~start_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 149:66]
wire _T_178 = start_addr_in_dccm_region_d & _T_177; // @[el2_lsu_addrcheck.scala 149:64]
wire _T_179 = ~end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 149:120]
wire _T_180 = end_addr_in_dccm_region_d & _T_179; // @[el2_lsu_addrcheck.scala 149:118]
wire _T_181 = _T_178 | _T_180; // @[el2_lsu_addrcheck.scala 149:88]
wire _T_182 = _T_181 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 149:142]
wire _T_184 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 150:66]
wire _T_185 = ~_T_184; // @[el2_lsu_addrcheck.scala 150:36]
wire _T_186 = _T_185 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 150:95]
reg _T_188; // @[el2_lsu_addrcheck.scala 152:60]
rvrangecheck rvrangecheck ( // @[el2_lsu_addrcheck.scala 45:44]
.io_addr(rvrangecheck_io_addr),
.io_in_range(rvrangecheck_io_in_range),
.io_in_region(rvrangecheck_io_in_region)
);
rvrangecheck rvrangecheck_1 ( // @[el2_lsu_addrcheck.scala 51:44]
.io_addr(rvrangecheck_1_io_addr),
.io_in_range(rvrangecheck_1_io_in_range),
.io_in_region(rvrangecheck_1_io_in_region)
);
rvrangecheck_2 start_addr_pic_rangecheck ( // @[el2_lsu_addrcheck.scala 74:41]
.io_addr(start_addr_pic_rangecheck_io_addr),
.io_in_range(start_addr_pic_rangecheck_io_in_range),
.io_in_region(start_addr_pic_rangecheck_io_in_region)
);
rvrangecheck_2 end_addr_pic_rangecheck ( // @[el2_lsu_addrcheck.scala 80:39]
.io_addr(end_addr_pic_rangecheck_io_addr),
.io_in_range(end_addr_pic_rangecheck_io_in_range),
.io_in_region(end_addr_pic_rangecheck_io_in_region)
);
assign io_is_sideeffects_m = _T_188; // @[el2_lsu_addrcheck.scala 152:50]
assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 87:32]
assign io_addr_in_pic_d = start_addr_pic_rangecheck_io_in_range & end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 88:32]
assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 90:30]
assign io_access_fault_d = _T_153 & _T_154; // @[el2_lsu_addrcheck.scala 142:21]
assign io_misaligned_fault_d = _T_168 & _T_154; // @[el2_lsu_addrcheck.scala 146:25]
assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 148:21]
assign io_fir_dccm_access_error_d = _T_182 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 149:31]
assign io_fir_nondccm_access_error_d = _T_186 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 150:33]
assign rvrangecheck_io_addr = io_start_addr_d; // @[el2_lsu_addrcheck.scala 46:41]
assign rvrangecheck_1_io_addr = io_end_addr_d; // @[el2_lsu_addrcheck.scala 52:41]
assign start_addr_pic_rangecheck_io_addr = io_start_addr_d; // @[el2_lsu_addrcheck.scala 75:37]
assign end_addr_pic_rangecheck_io_addr = io_end_addr_d; // @[el2_lsu_addrcheck.scala 81:35]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_188 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_188 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
if (reset) begin
_T_188 <= 1'h0;
end else begin
_T_188 <= _T_19 & _T_20;
end
end
endmodule

23
el2_lsu_clkdomain.anno.json Normal file
View File

@ -0,0 +1,23 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_clkdomain.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_clkdomain"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

430
el2_lsu_clkdomain.fir Normal file
View File

@ -0,0 +1,430 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_clkdomain :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
module el2_lsu_clkdomain :
input clock : Clock
input reset : UInt<1>
output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:36]
wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:36]
wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 62:36]
wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 63:36]
node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 64:51]
node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 64:70]
node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 65:51]
node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 65:70]
node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 66:51]
node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 66:70]
node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 68:47]
node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 68:66]
node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 69:47]
node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 69:66]
node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 71:49]
node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 71:71]
node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 72:49]
node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 72:71]
node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 73:55]
node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 73:77]
node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 73:107]
node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 74:49]
node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:61]
node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 75:79]
node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 75:98]
node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 76:32]
node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 76:61]
node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 76:79]
node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 78:48]
node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 78:69]
node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 78:90]
node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 78:114]
node _T_17 = or(_T_15, _T_16) @[el2_lsu_clkdomain.scala 78:112]
node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 78:145]
node _T_19 = or(_T_17, _T_18) @[el2_lsu_clkdomain.scala 78:143]
node lsu_free_c1_clken = or(_T_19, io.clk_override) @[el2_lsu_clkdomain.scala 78:169]
node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 79:50]
node lsu_free_c2_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 79:72]
reg _T_21 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:60]
_T_21 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 82:60]
lsu_free_c1_clken_q <= _T_21 @[el2_lsu_clkdomain.scala 82:26]
reg _T_22 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:67]
_T_22 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 84:67]
lsu_c1_d_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 84:26]
reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 85:67]
_T_23 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 85:67]
lsu_c1_m_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 85:26]
reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 86:67]
_T_24 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 86:67]
lsu_c1_r_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 86:26]
inst lsu_c1m_cgc of rvclkhdr @[el2_lsu_clkdomain.scala 88:35]
lsu_c1m_cgc.clock <= clock
lsu_c1m_cgc.reset <= reset
lsu_c1m_cgc.io.en <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 88:77]
io.lsu_c1_m_clk <= lsu_c1m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 88:127]
inst lsu_c1r_cgc of rvclkhdr_1 @[el2_lsu_clkdomain.scala 89:35]
lsu_c1r_cgc.clock <= clock
lsu_c1r_cgc.reset <= reset
lsu_c1r_cgc.io.en <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 89:77]
io.lsu_c1_r_clk <= lsu_c1r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 89:127]
inst lsu_c2m_cgc of rvclkhdr_2 @[el2_lsu_clkdomain.scala 90:35]
lsu_c2m_cgc.clock <= clock
lsu_c2m_cgc.reset <= reset
lsu_c2m_cgc.io.en <= lsu_c2_m_clken @[el2_lsu_clkdomain.scala 90:77]
io.lsu_c2_m_clk <= lsu_c2m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 90:127]
inst lsu_c2r_cgc of rvclkhdr_3 @[el2_lsu_clkdomain.scala 91:35]
lsu_c2r_cgc.clock <= clock
lsu_c2r_cgc.reset <= reset
lsu_c2r_cgc.io.en <= lsu_c2_r_clken @[el2_lsu_clkdomain.scala 91:77]
io.lsu_c2_r_clk <= lsu_c2r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 91:127]
inst lsu_store_c1m_cgc of rvclkhdr_4 @[el2_lsu_clkdomain.scala 92:35]
lsu_store_c1m_cgc.clock <= clock
lsu_store_c1m_cgc.reset <= reset
lsu_store_c1m_cgc.io.en <= lsu_store_c1_m_clken @[el2_lsu_clkdomain.scala 92:77]
io.lsu_store_c1_m_clk <= lsu_store_c1m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 92:127]
inst lsu_store_c1r_cgc of rvclkhdr_5 @[el2_lsu_clkdomain.scala 93:35]
lsu_store_c1r_cgc.clock <= clock
lsu_store_c1r_cgc.reset <= reset
lsu_store_c1r_cgc.io.en <= lsu_store_c1_r_clken @[el2_lsu_clkdomain.scala 93:77]
io.lsu_store_c1_r_clk <= lsu_store_c1r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 93:127]
inst lsu_stbuf_c1_cgc of rvclkhdr_6 @[el2_lsu_clkdomain.scala 94:35]
lsu_stbuf_c1_cgc.clock <= clock
lsu_stbuf_c1_cgc.reset <= reset
lsu_stbuf_c1_cgc.io.en <= lsu_stbuf_c1_clken @[el2_lsu_clkdomain.scala 94:77]
io.lsu_stbuf_c1_clk <= lsu_stbuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 94:127]
inst lsu_bus_ibuf_c1_cgc of rvclkhdr_7 @[el2_lsu_clkdomain.scala 95:35]
lsu_bus_ibuf_c1_cgc.clock <= clock
lsu_bus_ibuf_c1_cgc.reset <= reset
lsu_bus_ibuf_c1_cgc.io.en <= lsu_bus_ibuf_c1_clken @[el2_lsu_clkdomain.scala 95:77]
io.lsu_bus_ibuf_c1_clk <= lsu_bus_ibuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 95:127]
inst lsu_bus_obuf_c1_cgc of rvclkhdr_8 @[el2_lsu_clkdomain.scala 96:35]
lsu_bus_obuf_c1_cgc.clock <= clock
lsu_bus_obuf_c1_cgc.reset <= reset
lsu_bus_obuf_c1_cgc.io.en <= lsu_bus_obuf_c1_clken @[el2_lsu_clkdomain.scala 96:77]
io.lsu_bus_obuf_c1_clk <= lsu_bus_obuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 96:127]
inst lsu_bus_buf_c1_cgc of rvclkhdr_9 @[el2_lsu_clkdomain.scala 97:35]
lsu_bus_buf_c1_cgc.clock <= clock
lsu_bus_buf_c1_cgc.reset <= reset
lsu_bus_buf_c1_cgc.io.en <= lsu_bus_buf_c1_clken @[el2_lsu_clkdomain.scala 97:77]
io.lsu_bus_buf_c1_clk <= lsu_bus_buf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 97:127]
inst lsu_busm_cgc of rvclkhdr_10 @[el2_lsu_clkdomain.scala 98:35]
lsu_busm_cgc.clock <= clock
lsu_busm_cgc.reset <= reset
lsu_busm_cgc.io.en <= io.lsu_bus_clk_en @[el2_lsu_clkdomain.scala 98:77]
io.lsu_busm_clk <= lsu_busm_cgc.io.l1clk @[el2_lsu_clkdomain.scala 98:127]
inst lsu_free_cgc of rvclkhdr_11 @[el2_lsu_clkdomain.scala 99:35]
lsu_free_cgc.clock <= clock
lsu_free_cgc.reset <= reset
lsu_free_cgc.io.en <= lsu_free_c2_clken @[el2_lsu_clkdomain.scala 99:77]
io.lsu_free_c2_clk <= lsu_free_cgc.io.l1clk @[el2_lsu_clkdomain.scala 99:127]
lsu_c1m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 101:30]
lsu_c1m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 101:75]
lsu_c1r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 102:30]
lsu_c1r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 102:75]
lsu_c2m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 103:30]
lsu_c2m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 103:75]
lsu_c2r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 104:30]
lsu_c2r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 104:75]
lsu_store_c1m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 105:30]
lsu_store_c1m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 105:75]
lsu_store_c1r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 106:30]
lsu_store_c1r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 106:75]
lsu_stbuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 107:30]
lsu_stbuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 107:75]
lsu_bus_ibuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 108:30]
lsu_bus_ibuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 108:75]
lsu_bus_obuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 109:30]
lsu_bus_obuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 109:75]
lsu_bus_buf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 110:30]
lsu_bus_buf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 110:75]
lsu_busm_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 111:30]
lsu_busm_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 111:75]
lsu_free_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 112:30]
lsu_free_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 112:75]

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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[beh_lib.scala 330:26]
wire clkhdr_CK; // @[beh_lib.scala 330:26]
wire clkhdr_EN; // @[beh_lib.scala 330:26]
wire clkhdr_SE; // @[beh_lib.scala 330:26]
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 330:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 331:14]
assign clkhdr_CK = io_clk; // @[beh_lib.scala 332:18]
assign clkhdr_EN = io_en; // @[beh_lib.scala 333:18]
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 334:18]
endmodule
module el2_lsu_clkdomain(
input clock,
input reset,
input io_free_clk,
input io_clk_override,
input io_addr_in_dccm_m,
input io_dma_dccm_req,
input io_ldst_stbuf_reqvld_r,
input io_stbuf_reqvld_any,
input io_stbuf_reqvld_flushed_any,
input io_lsu_busreq_r,
input io_lsu_bus_buffer_pend_any,
input io_lsu_bus_buffer_empty_any,
input io_lsu_stbuf_empty_any,
input io_lsu_bus_clk_en,
input io_lsu_p_fast_int,
input io_lsu_p_by,
input io_lsu_p_half,
input io_lsu_p_word,
input io_lsu_p_dword,
input io_lsu_p_load,
input io_lsu_p_store,
input io_lsu_p_unsign,
input io_lsu_p_dma,
input io_lsu_p_store_data_bypass_d,
input io_lsu_p_load_ldst_bypass_d,
input io_lsu_p_store_data_bypass_m,
input io_lsu_p_valid,
input io_lsu_pkt_d_fast_int,
input io_lsu_pkt_d_by,
input io_lsu_pkt_d_half,
input io_lsu_pkt_d_word,
input io_lsu_pkt_d_dword,
input io_lsu_pkt_d_load,
input io_lsu_pkt_d_store,
input io_lsu_pkt_d_unsign,
input io_lsu_pkt_d_dma,
input io_lsu_pkt_d_store_data_bypass_d,
input io_lsu_pkt_d_load_ldst_bypass_d,
input io_lsu_pkt_d_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_r_fast_int,
input io_lsu_pkt_r_by,
input io_lsu_pkt_r_half,
input io_lsu_pkt_r_word,
input io_lsu_pkt_r_dword,
input io_lsu_pkt_r_load,
input io_lsu_pkt_r_store,
input io_lsu_pkt_r_unsign,
input io_lsu_pkt_r_dma,
input io_lsu_pkt_r_store_data_bypass_d,
input io_lsu_pkt_r_load_ldst_bypass_d,
input io_lsu_pkt_r_store_data_bypass_m,
input io_lsu_pkt_r_valid,
output io_lsu_c1_m_clk,
output io_lsu_c1_r_clk,
output io_lsu_c2_m_clk,
output io_lsu_c2_r_clk,
output io_lsu_store_c1_m_clk,
output io_lsu_store_c1_r_clk,
output io_lsu_stbuf_c1_clk,
output io_lsu_bus_obuf_c1_clk,
output io_lsu_bus_ibuf_c1_clk,
output io_lsu_bus_buf_c1_clk,
output io_lsu_busm_clk,
output io_lsu_free_c2_clk,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
wire lsu_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 88:35]
wire lsu_c1m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 88:35]
wire lsu_c1m_cgc_io_en; // @[el2_lsu_clkdomain.scala 88:35]
wire lsu_c1m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 88:35]
wire lsu_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 89:35]
wire lsu_c1r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 89:35]
wire lsu_c1r_cgc_io_en; // @[el2_lsu_clkdomain.scala 89:35]
wire lsu_c1r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 89:35]
wire lsu_c2m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 90:35]
wire lsu_c2m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 90:35]
wire lsu_c2m_cgc_io_en; // @[el2_lsu_clkdomain.scala 90:35]
wire lsu_c2m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 90:35]
wire lsu_c2r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 91:35]
wire lsu_c2r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 91:35]
wire lsu_c2r_cgc_io_en; // @[el2_lsu_clkdomain.scala 91:35]
wire lsu_c2r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 91:35]
wire lsu_store_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 92:35]
wire lsu_store_c1m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 92:35]
wire lsu_store_c1m_cgc_io_en; // @[el2_lsu_clkdomain.scala 92:35]
wire lsu_store_c1m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 92:35]
wire lsu_store_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 93:35]
wire lsu_store_c1r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 93:35]
wire lsu_store_c1r_cgc_io_en; // @[el2_lsu_clkdomain.scala 93:35]
wire lsu_store_c1r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 93:35]
wire lsu_stbuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 94:35]
wire lsu_stbuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 94:35]
wire lsu_stbuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 94:35]
wire lsu_stbuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 94:35]
wire lsu_bus_ibuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 95:35]
wire lsu_bus_ibuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 95:35]
wire lsu_bus_ibuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 95:35]
wire lsu_bus_ibuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 95:35]
wire lsu_bus_obuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 96:35]
wire lsu_bus_obuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 96:35]
wire lsu_bus_obuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 96:35]
wire lsu_bus_obuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 96:35]
wire lsu_bus_buf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 97:35]
wire lsu_bus_buf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 97:35]
wire lsu_bus_buf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 97:35]
wire lsu_bus_buf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 97:35]
wire lsu_busm_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 98:35]
wire lsu_busm_cgc_io_clk; // @[el2_lsu_clkdomain.scala 98:35]
wire lsu_busm_cgc_io_en; // @[el2_lsu_clkdomain.scala 98:35]
wire lsu_busm_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 98:35]
wire lsu_free_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 99:35]
wire lsu_free_cgc_io_clk; // @[el2_lsu_clkdomain.scala 99:35]
wire lsu_free_cgc_io_en; // @[el2_lsu_clkdomain.scala 99:35]
wire lsu_free_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 99:35]
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 64:51]
wire lsu_c1_d_clken = _T | io_clk_override; // @[el2_lsu_clkdomain.scala 64:70]
reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 84:67]
wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 65:51]
wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70]
reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 85:67]
wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 66:51]
wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 66:70]
wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 68:47]
reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 86:67]
wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 69:47]
wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 71:49]
wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 72:49]
wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 73:55]
wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 73:77]
wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:61]
wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 75:79]
wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 76:32]
wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 76:61]
wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 78:48]
wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 78:69]
wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 78:90]
wire _T_17 = _T_15 | _T_11; // @[el2_lsu_clkdomain.scala 78:112]
wire _T_18 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 78:145]
wire _T_19 = _T_17 | _T_18; // @[el2_lsu_clkdomain.scala 78:143]
wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[el2_lsu_clkdomain.scala 78:169]
reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 82:60]
wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 79:50]
rvclkhdr lsu_c1m_cgc ( // @[el2_lsu_clkdomain.scala 88:35]
.io_l1clk(lsu_c1m_cgc_io_l1clk),
.io_clk(lsu_c1m_cgc_io_clk),
.io_en(lsu_c1m_cgc_io_en),
.io_scan_mode(lsu_c1m_cgc_io_scan_mode)
);
rvclkhdr lsu_c1r_cgc ( // @[el2_lsu_clkdomain.scala 89:35]
.io_l1clk(lsu_c1r_cgc_io_l1clk),
.io_clk(lsu_c1r_cgc_io_clk),
.io_en(lsu_c1r_cgc_io_en),
.io_scan_mode(lsu_c1r_cgc_io_scan_mode)
);
rvclkhdr lsu_c2m_cgc ( // @[el2_lsu_clkdomain.scala 90:35]
.io_l1clk(lsu_c2m_cgc_io_l1clk),
.io_clk(lsu_c2m_cgc_io_clk),
.io_en(lsu_c2m_cgc_io_en),
.io_scan_mode(lsu_c2m_cgc_io_scan_mode)
);
rvclkhdr lsu_c2r_cgc ( // @[el2_lsu_clkdomain.scala 91:35]
.io_l1clk(lsu_c2r_cgc_io_l1clk),
.io_clk(lsu_c2r_cgc_io_clk),
.io_en(lsu_c2r_cgc_io_en),
.io_scan_mode(lsu_c2r_cgc_io_scan_mode)
);
rvclkhdr lsu_store_c1m_cgc ( // @[el2_lsu_clkdomain.scala 92:35]
.io_l1clk(lsu_store_c1m_cgc_io_l1clk),
.io_clk(lsu_store_c1m_cgc_io_clk),
.io_en(lsu_store_c1m_cgc_io_en),
.io_scan_mode(lsu_store_c1m_cgc_io_scan_mode)
);
rvclkhdr lsu_store_c1r_cgc ( // @[el2_lsu_clkdomain.scala 93:35]
.io_l1clk(lsu_store_c1r_cgc_io_l1clk),
.io_clk(lsu_store_c1r_cgc_io_clk),
.io_en(lsu_store_c1r_cgc_io_en),
.io_scan_mode(lsu_store_c1r_cgc_io_scan_mode)
);
rvclkhdr lsu_stbuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 94:35]
.io_l1clk(lsu_stbuf_c1_cgc_io_l1clk),
.io_clk(lsu_stbuf_c1_cgc_io_clk),
.io_en(lsu_stbuf_c1_cgc_io_en),
.io_scan_mode(lsu_stbuf_c1_cgc_io_scan_mode)
);
rvclkhdr lsu_bus_ibuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 95:35]
.io_l1clk(lsu_bus_ibuf_c1_cgc_io_l1clk),
.io_clk(lsu_bus_ibuf_c1_cgc_io_clk),
.io_en(lsu_bus_ibuf_c1_cgc_io_en),
.io_scan_mode(lsu_bus_ibuf_c1_cgc_io_scan_mode)
);
rvclkhdr lsu_bus_obuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 96:35]
.io_l1clk(lsu_bus_obuf_c1_cgc_io_l1clk),
.io_clk(lsu_bus_obuf_c1_cgc_io_clk),
.io_en(lsu_bus_obuf_c1_cgc_io_en),
.io_scan_mode(lsu_bus_obuf_c1_cgc_io_scan_mode)
);
rvclkhdr lsu_bus_buf_c1_cgc ( // @[el2_lsu_clkdomain.scala 97:35]
.io_l1clk(lsu_bus_buf_c1_cgc_io_l1clk),
.io_clk(lsu_bus_buf_c1_cgc_io_clk),
.io_en(lsu_bus_buf_c1_cgc_io_en),
.io_scan_mode(lsu_bus_buf_c1_cgc_io_scan_mode)
);
rvclkhdr lsu_busm_cgc ( // @[el2_lsu_clkdomain.scala 98:35]
.io_l1clk(lsu_busm_cgc_io_l1clk),
.io_clk(lsu_busm_cgc_io_clk),
.io_en(lsu_busm_cgc_io_en),
.io_scan_mode(lsu_busm_cgc_io_scan_mode)
);
rvclkhdr lsu_free_cgc ( // @[el2_lsu_clkdomain.scala 99:35]
.io_l1clk(lsu_free_cgc_io_l1clk),
.io_clk(lsu_free_cgc_io_clk),
.io_en(lsu_free_cgc_io_en),
.io_scan_mode(lsu_free_cgc_io_scan_mode)
);
assign io_lsu_c1_m_clk = lsu_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 88:127]
assign io_lsu_c1_r_clk = lsu_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 89:127]
assign io_lsu_c2_m_clk = lsu_c2m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 90:127]
assign io_lsu_c2_r_clk = lsu_c2r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 91:127]
assign io_lsu_store_c1_m_clk = lsu_store_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 92:127]
assign io_lsu_store_c1_r_clk = lsu_store_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 93:127]
assign io_lsu_stbuf_c1_clk = lsu_stbuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 94:127]
assign io_lsu_bus_obuf_c1_clk = lsu_bus_obuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 96:127]
assign io_lsu_bus_ibuf_c1_clk = lsu_bus_ibuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 95:127]
assign io_lsu_bus_buf_c1_clk = lsu_bus_buf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 97:127]
assign io_lsu_busm_clk = lsu_busm_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 98:127]
assign io_lsu_free_c2_clk = lsu_free_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 99:127]
assign lsu_c1m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 101:30]
assign lsu_c1m_cgc_io_en = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 88:77]
assign lsu_c1m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 101:75]
assign lsu_c1r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 102:30]
assign lsu_c1r_cgc_io_en = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 89:77]
assign lsu_c1r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 102:75]
assign lsu_c2m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 103:30]
assign lsu_c2m_cgc_io_en = _T_3 | io_clk_override; // @[el2_lsu_clkdomain.scala 90:77]
assign lsu_c2m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 103:75]
assign lsu_c2r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 104:30]
assign lsu_c2r_cgc_io_en = _T_4 | io_clk_override; // @[el2_lsu_clkdomain.scala 91:77]
assign lsu_c2r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 104:75]
assign lsu_store_c1m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 105:30]
assign lsu_store_c1m_cgc_io_en = _T_5 | io_clk_override; // @[el2_lsu_clkdomain.scala 92:77]
assign lsu_store_c1m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 105:75]
assign lsu_store_c1r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 106:30]
assign lsu_store_c1r_cgc_io_en = _T_6 | io_clk_override; // @[el2_lsu_clkdomain.scala 93:77]
assign lsu_store_c1r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 106:75]
assign lsu_stbuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 107:30]
assign lsu_stbuf_c1_cgc_io_en = _T_8 | io_clk_override; // @[el2_lsu_clkdomain.scala 94:77]
assign lsu_stbuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 107:75]
assign lsu_bus_ibuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 108:30]
assign lsu_bus_ibuf_c1_cgc_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lsu_clkdomain.scala 95:77]
assign lsu_bus_ibuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 108:75]
assign lsu_bus_obuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 109:30]
assign lsu_bus_obuf_c1_cgc_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lsu_clkdomain.scala 96:77]
assign lsu_bus_obuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 109:75]
assign lsu_bus_buf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 110:30]
assign lsu_bus_buf_c1_cgc_io_en = _T_12 | io_clk_override; // @[el2_lsu_clkdomain.scala 97:77]
assign lsu_bus_buf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 110:75]
assign lsu_busm_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 111:30]
assign lsu_busm_cgc_io_en = io_lsu_bus_clk_en; // @[el2_lsu_clkdomain.scala 98:77]
assign lsu_busm_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 111:75]
assign lsu_free_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 112:30]
assign lsu_free_cgc_io_en = _T_20 | io_clk_override; // @[el2_lsu_clkdomain.scala 99:77]
assign lsu_free_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 112:75]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
lsu_c1_d_clken_q = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
lsu_c1_m_clken_q = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
lsu_c1_r_clken_q = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
lsu_free_c1_clken_q = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_free_c2_clk) begin
if (reset) begin
lsu_c1_d_clken_q <= 1'h0;
end else begin
lsu_c1_d_clken_q <= lsu_c1_d_clken;
end
if (reset) begin
lsu_c1_m_clken_q <= 1'h0;
end else begin
lsu_c1_m_clken_q <= lsu_c1_m_clken;
end
if (reset) begin
lsu_c1_r_clken_q <= 1'h0;
end else begin
lsu_c1_r_clken_q <= lsu_c1_r_clken;
end
end
always @(posedge io_free_clk) begin
if (reset) begin
lsu_free_c1_clken_q <= 1'h0;
end else begin
lsu_free_c1_clken_q <= lsu_free_c1_clken;
end
end
endmodule

382
el2_lsu_dccm_ctl.anno.json Normal file
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@ -0,0 +1,382 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wr_data_lo",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wdata_lo",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_ecc_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_ld_data_m",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rd_data",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rdata_hi_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rdata_lo_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_hi",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_mken",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_r",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_hi_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wr_addr_hi",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_lo_r",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wren",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_pic_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_commit_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rdata_lo_m",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_rdata",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rd_data",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_hi_m",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_lo_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rdata_hi_m",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wraddr",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_pic_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_mem_addr",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wr_data",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_pic_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_mem_wdata",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_lo_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_hi_r",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_hi_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rdaddr",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wren",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_ecc_error",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_double_ecc_error_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wr_data_hi",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wdata_hi",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_ecc_any",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_addr_lo",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_double_ecc_error_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_single_ecc_error_lo_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_single_ecc_error_hi_r",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_rvalid",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_dma",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wr_addr_lo",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_mask_data_m",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_rtag",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_mem_tag_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rden",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_addr_hi",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rden",
"sources":[
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_d",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_lsu_dccm_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_dccm_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

845
el2_lsu_dccm_ctl.fir Normal file
View File

@ -0,0 +1,845 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_lsu_dccm_ctl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 330:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 331:14]
clkhdr.CK <= io.clk @[beh_lib.scala 332:18]
clkhdr.EN <= io.en @[beh_lib.scala 333:18]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 334:18]
module el2_lsu_dccm_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip clk : Clock, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_rd_addr_lo : UInt<16>, flip dccm_rd_data_lo : UInt<39>, dccm_wr_addr_hi : UInt<16>, dccm_wr_data_hi : UInt<39>, dccm_rd_addr_hi : UInt<16>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, flip scan_mode : UInt<1>}
node picm_rd_data_m = cat(io.picm_rd_data, io.picm_rd_data) @[Cat.scala 29:58]
node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58]
node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58]
node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58]
node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58]
wire lsu_rdata_r : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 134:32]
wire lsu_rdata_m : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 135:32]
wire lsu_rdata_corr_r : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 136:32]
wire lsu_rdata_corr_m : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 137:32]
wire stbuf_fwddata_r : UInt<64>
stbuf_fwddata_r <= UInt<1>("h00")
wire stbuf_fwdbyteen_r : UInt<64>
stbuf_fwdbyteen_r <= UInt<1>("h00")
wire picm_rd_data_r_32 : UInt<32>
picm_rd_data_r_32 <= UInt<1>("h00")
wire picm_rd_data_r : UInt<64>
picm_rd_data_r <= UInt<1>("h00")
wire lsu_ld_data_corr_m : UInt<64>
lsu_ld_data_corr_m <= UInt<1>("h00")
node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.load) @[el2_lsu_dccm_ctl.scala 168:50]
node _T_1 = and(_T, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 168:70]
io.dccm_dma_rvalid <= _T_1 @[el2_lsu_dccm_ctl.scala 168:28]
io.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[el2_lsu_dccm_ctl.scala 169:28]
node _T_2 = cat(lsu_rdata_corr_m[1], lsu_rdata_corr_m[0]) @[el2_lsu_dccm_ctl.scala 170:48]
node _T_3 = cat(lsu_rdata_corr_m[3], lsu_rdata_corr_m[2]) @[el2_lsu_dccm_ctl.scala 170:48]
node _T_4 = cat(_T_3, _T_2) @[el2_lsu_dccm_ctl.scala 170:48]
node _T_5 = cat(lsu_rdata_corr_m[5], lsu_rdata_corr_m[4]) @[el2_lsu_dccm_ctl.scala 170:48]
node _T_6 = cat(lsu_rdata_corr_m[7], lsu_rdata_corr_m[6]) @[el2_lsu_dccm_ctl.scala 170:48]
node _T_7 = cat(_T_6, _T_5) @[el2_lsu_dccm_ctl.scala 170:48]
node _T_8 = cat(_T_7, _T_4) @[el2_lsu_dccm_ctl.scala 170:48]
io.dccm_dma_rdata <= _T_8 @[el2_lsu_dccm_ctl.scala 170:28]
io.dccm_dma_rtag <= io.dma_mem_tag_m @[el2_lsu_dccm_ctl.scala 171:28]
io.dccm_rdata_lo_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 172:28]
io.dccm_rdata_hi_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 173:28]
io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 174:28]
io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 175:28]
reg _T_9 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 178:65]
_T_9 <= lsu_ld_data_corr_m @[el2_lsu_dccm_ctl.scala 178:65]
io.lsu_ld_data_corr_r <= _T_9 @[el2_lsu_dccm_ctl.scala 178:28]
lsu_rdata_r[0] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[0] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_10 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_11 = bits(_T_10, 0, 0) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_12 = bits(_T_11, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_13 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_14 = bits(_T_13, 7, 0) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_15 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_16 = bits(picm_rd_data_m, 7, 0) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_17 = bits(dccm_rdata_corr_m, 7, 0) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_18 = mux(_T_15, _T_16, _T_17) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_19 = mux(_T_12, _T_14, _T_18) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[0] <= _T_19 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_20 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_21 = bits(_T_20, 0, 0) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_22 = bits(_T_21, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_23 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_24 = bits(_T_23, 7, 0) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_25 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_26 = bits(picm_rd_data_m, 7, 0) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_27 = bits(dccm_rdata_m, 7, 0) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_28 = mux(_T_25, _T_26, _T_27) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_29 = mux(_T_22, _T_24, _T_28) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[0] <= _T_29 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[1] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[1] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_30 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_31 = bits(_T_30, 1, 1) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_32 = bits(_T_31, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_33 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_34 = bits(_T_33, 15, 8) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_35 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_36 = bits(picm_rd_data_m, 15, 8) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_37 = bits(dccm_rdata_corr_m, 15, 8) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_38 = mux(_T_35, _T_36, _T_37) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_39 = mux(_T_32, _T_34, _T_38) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[1] <= _T_39 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_40 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_41 = bits(_T_40, 1, 1) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_42 = bits(_T_41, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_43 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_44 = bits(_T_43, 15, 8) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_45 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_46 = bits(picm_rd_data_m, 15, 8) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_47 = bits(dccm_rdata_m, 15, 8) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_48 = mux(_T_45, _T_46, _T_47) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_49 = mux(_T_42, _T_44, _T_48) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[1] <= _T_49 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[2] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[2] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_50 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_51 = bits(_T_50, 2, 2) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_52 = bits(_T_51, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_53 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_54 = bits(_T_53, 23, 16) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_55 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_56 = bits(picm_rd_data_m, 23, 16) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_57 = bits(dccm_rdata_corr_m, 23, 16) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_58 = mux(_T_55, _T_56, _T_57) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_59 = mux(_T_52, _T_54, _T_58) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[2] <= _T_59 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_60 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_61 = bits(_T_60, 2, 2) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_62 = bits(_T_61, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_63 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_64 = bits(_T_63, 23, 16) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_65 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_66 = bits(picm_rd_data_m, 23, 16) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_67 = bits(dccm_rdata_m, 23, 16) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_68 = mux(_T_65, _T_66, _T_67) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_69 = mux(_T_62, _T_64, _T_68) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[2] <= _T_69 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[3] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[3] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_70 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_71 = bits(_T_70, 3, 3) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_72 = bits(_T_71, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_73 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_74 = bits(_T_73, 31, 24) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_75 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_76 = bits(picm_rd_data_m, 31, 24) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_77 = bits(dccm_rdata_corr_m, 31, 24) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_78 = mux(_T_75, _T_76, _T_77) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_79 = mux(_T_72, _T_74, _T_78) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[3] <= _T_79 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_80 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_81 = bits(_T_80, 3, 3) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_82 = bits(_T_81, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_83 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_84 = bits(_T_83, 31, 24) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_85 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_86 = bits(picm_rd_data_m, 31, 24) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_87 = bits(dccm_rdata_m, 31, 24) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_88 = mux(_T_85, _T_86, _T_87) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_89 = mux(_T_82, _T_84, _T_88) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[3] <= _T_89 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[4] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[4] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_90 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_91 = bits(_T_90, 4, 4) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_92 = bits(_T_91, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_93 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_94 = bits(_T_93, 39, 32) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_95 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_96 = bits(picm_rd_data_m, 39, 32) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_97 = bits(dccm_rdata_corr_m, 39, 32) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_98 = mux(_T_95, _T_96, _T_97) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_99 = mux(_T_92, _T_94, _T_98) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[4] <= _T_99 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_100 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_101 = bits(_T_100, 4, 4) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_102 = bits(_T_101, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_103 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_104 = bits(_T_103, 39, 32) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_105 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_106 = bits(picm_rd_data_m, 39, 32) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_107 = bits(dccm_rdata_m, 39, 32) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_108 = mux(_T_105, _T_106, _T_107) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_109 = mux(_T_102, _T_104, _T_108) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[4] <= _T_109 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[5] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[5] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_110 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_111 = bits(_T_110, 5, 5) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_112 = bits(_T_111, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_113 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_114 = bits(_T_113, 47, 40) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_115 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_116 = bits(picm_rd_data_m, 47, 40) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_117 = bits(dccm_rdata_corr_m, 47, 40) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_118 = mux(_T_115, _T_116, _T_117) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_119 = mux(_T_112, _T_114, _T_118) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[5] <= _T_119 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_120 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_121 = bits(_T_120, 5, 5) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_122 = bits(_T_121, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_123 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_124 = bits(_T_123, 47, 40) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_125 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_126 = bits(picm_rd_data_m, 47, 40) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_127 = bits(dccm_rdata_m, 47, 40) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_128 = mux(_T_125, _T_126, _T_127) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_129 = mux(_T_122, _T_124, _T_128) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[5] <= _T_129 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[6] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[6] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_130 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_131 = bits(_T_130, 6, 6) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_132 = bits(_T_131, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_133 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_134 = bits(_T_133, 55, 48) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_135 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_136 = bits(picm_rd_data_m, 55, 48) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_137 = bits(dccm_rdata_corr_m, 55, 48) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_138 = mux(_T_135, _T_136, _T_137) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_139 = mux(_T_132, _T_134, _T_138) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[6] <= _T_139 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_140 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_141 = bits(_T_140, 6, 6) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_142 = bits(_T_141, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_143 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_144 = bits(_T_143, 55, 48) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_145 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_146 = bits(picm_rd_data_m, 55, 48) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_147 = bits(dccm_rdata_m, 55, 48) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_148 = mux(_T_145, _T_146, _T_147) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_149 = mux(_T_142, _T_144, _T_148) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[6] <= _T_149 @[el2_lsu_dccm_ctl.scala 185:30]
lsu_rdata_r[7] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27]
io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27]
lsu_rdata_corr_r[7] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27]
node _T_150 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_151 = bits(_T_150, 7, 7) @[el2_lsu_dccm_ctl.scala 184:92]
node _T_152 = bits(_T_151, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97]
node _T_153 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_154 = bits(_T_153, 63, 56) @[el2_lsu_dccm_ctl.scala 184:154]
node _T_155 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189]
node _T_156 = bits(picm_rd_data_m, 63, 56) @[el2_lsu_dccm_ctl.scala 184:210]
node _T_157 = bits(dccm_rdata_corr_m, 63, 56) @[el2_lsu_dccm_ctl.scala 184:241]
node _T_158 = mux(_T_155, _T_156, _T_157) @[el2_lsu_dccm_ctl.scala 184:171]
node _T_159 = mux(_T_152, _T_154, _T_158) @[el2_lsu_dccm_ctl.scala 184:36]
lsu_rdata_corr_m[7] <= _T_159 @[el2_lsu_dccm_ctl.scala 184:30]
node _T_160 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
node _T_161 = bits(_T_160, 7, 7) @[el2_lsu_dccm_ctl.scala 185:92]
node _T_162 = bits(_T_161, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97]
node _T_163 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
node _T_164 = bits(_T_163, 63, 56) @[el2_lsu_dccm_ctl.scala 185:154]
node _T_165 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189]
node _T_166 = bits(picm_rd_data_m, 63, 56) @[el2_lsu_dccm_ctl.scala 185:210]
node _T_167 = bits(dccm_rdata_m, 63, 56) @[el2_lsu_dccm_ctl.scala 185:236]
node _T_168 = mux(_T_165, _T_166, _T_167) @[el2_lsu_dccm_ctl.scala 185:171]
node _T_169 = mux(_T_162, _T_164, _T_168) @[el2_lsu_dccm_ctl.scala 185:36]
lsu_rdata_m[7] <= _T_169 @[el2_lsu_dccm_ctl.scala 185:30]
node _T_170 = cat(lsu_rdata_m[1], lsu_rdata_m[0]) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_171 = cat(lsu_rdata_m[3], lsu_rdata_m[2]) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_172 = cat(_T_171, _T_170) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_173 = cat(lsu_rdata_m[5], lsu_rdata_m[4]) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_174 = cat(lsu_rdata_m[7], lsu_rdata_m[6]) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_175 = cat(_T_174, _T_173) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_176 = cat(_T_175, _T_172) @[el2_lsu_dccm_ctl.scala 186:43]
node _T_177 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 186:70]
node _T_178 = mul(UInt<4>("h08"), _T_177) @[el2_lsu_dccm_ctl.scala 186:56]
node _T_179 = dshr(_T_176, _T_178) @[el2_lsu_dccm_ctl.scala 186:50]
io.lsu_ld_data_m <= _T_179 @[el2_lsu_dccm_ctl.scala 186:28]
node _T_180 = cat(lsu_rdata_corr_m[1], lsu_rdata_corr_m[0]) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_181 = cat(lsu_rdata_corr_m[3], lsu_rdata_corr_m[2]) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_182 = cat(_T_181, _T_180) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_183 = cat(lsu_rdata_corr_m[5], lsu_rdata_corr_m[4]) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_184 = cat(lsu_rdata_corr_m[7], lsu_rdata_corr_m[6]) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_185 = cat(_T_184, _T_183) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_186 = cat(_T_185, _T_182) @[el2_lsu_dccm_ctl.scala 187:48]
node _T_187 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 187:75]
node _T_188 = mul(UInt<4>("h08"), _T_187) @[el2_lsu_dccm_ctl.scala 187:61]
node _T_189 = dshr(_T_186, _T_188) @[el2_lsu_dccm_ctl.scala 187:55]
lsu_ld_data_corr_m <= _T_189 @[el2_lsu_dccm_ctl.scala 187:28]
node _T_190 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 190:44]
node _T_191 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 190:81]
node _T_192 = eq(_T_190, _T_191) @[el2_lsu_dccm_ctl.scala 190:64]
node _T_193 = bits(io.end_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 190:125]
node _T_194 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 190:162]
node _T_195 = eq(_T_193, _T_194) @[el2_lsu_dccm_ctl.scala 190:145]
node _T_196 = or(_T_192, _T_195) @[el2_lsu_dccm_ctl.scala 190:109]
node _T_197 = and(_T_196, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 190:191]
node _T_198 = and(_T_197, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 190:212]
node _T_199 = and(_T_198, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 190:233]
node _T_200 = and(_T_199, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 190:252]
node _T_201 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 191:21]
node _T_202 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 191:58]
node _T_203 = eq(_T_201, _T_202) @[el2_lsu_dccm_ctl.scala 191:41]
node _T_204 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 191:102]
node _T_205 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 191:139]
node _T_206 = eq(_T_204, _T_205) @[el2_lsu_dccm_ctl.scala 191:122]
node _T_207 = or(_T_203, _T_206) @[el2_lsu_dccm_ctl.scala 191:86]
node _T_208 = and(_T_207, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 191:168]
node _T_209 = and(_T_208, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 191:189]
node _T_210 = and(_T_209, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 191:210]
node _T_211 = and(_T_210, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 191:229]
node kill_ecc_corr_lo_r = or(_T_200, _T_211) @[el2_lsu_dccm_ctl.scala 190:273]
node _T_212 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 192:44]
node _T_213 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 192:81]
node _T_214 = eq(_T_212, _T_213) @[el2_lsu_dccm_ctl.scala 192:64]
node _T_215 = bits(io.end_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 192:125]
node _T_216 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 192:162]
node _T_217 = eq(_T_215, _T_216) @[el2_lsu_dccm_ctl.scala 192:145]
node _T_218 = or(_T_214, _T_217) @[el2_lsu_dccm_ctl.scala 192:109]
node _T_219 = and(_T_218, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 192:191]
node _T_220 = and(_T_219, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 192:212]
node _T_221 = and(_T_220, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 192:233]
node _T_222 = and(_T_221, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 192:252]
node _T_223 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 193:21]
node _T_224 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 193:58]
node _T_225 = eq(_T_223, _T_224) @[el2_lsu_dccm_ctl.scala 193:41]
node _T_226 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 193:102]
node _T_227 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 193:139]
node _T_228 = eq(_T_226, _T_227) @[el2_lsu_dccm_ctl.scala 193:122]
node _T_229 = or(_T_225, _T_228) @[el2_lsu_dccm_ctl.scala 193:86]
node _T_230 = and(_T_229, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 193:168]
node _T_231 = and(_T_230, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 193:189]
node _T_232 = and(_T_231, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 193:210]
node _T_233 = and(_T_232, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 193:229]
node kill_ecc_corr_hi_r = or(_T_222, _T_233) @[el2_lsu_dccm_ctl.scala 192:273]
node _T_234 = and(io.lsu_pkt_r.load, io.single_ecc_error_lo_r) @[el2_lsu_dccm_ctl.scala 194:55]
node _T_235 = not(io.lsu_raw_fwd_lo_r) @[el2_lsu_dccm_ctl.scala 194:84]
node ld_single_ecc_error_lo_r = and(_T_234, _T_235) @[el2_lsu_dccm_ctl.scala 194:82]
node _T_236 = and(io.lsu_pkt_r.load, io.single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 195:55]
node _T_237 = not(io.lsu_raw_fwd_hi_r) @[el2_lsu_dccm_ctl.scala 195:84]
node ld_single_ecc_error_hi_r = and(_T_236, _T_237) @[el2_lsu_dccm_ctl.scala 195:82]
node _T_238 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 196:62]
node _T_239 = not(io.lsu_double_ecc_error_r) @[el2_lsu_dccm_ctl.scala 196:92]
node _T_240 = and(_T_238, _T_239) @[el2_lsu_dccm_ctl.scala 196:90]
io.ld_single_ecc_error_r <= _T_240 @[el2_lsu_dccm_ctl.scala 196:33]
node _T_241 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 197:81]
node _T_242 = and(ld_single_ecc_error_lo_r, _T_241) @[el2_lsu_dccm_ctl.scala 197:62]
node _T_243 = not(kill_ecc_corr_lo_r) @[el2_lsu_dccm_ctl.scala 197:103]
node ld_single_ecc_error_lo_r_ns = and(_T_242, _T_243) @[el2_lsu_dccm_ctl.scala 197:101]
node _T_244 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 198:81]
node _T_245 = and(ld_single_ecc_error_hi_r, _T_244) @[el2_lsu_dccm_ctl.scala 198:62]
node _T_246 = not(kill_ecc_corr_hi_r) @[el2_lsu_dccm_ctl.scala 198:103]
node ld_single_ecc_error_hi_r_ns = and(_T_245, _T_246) @[el2_lsu_dccm_ctl.scala 198:101]
reg lsu_double_ecc_error_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 200:74]
lsu_double_ecc_error_r_ff <= io.lsu_double_ecc_error_r @[el2_lsu_dccm_ctl.scala 200:74]
reg ld_single_ecc_error_hi_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 201:74]
ld_single_ecc_error_hi_r_ff <= ld_single_ecc_error_hi_r_ns @[el2_lsu_dccm_ctl.scala 201:74]
reg ld_single_ecc_error_lo_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 202:74]
ld_single_ecc_error_lo_r_ff <= ld_single_ecc_error_lo_r_ns @[el2_lsu_dccm_ctl.scala 202:74]
node _T_247 = bits(io.end_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 206:49]
node _T_248 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 206:94]
node _T_249 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 206:121]
inst rvclkhdr of rvclkhdr @[beh_lib.scala 350:21]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= io.clk @[beh_lib.scala 352:16]
rvclkhdr.io.en <= _T_248 @[beh_lib.scala 353:15]
rvclkhdr.io.scan_mode <= _T_249 @[beh_lib.scala 354:22]
reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 356:14]
ld_sec_addr_hi_r_ff <= _T_247 @[beh_lib.scala 356:14]
node _T_250 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 207:49]
node _T_251 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 207:94]
node _T_252 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 207:121]
inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 350:21]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= io.clk @[beh_lib.scala 352:16]
rvclkhdr_1.io.en <= _T_251 @[beh_lib.scala 353:15]
rvclkhdr_1.io.scan_mode <= _T_252 @[beh_lib.scala 354:22]
reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 356:14]
ld_sec_addr_lo_r_ff <= _T_250 @[beh_lib.scala 356:14]
node _T_253 = or(io.lsu_pkt_d.word, io.lsu_pkt_d.dword) @[el2_lsu_dccm_ctl.scala 208:110]
node _T_254 = not(_T_253) @[el2_lsu_dccm_ctl.scala 208:90]
node _T_255 = bits(io.lsu_addr_d, 1, 0) @[el2_lsu_dccm_ctl.scala 208:148]
node _T_256 = neq(_T_255, UInt<2>("h00")) @[el2_lsu_dccm_ctl.scala 208:154]
node _T_257 = or(_T_254, _T_256) @[el2_lsu_dccm_ctl.scala 208:132]
node _T_258 = and(io.lsu_pkt_d.store, _T_257) @[el2_lsu_dccm_ctl.scala 208:87]
node _T_259 = or(io.lsu_pkt_d.load, _T_258) @[el2_lsu_dccm_ctl.scala 208:65]
node _T_260 = and(io.lsu_pkt_d.valid, _T_259) @[el2_lsu_dccm_ctl.scala 208:44]
node lsu_dccm_rden_d = and(_T_260, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 208:171]
node _T_261 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[el2_lsu_dccm_ctl.scala 211:63]
node _T_262 = not(lsu_double_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 211:96]
node _T_263 = and(_T_261, _T_262) @[el2_lsu_dccm_ctl.scala 211:94]
io.ld_single_ecc_error_r_ff <= _T_263 @[el2_lsu_dccm_ctl.scala 211:31]
node _T_264 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[el2_lsu_dccm_ctl.scala 212:71]
node _T_265 = or(_T_264, io.ld_single_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 212:89]
node _T_266 = not(_T_265) @[el2_lsu_dccm_ctl.scala 212:53]
node _T_267 = bits(io.stbuf_addr_any, 3, 2) @[el2_lsu_dccm_ctl.scala 213:44]
node _T_268 = bits(io.lsu_addr_d, 3, 2) @[el2_lsu_dccm_ctl.scala 213:124]
node _T_269 = eq(_T_267, _T_268) @[el2_lsu_dccm_ctl.scala 213:107]
node _T_270 = bits(io.stbuf_addr_any, 3, 2) @[el2_lsu_dccm_ctl.scala 214:25]
node _T_271 = bits(io.end_addr_d, 3, 2) @[el2_lsu_dccm_ctl.scala 214:105]
node _T_272 = eq(_T_270, _T_271) @[el2_lsu_dccm_ctl.scala 214:88]
node _T_273 = or(_T_269, _T_272) @[el2_lsu_dccm_ctl.scala 213:195]
node _T_274 = not(_T_273) @[el2_lsu_dccm_ctl.scala 213:24]
node _T_275 = and(lsu_dccm_rden_d, _T_274) @[el2_lsu_dccm_ctl.scala 213:22]
node _T_276 = or(_T_266, _T_275) @[el2_lsu_dccm_ctl.scala 212:120]
node _T_277 = and(io.stbuf_reqvld_any, _T_276) @[el2_lsu_dccm_ctl.scala 212:50]
io.lsu_stbuf_commit_any <= _T_277 @[el2_lsu_dccm_ctl.scala 212:27]
node _T_278 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[el2_lsu_dccm_ctl.scala 217:41]
node _T_279 = or(_T_278, io.ld_single_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 217:67]
io.dccm_wren <= _T_279 @[el2_lsu_dccm_ctl.scala 217:22]
node _T_280 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 218:41]
io.dccm_rden <= _T_280 @[el2_lsu_dccm_ctl.scala 218:22]
node _T_281 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 219:57]
node _T_282 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 220:36]
node _T_283 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 220:62]
node _T_284 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 220:101]
node _T_285 = mux(_T_282, _T_283, _T_284) @[el2_lsu_dccm_ctl.scala 220:8]
node _T_286 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 221:25]
node _T_287 = bits(io.lsu_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 221:45]
node _T_288 = bits(io.stbuf_addr_any, 15, 0) @[el2_lsu_dccm_ctl.scala 221:82]
node _T_289 = mux(_T_286, _T_287, _T_288) @[el2_lsu_dccm_ctl.scala 221:8]
node _T_290 = mux(_T_281, _T_285, _T_289) @[el2_lsu_dccm_ctl.scala 219:28]
io.dccm_wr_addr_lo <= _T_290 @[el2_lsu_dccm_ctl.scala 219:22]
node _T_291 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 222:57]
node _T_292 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 223:36]
node _T_293 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 223:63]
node _T_294 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 223:103]
node _T_295 = mux(_T_292, _T_293, _T_294) @[el2_lsu_dccm_ctl.scala 223:8]
node _T_296 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 224:25]
node _T_297 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 224:46]
node _T_298 = bits(io.stbuf_addr_any, 15, 0) @[el2_lsu_dccm_ctl.scala 224:83]
node _T_299 = mux(_T_296, _T_297, _T_298) @[el2_lsu_dccm_ctl.scala 224:8]
node _T_300 = mux(_T_291, _T_295, _T_299) @[el2_lsu_dccm_ctl.scala 222:28]
io.dccm_wr_addr_hi <= _T_300 @[el2_lsu_dccm_ctl.scala 222:22]
node _T_301 = bits(io.lsu_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 225:38]
io.dccm_rd_addr_lo <= _T_301 @[el2_lsu_dccm_ctl.scala 225:22]
node _T_302 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 226:38]
io.dccm_rd_addr_hi <= _T_302 @[el2_lsu_dccm_ctl.scala 226:22]
node _T_303 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 227:57]
node _T_304 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 228:36]
node _T_305 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 228:70]
node _T_306 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 228:114]
node _T_307 = cat(_T_305, _T_306) @[Cat.scala 29:58]
node _T_308 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 229:34]
node _T_309 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 229:78]
node _T_310 = cat(_T_308, _T_309) @[Cat.scala 29:58]
node _T_311 = mux(_T_304, _T_307, _T_310) @[el2_lsu_dccm_ctl.scala 228:8]
node _T_312 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 230:25]
node _T_313 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[el2_lsu_dccm_ctl.scala 230:60]
node _T_314 = bits(io.dma_dccm_wdata_lo, 31, 0) @[el2_lsu_dccm_ctl.scala 230:105]
node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58]
node _T_316 = bits(io.stbuf_ecc_any, 6, 0) @[el2_lsu_dccm_ctl.scala 231:27]
node _T_317 = bits(io.stbuf_data_any, 31, 0) @[el2_lsu_dccm_ctl.scala 231:69]
node _T_318 = cat(_T_316, _T_317) @[Cat.scala 29:58]
node _T_319 = mux(_T_312, _T_315, _T_318) @[el2_lsu_dccm_ctl.scala 230:8]
node _T_320 = mux(_T_303, _T_311, _T_319) @[el2_lsu_dccm_ctl.scala 227:28]
io.dccm_wr_data_lo <= _T_320 @[el2_lsu_dccm_ctl.scala 227:22]
node _T_321 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 233:57]
node _T_322 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 234:36]
node _T_323 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 234:71]
node _T_324 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 234:115]
node _T_325 = cat(_T_323, _T_324) @[Cat.scala 29:58]
node _T_326 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 235:34]
node _T_327 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 235:78]
node _T_328 = cat(_T_326, _T_327) @[Cat.scala 29:58]
node _T_329 = mux(_T_322, _T_325, _T_328) @[el2_lsu_dccm_ctl.scala 234:8]
node _T_330 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 236:25]
node _T_331 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[el2_lsu_dccm_ctl.scala 236:61]
node _T_332 = bits(io.dma_dccm_wdata_hi, 31, 0) @[el2_lsu_dccm_ctl.scala 236:106]
node _T_333 = cat(_T_331, _T_332) @[Cat.scala 29:58]
node _T_334 = bits(io.stbuf_ecc_any, 6, 0) @[el2_lsu_dccm_ctl.scala 237:27]
node _T_335 = bits(io.stbuf_data_any, 31, 0) @[el2_lsu_dccm_ctl.scala 237:69]
node _T_336 = cat(_T_334, _T_335) @[Cat.scala 29:58]
node _T_337 = mux(_T_330, _T_333, _T_336) @[el2_lsu_dccm_ctl.scala 236:8]
node _T_338 = mux(_T_321, _T_329, _T_337) @[el2_lsu_dccm_ctl.scala 233:28]
io.dccm_wr_data_hi <= _T_338 @[el2_lsu_dccm_ctl.scala 233:22]
node _T_339 = bits(io.lsu_pkt_m.store, 0, 0) @[Bitwise.scala 72:15]
node _T_340 = mux(_T_339, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_341 = bits(io.lsu_pkt_m.by, 0, 0) @[Bitwise.scala 72:15]
node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_343 = and(_T_342, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 240:84]
node _T_344 = bits(io.lsu_pkt_m.half, 0, 0) @[Bitwise.scala 72:15]
node _T_345 = mux(_T_344, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_346 = and(_T_345, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 241:33]
node _T_347 = or(_T_343, _T_346) @[el2_lsu_dccm_ctl.scala 240:97]
node _T_348 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15]
node _T_349 = mux(_T_348, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_350 = and(_T_349, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 242:33]
node _T_351 = or(_T_347, _T_350) @[el2_lsu_dccm_ctl.scala 241:46]
node store_byteen_m = and(_T_340, _T_351) @[el2_lsu_dccm_ctl.scala 240:53]
node _T_352 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15]
node _T_353 = mux(_T_352, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_354 = bits(io.lsu_pkt_r.by, 0, 0) @[Bitwise.scala 72:15]
node _T_355 = mux(_T_354, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_356 = and(_T_355, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 243:84]
node _T_357 = bits(io.lsu_pkt_r.half, 0, 0) @[Bitwise.scala 72:15]
node _T_358 = mux(_T_357, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_359 = and(_T_358, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 244:33]
node _T_360 = or(_T_356, _T_359) @[el2_lsu_dccm_ctl.scala 243:97]
node _T_361 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15]
node _T_362 = mux(_T_361, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_363 = and(_T_362, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 245:33]
node _T_364 = or(_T_360, _T_363) @[el2_lsu_dccm_ctl.scala 244:46]
node store_byteen_r = and(_T_353, _T_364) @[el2_lsu_dccm_ctl.scala 243:53]
node _T_365 = bits(store_byteen_m, 3, 0) @[el2_lsu_dccm_ctl.scala 246:55]
node _T_366 = cat(UInt<4>("h00"), _T_365) @[Cat.scala 29:58]
node _T_367 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 246:78]
node store_byteen_ext_m = dshl(_T_366, _T_367) @[el2_lsu_dccm_ctl.scala 246:62]
node _T_368 = bits(store_byteen_r, 3, 0) @[el2_lsu_dccm_ctl.scala 247:55]
node _T_369 = cat(UInt<4>("h00"), _T_368) @[Cat.scala 29:58]
node _T_370 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 247:78]
node store_byteen_ext_r = dshl(_T_369, _T_370) @[el2_lsu_dccm_ctl.scala 247:62]
node _T_371 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 250:51]
node _T_372 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 250:88]
node _T_373 = eq(_T_371, _T_372) @[el2_lsu_dccm_ctl.scala 250:71]
node dccm_wr_bypass_d_m_lo = and(_T_373, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 250:109]
node _T_374 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 251:51]
node _T_375 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 251:88]
node _T_376 = eq(_T_374, _T_375) @[el2_lsu_dccm_ctl.scala 251:71]
node dccm_wr_bypass_d_m_hi = and(_T_376, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 251:109]
node _T_377 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 253:51]
node _T_378 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 253:88]
node _T_379 = eq(_T_377, _T_378) @[el2_lsu_dccm_ctl.scala 253:71]
node dccm_wr_bypass_d_r_lo = and(_T_379, io.addr_in_dccm_r) @[el2_lsu_dccm_ctl.scala 253:109]
node _T_380 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 254:51]
node _T_381 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 254:88]
node _T_382 = eq(_T_380, _T_381) @[el2_lsu_dccm_ctl.scala 254:71]
node dccm_wr_bypass_d_r_hi = and(_T_382, io.addr_in_dccm_r) @[el2_lsu_dccm_ctl.scala 254:109]
wire dccm_wr_bypass_d_m_hi_Q : UInt<1>
dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00")
wire dccm_wr_bypass_d_m_lo_Q : UInt<1>
dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00")
wire dccm_wren_Q : UInt<1>
dccm_wren_Q <= UInt<1>("h00")
wire dccm_wr_data_Q : UInt<32>
dccm_wr_data_Q <= UInt<32>("h00")
wire store_data_pre_r : UInt<64>
store_data_pre_r <= UInt<64>("h00")
wire store_data_pre_hi_r : UInt<32>
store_data_pre_hi_r <= UInt<32>("h00")
wire store_data_pre_lo_r : UInt<32>
store_data_pre_lo_r <= UInt<32>("h00")
wire store_data_pre_m : UInt<64>
store_data_pre_m <= UInt<64>("h00")
wire store_data_hi_m : UInt<32>
store_data_hi_m <= UInt<32>("h00")
wire store_data_lo_m : UInt<32>
store_data_lo_m <= UInt<32>("h00")
node _T_383 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_384 = bits(io.store_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 287:64]
node _T_385 = cat(_T_383, _T_384) @[Cat.scala 29:58]
node _T_386 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 287:92]
node _T_387 = mul(UInt<4>("h08"), _T_386) @[el2_lsu_dccm_ctl.scala 287:78]
node _T_388 = dshl(_T_385, _T_387) @[el2_lsu_dccm_ctl.scala 287:72]
store_data_pre_m <= _T_388 @[el2_lsu_dccm_ctl.scala 287:29]
node _T_389 = bits(store_data_pre_m, 63, 32) @[el2_lsu_dccm_ctl.scala 288:48]
store_data_hi_m <= _T_389 @[el2_lsu_dccm_ctl.scala 288:29]
node _T_390 = bits(store_data_pre_m, 31, 0) @[el2_lsu_dccm_ctl.scala 289:48]
store_data_lo_m <= _T_390 @[el2_lsu_dccm_ctl.scala 289:29]
node _T_391 = bits(store_byteen_ext_m, 0, 0) @[el2_lsu_dccm_ctl.scala 290:123]
node _T_392 = bits(_T_391, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127]
node _T_393 = bits(store_data_lo_m, 7, 0) @[el2_lsu_dccm_ctl.scala 290:151]
node _T_394 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195]
node _T_395 = bits(_T_394, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221]
node _T_396 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 290:246]
node _T_397 = bits(io.sec_data_lo_m, 7, 0) @[el2_lsu_dccm_ctl.scala 290:276]
node _T_398 = mux(_T_395, _T_396, _T_397) @[el2_lsu_dccm_ctl.scala 290:169]
node _T_399 = mux(_T_392, _T_393, _T_398) @[el2_lsu_dccm_ctl.scala 290:104]
node _T_400 = bits(store_byteen_ext_m, 1, 1) @[el2_lsu_dccm_ctl.scala 290:123]
node _T_401 = bits(_T_400, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127]
node _T_402 = bits(store_data_lo_m, 15, 8) @[el2_lsu_dccm_ctl.scala 290:151]
node _T_403 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195]
node _T_404 = bits(_T_403, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221]
node _T_405 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 290:246]
node _T_406 = bits(io.sec_data_lo_m, 15, 8) @[el2_lsu_dccm_ctl.scala 290:276]
node _T_407 = mux(_T_404, _T_405, _T_406) @[el2_lsu_dccm_ctl.scala 290:169]
node _T_408 = mux(_T_401, _T_402, _T_407) @[el2_lsu_dccm_ctl.scala 290:104]
node _T_409 = bits(store_byteen_ext_m, 2, 2) @[el2_lsu_dccm_ctl.scala 290:123]
node _T_410 = bits(_T_409, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127]
node _T_411 = bits(store_data_lo_m, 23, 16) @[el2_lsu_dccm_ctl.scala 290:151]
node _T_412 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195]
node _T_413 = bits(_T_412, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221]
node _T_414 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 290:246]
node _T_415 = bits(io.sec_data_lo_m, 23, 16) @[el2_lsu_dccm_ctl.scala 290:276]
node _T_416 = mux(_T_413, _T_414, _T_415) @[el2_lsu_dccm_ctl.scala 290:169]
node _T_417 = mux(_T_410, _T_411, _T_416) @[el2_lsu_dccm_ctl.scala 290:104]
node _T_418 = bits(store_byteen_ext_m, 3, 3) @[el2_lsu_dccm_ctl.scala 290:123]
node _T_419 = bits(_T_418, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127]
node _T_420 = bits(store_data_lo_m, 31, 24) @[el2_lsu_dccm_ctl.scala 290:151]
node _T_421 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195]
node _T_422 = bits(_T_421, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221]
node _T_423 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 290:246]
node _T_424 = bits(io.sec_data_lo_m, 31, 24) @[el2_lsu_dccm_ctl.scala 290:276]
node _T_425 = mux(_T_422, _T_423, _T_424) @[el2_lsu_dccm_ctl.scala 290:169]
node _T_426 = mux(_T_419, _T_420, _T_425) @[el2_lsu_dccm_ctl.scala 290:104]
wire _T_427 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 290:96]
_T_427[0] <= _T_399 @[el2_lsu_dccm_ctl.scala 290:96]
_T_427[1] <= _T_408 @[el2_lsu_dccm_ctl.scala 290:96]
_T_427[2] <= _T_417 @[el2_lsu_dccm_ctl.scala 290:96]
_T_427[3] <= _T_426 @[el2_lsu_dccm_ctl.scala 290:96]
node _T_428 = cat(_T_427[2], _T_427[3]) @[Cat.scala 29:58]
node _T_429 = cat(_T_427[0], _T_427[1]) @[Cat.scala 29:58]
node _T_430 = cat(_T_429, _T_428) @[Cat.scala 29:58]
reg _T_431 : UInt, io.lsu_store_c1_r_clk @[el2_lsu_dccm_ctl.scala 290:72]
_T_431 <= _T_430 @[el2_lsu_dccm_ctl.scala 290:72]
io.store_data_lo_r <= _T_431 @[el2_lsu_dccm_ctl.scala 290:29]
node _T_432 = bits(store_byteen_ext_m, 4, 4) @[el2_lsu_dccm_ctl.scala 291:123]
node _T_433 = bits(_T_432, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129]
node _T_434 = bits(store_data_hi_m, 7, 0) @[el2_lsu_dccm_ctl.scala 291:151]
node _T_435 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195]
node _T_436 = bits(_T_435, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221]
node _T_437 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 291:246]
node _T_438 = bits(io.sec_data_hi_m, 7, 0) @[el2_lsu_dccm_ctl.scala 291:276]
node _T_439 = mux(_T_436, _T_437, _T_438) @[el2_lsu_dccm_ctl.scala 291:169]
node _T_440 = mux(_T_433, _T_434, _T_439) @[el2_lsu_dccm_ctl.scala 291:104]
node _T_441 = bits(store_byteen_ext_m, 5, 5) @[el2_lsu_dccm_ctl.scala 291:123]
node _T_442 = bits(_T_441, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129]
node _T_443 = bits(store_data_hi_m, 15, 8) @[el2_lsu_dccm_ctl.scala 291:151]
node _T_444 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195]
node _T_445 = bits(_T_444, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221]
node _T_446 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 291:246]
node _T_447 = bits(io.sec_data_hi_m, 15, 8) @[el2_lsu_dccm_ctl.scala 291:276]
node _T_448 = mux(_T_445, _T_446, _T_447) @[el2_lsu_dccm_ctl.scala 291:169]
node _T_449 = mux(_T_442, _T_443, _T_448) @[el2_lsu_dccm_ctl.scala 291:104]
node _T_450 = bits(store_byteen_ext_m, 6, 6) @[el2_lsu_dccm_ctl.scala 291:123]
node _T_451 = bits(_T_450, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129]
node _T_452 = bits(store_data_hi_m, 23, 16) @[el2_lsu_dccm_ctl.scala 291:151]
node _T_453 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195]
node _T_454 = bits(_T_453, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221]
node _T_455 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 291:246]
node _T_456 = bits(io.sec_data_hi_m, 23, 16) @[el2_lsu_dccm_ctl.scala 291:276]
node _T_457 = mux(_T_454, _T_455, _T_456) @[el2_lsu_dccm_ctl.scala 291:169]
node _T_458 = mux(_T_451, _T_452, _T_457) @[el2_lsu_dccm_ctl.scala 291:104]
node _T_459 = bits(store_byteen_ext_m, 7, 7) @[el2_lsu_dccm_ctl.scala 291:123]
node _T_460 = bits(_T_459, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129]
node _T_461 = bits(store_data_hi_m, 31, 24) @[el2_lsu_dccm_ctl.scala 291:151]
node _T_462 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195]
node _T_463 = bits(_T_462, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221]
node _T_464 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 291:246]
node _T_465 = bits(io.sec_data_hi_m, 31, 24) @[el2_lsu_dccm_ctl.scala 291:276]
node _T_466 = mux(_T_463, _T_464, _T_465) @[el2_lsu_dccm_ctl.scala 291:169]
node _T_467 = mux(_T_460, _T_461, _T_466) @[el2_lsu_dccm_ctl.scala 291:104]
wire _T_468 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 291:96]
_T_468[0] <= _T_440 @[el2_lsu_dccm_ctl.scala 291:96]
_T_468[1] <= _T_449 @[el2_lsu_dccm_ctl.scala 291:96]
_T_468[2] <= _T_458 @[el2_lsu_dccm_ctl.scala 291:96]
_T_468[3] <= _T_467 @[el2_lsu_dccm_ctl.scala 291:96]
node _T_469 = cat(_T_468[2], _T_468[3]) @[Cat.scala 29:58]
node _T_470 = cat(_T_468[0], _T_468[1]) @[Cat.scala 29:58]
node _T_471 = cat(_T_470, _T_469) @[Cat.scala 29:58]
reg _T_472 : UInt, io.lsu_store_c1_r_clk @[el2_lsu_dccm_ctl.scala 291:72]
_T_472 <= _T_471 @[el2_lsu_dccm_ctl.scala 291:72]
io.store_data_hi_r <= _T_472 @[el2_lsu_dccm_ctl.scala 291:29]
node _T_473 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89]
node _T_474 = bits(store_byteen_ext_r, 0, 0) @[el2_lsu_dccm_ctl.scala 292:134]
node _T_475 = not(_T_474) @[el2_lsu_dccm_ctl.scala 292:115]
node _T_476 = and(_T_473, _T_475) @[el2_lsu_dccm_ctl.scala 292:113]
node _T_477 = bits(_T_476, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139]
node _T_478 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 292:163]
node _T_479 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_dccm_ctl.scala 292:195]
node _T_480 = mux(_T_477, _T_478, _T_479) @[el2_lsu_dccm_ctl.scala 292:63]
node _T_481 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89]
node _T_482 = bits(store_byteen_ext_r, 1, 1) @[el2_lsu_dccm_ctl.scala 292:134]
node _T_483 = not(_T_482) @[el2_lsu_dccm_ctl.scala 292:115]
node _T_484 = and(_T_481, _T_483) @[el2_lsu_dccm_ctl.scala 292:113]
node _T_485 = bits(_T_484, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139]
node _T_486 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 292:163]
node _T_487 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_dccm_ctl.scala 292:195]
node _T_488 = mux(_T_485, _T_486, _T_487) @[el2_lsu_dccm_ctl.scala 292:63]
node _T_489 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89]
node _T_490 = bits(store_byteen_ext_r, 2, 2) @[el2_lsu_dccm_ctl.scala 292:134]
node _T_491 = not(_T_490) @[el2_lsu_dccm_ctl.scala 292:115]
node _T_492 = and(_T_489, _T_491) @[el2_lsu_dccm_ctl.scala 292:113]
node _T_493 = bits(_T_492, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139]
node _T_494 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 292:163]
node _T_495 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_dccm_ctl.scala 292:195]
node _T_496 = mux(_T_493, _T_494, _T_495) @[el2_lsu_dccm_ctl.scala 292:63]
node _T_497 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89]
node _T_498 = bits(store_byteen_ext_r, 3, 3) @[el2_lsu_dccm_ctl.scala 292:134]
node _T_499 = not(_T_498) @[el2_lsu_dccm_ctl.scala 292:115]
node _T_500 = and(_T_497, _T_499) @[el2_lsu_dccm_ctl.scala 292:113]
node _T_501 = bits(_T_500, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139]
node _T_502 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 292:163]
node _T_503 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_dccm_ctl.scala 292:195]
node _T_504 = mux(_T_501, _T_502, _T_503) @[el2_lsu_dccm_ctl.scala 292:63]
wire _T_505 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 292:55]
_T_505[0] <= _T_480 @[el2_lsu_dccm_ctl.scala 292:55]
_T_505[1] <= _T_488 @[el2_lsu_dccm_ctl.scala 292:55]
_T_505[2] <= _T_496 @[el2_lsu_dccm_ctl.scala 292:55]
_T_505[3] <= _T_504 @[el2_lsu_dccm_ctl.scala 292:55]
node _T_506 = cat(_T_505[2], _T_505[3]) @[Cat.scala 29:58]
node _T_507 = cat(_T_505[0], _T_505[1]) @[Cat.scala 29:58]
node _T_508 = cat(_T_507, _T_506) @[Cat.scala 29:58]
io.store_datafn_lo_r <= _T_508 @[el2_lsu_dccm_ctl.scala 292:29]
node _T_509 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89]
node _T_510 = bits(store_byteen_ext_r, 0, 0) @[el2_lsu_dccm_ctl.scala 293:134]
node _T_511 = not(_T_510) @[el2_lsu_dccm_ctl.scala 293:115]
node _T_512 = and(_T_509, _T_511) @[el2_lsu_dccm_ctl.scala 293:113]
node _T_513 = bits(_T_512, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139]
node _T_514 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 293:163]
node _T_515 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_dccm_ctl.scala 293:195]
node _T_516 = mux(_T_513, _T_514, _T_515) @[el2_lsu_dccm_ctl.scala 293:63]
node _T_517 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89]
node _T_518 = bits(store_byteen_ext_r, 1, 1) @[el2_lsu_dccm_ctl.scala 293:134]
node _T_519 = not(_T_518) @[el2_lsu_dccm_ctl.scala 293:115]
node _T_520 = and(_T_517, _T_519) @[el2_lsu_dccm_ctl.scala 293:113]
node _T_521 = bits(_T_520, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139]
node _T_522 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 293:163]
node _T_523 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_dccm_ctl.scala 293:195]
node _T_524 = mux(_T_521, _T_522, _T_523) @[el2_lsu_dccm_ctl.scala 293:63]
node _T_525 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89]
node _T_526 = bits(store_byteen_ext_r, 2, 2) @[el2_lsu_dccm_ctl.scala 293:134]
node _T_527 = not(_T_526) @[el2_lsu_dccm_ctl.scala 293:115]
node _T_528 = and(_T_525, _T_527) @[el2_lsu_dccm_ctl.scala 293:113]
node _T_529 = bits(_T_528, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139]
node _T_530 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 293:163]
node _T_531 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_dccm_ctl.scala 293:195]
node _T_532 = mux(_T_529, _T_530, _T_531) @[el2_lsu_dccm_ctl.scala 293:63]
node _T_533 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89]
node _T_534 = bits(store_byteen_ext_r, 3, 3) @[el2_lsu_dccm_ctl.scala 293:134]
node _T_535 = not(_T_534) @[el2_lsu_dccm_ctl.scala 293:115]
node _T_536 = and(_T_533, _T_535) @[el2_lsu_dccm_ctl.scala 293:113]
node _T_537 = bits(_T_536, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139]
node _T_538 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 293:163]
node _T_539 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_dccm_ctl.scala 293:195]
node _T_540 = mux(_T_537, _T_538, _T_539) @[el2_lsu_dccm_ctl.scala 293:63]
wire _T_541 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 293:55]
_T_541[0] <= _T_516 @[el2_lsu_dccm_ctl.scala 293:55]
_T_541[1] <= _T_524 @[el2_lsu_dccm_ctl.scala 293:55]
_T_541[2] <= _T_532 @[el2_lsu_dccm_ctl.scala 293:55]
_T_541[3] <= _T_540 @[el2_lsu_dccm_ctl.scala 293:55]
node _T_542 = cat(_T_541[2], _T_541[3]) @[Cat.scala 29:58]
node _T_543 = cat(_T_541[0], _T_541[1]) @[Cat.scala 29:58]
node _T_544 = cat(_T_543, _T_542) @[Cat.scala 29:58]
io.store_datafn_hi_r <= _T_544 @[el2_lsu_dccm_ctl.scala 293:29]
node _T_545 = bits(io.store_data_hi_r, 31, 0) @[el2_lsu_dccm_ctl.scala 294:63]
node _T_546 = bits(io.store_data_lo_r, 31, 0) @[el2_lsu_dccm_ctl.scala 294:88]
node _T_547 = cat(_T_545, _T_546) @[Cat.scala 29:58]
node _T_548 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 294:116]
node _T_549 = mul(UInt<4>("h08"), _T_548) @[el2_lsu_dccm_ctl.scala 294:102]
node _T_550 = dshr(_T_547, _T_549) @[el2_lsu_dccm_ctl.scala 294:96]
node _T_551 = cat(_T_550, _T_550) @[Cat.scala 29:58]
node _T_552 = cat(_T_551, _T_551) @[Cat.scala 29:58]
node _T_553 = cat(_T_552, _T_552) @[Cat.scala 29:58]
node _T_554 = cat(_T_553, _T_553) @[Cat.scala 29:58]
node _T_555 = cat(_T_554, _T_554) @[Cat.scala 29:58]
node _T_556 = bits(store_byteen_r, 0, 0) @[el2_lsu_dccm_ctl.scala 294:174]
node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15]
node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_559 = bits(store_byteen_r, 1, 1) @[el2_lsu_dccm_ctl.scala 294:174]
node _T_560 = bits(_T_559, 0, 0) @[Bitwise.scala 72:15]
node _T_561 = mux(_T_560, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_562 = bits(store_byteen_r, 2, 2) @[el2_lsu_dccm_ctl.scala 294:174]
node _T_563 = bits(_T_562, 0, 0) @[Bitwise.scala 72:15]
node _T_564 = mux(_T_563, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_565 = bits(store_byteen_r, 3, 3) @[el2_lsu_dccm_ctl.scala 294:174]
node _T_566 = bits(_T_565, 0, 0) @[Bitwise.scala 72:15]
node _T_567 = mux(_T_566, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
wire _T_568 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 294:148]
_T_568[0] <= _T_558 @[el2_lsu_dccm_ctl.scala 294:148]
_T_568[1] <= _T_561 @[el2_lsu_dccm_ctl.scala 294:148]
_T_568[2] <= _T_564 @[el2_lsu_dccm_ctl.scala 294:148]
_T_568[3] <= _T_567 @[el2_lsu_dccm_ctl.scala 294:148]
node _T_569 = cat(_T_568[2], _T_568[3]) @[Cat.scala 29:58]
node _T_570 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58]
node _T_571 = cat(_T_570, _T_569) @[Cat.scala 29:58]
node _T_572 = and(_T_555, _T_571) @[el2_lsu_dccm_ctl.scala 294:123]
io.store_data_r <= _T_572 @[el2_lsu_dccm_ctl.scala 294:29]
node _T_573 = bits(io.dccm_rd_data_lo, 31, 0) @[el2_lsu_dccm_ctl.scala 297:48]
io.dccm_rdata_lo_m <= _T_573 @[el2_lsu_dccm_ctl.scala 297:27]
node _T_574 = bits(io.dccm_rd_data_hi, 31, 0) @[el2_lsu_dccm_ctl.scala 298:48]
io.dccm_rdata_hi_m <= _T_574 @[el2_lsu_dccm_ctl.scala 298:27]
node _T_575 = bits(io.dccm_rd_data_lo, 38, 32) @[el2_lsu_dccm_ctl.scala 299:48]
io.dccm_data_ecc_lo_m <= _T_575 @[el2_lsu_dccm_ctl.scala 299:27]
node _T_576 = bits(io.dccm_rd_data_hi, 38, 32) @[el2_lsu_dccm_ctl.scala 300:48]
io.dccm_data_ecc_hi_m <= _T_576 @[el2_lsu_dccm_ctl.scala 300:27]
node _T_577 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_dccm_ctl.scala 302:50]
node _T_578 = and(_T_577, io.addr_in_pic_r) @[el2_lsu_dccm_ctl.scala 302:71]
node _T_579 = and(_T_578, io.lsu_commit_r) @[el2_lsu_dccm_ctl.scala 302:90]
node _T_580 = or(_T_579, io.dma_pic_wen) @[el2_lsu_dccm_ctl.scala 302:109]
io.picm_wren <= _T_580 @[el2_lsu_dccm_ctl.scala 302:27]
node _T_581 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.load) @[el2_lsu_dccm_ctl.scala 303:50]
node _T_582 = and(_T_581, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 303:71]
io.picm_rden <= _T_582 @[el2_lsu_dccm_ctl.scala 303:27]
node _T_583 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 304:50]
node _T_584 = and(_T_583, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 304:71]
io.picm_mken <= _T_584 @[el2_lsu_dccm_ctl.scala 304:27]
node _T_585 = sub(UInt<6>("h020"), UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 306:58]
node _T_586 = tail(_T_585, 1) @[el2_lsu_dccm_ctl.scala 306:58]
node _T_587 = bits(io.lsu_addr_d, 14, 0) @[el2_lsu_dccm_ctl.scala 306:88]
node _T_588 = cat(_T_586, _T_587) @[Cat.scala 29:58]
node _T_589 = or(UInt<32>("h0f00c0000"), _T_588) @[el2_lsu_dccm_ctl.scala 306:47]
io.picm_rdaddr <= _T_589 @[el2_lsu_dccm_ctl.scala 306:27]
node _T_590 = sub(UInt<6>("h020"), UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 307:58]
node _T_591 = tail(_T_590, 1) @[el2_lsu_dccm_ctl.scala 307:58]
node _T_592 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 307:94]
node _T_593 = bits(io.dma_mem_addr, 14, 0) @[el2_lsu_dccm_ctl.scala 307:116]
node _T_594 = bits(io.lsu_addr_r, 14, 0) @[el2_lsu_dccm_ctl.scala 307:148]
node _T_595 = mux(_T_592, _T_593, _T_594) @[el2_lsu_dccm_ctl.scala 307:78]
node _T_596 = cat(_T_591, _T_595) @[Cat.scala 29:58]
node _T_597 = or(UInt<32>("h0f00c0000"), _T_596) @[el2_lsu_dccm_ctl.scala 307:47]
io.picm_wraddr <= _T_597 @[el2_lsu_dccm_ctl.scala 307:27]
node _T_598 = bits(picm_rd_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 308:44]
io.picm_mask_data_m <= _T_598 @[el2_lsu_dccm_ctl.scala 308:27]
node _T_599 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 309:49]
node _T_600 = bits(io.dma_mem_wdata, 31, 0) @[el2_lsu_dccm_ctl.scala 309:72]
node _T_601 = bits(io.store_datafn_lo_r, 31, 0) @[el2_lsu_dccm_ctl.scala 309:99]
node _T_602 = mux(_T_599, _T_600, _T_601) @[el2_lsu_dccm_ctl.scala 309:33]
io.picm_wr_data <= _T_602 @[el2_lsu_dccm_ctl.scala 309:27]
reg _T_603 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 312:61]
_T_603 <= lsu_dccm_rden_d @[el2_lsu_dccm_ctl.scala 312:61]
io.lsu_dccm_rden_m <= _T_603 @[el2_lsu_dccm_ctl.scala 312:24]
reg _T_604 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 313:61]
_T_604 <= io.lsu_dccm_rden_m @[el2_lsu_dccm_ctl.scala 313:61]
io.lsu_dccm_rden_r <= _T_604 @[el2_lsu_dccm_ctl.scala 313:24]

621
el2_lsu_dccm_ctl.v Normal file
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@ -0,0 +1,621 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[beh_lib.scala 330:26]
wire clkhdr_CK; // @[beh_lib.scala 330:26]
wire clkhdr_EN; // @[beh_lib.scala 330:26]
wire clkhdr_SE; // @[beh_lib.scala 330:26]
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 330:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 331:14]
assign clkhdr_CK = io_clk; // @[beh_lib.scala 332:18]
assign clkhdr_EN = io_en; // @[beh_lib.scala 333:18]
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 334:18]
endmodule
module el2_lsu_dccm_ctl(
input clock,
input reset,
input io_lsu_c2_m_clk,
input io_lsu_c2_r_clk,
input io_lsu_free_c2_clk,
input io_lsu_c1_r_clk,
input io_lsu_store_c1_r_clk,
input io_clk,
input io_lsu_pkt_d_fast_int,
input io_lsu_pkt_d_by,
input io_lsu_pkt_d_half,
input io_lsu_pkt_d_word,
input io_lsu_pkt_d_dword,
input io_lsu_pkt_d_load,
input io_lsu_pkt_d_store,
input io_lsu_pkt_d_unsign,
input io_lsu_pkt_d_dma,
input io_lsu_pkt_d_store_data_bypass_d,
input io_lsu_pkt_d_load_ldst_bypass_d,
input io_lsu_pkt_d_store_data_bypass_m,
input io_lsu_pkt_d_valid,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_r_fast_int,
input io_lsu_pkt_r_by,
input io_lsu_pkt_r_half,
input io_lsu_pkt_r_word,
input io_lsu_pkt_r_dword,
input io_lsu_pkt_r_load,
input io_lsu_pkt_r_store,
input io_lsu_pkt_r_unsign,
input io_lsu_pkt_r_dma,
input io_lsu_pkt_r_store_data_bypass_d,
input io_lsu_pkt_r_load_ldst_bypass_d,
input io_lsu_pkt_r_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_addr_in_dccm_d,
input io_addr_in_dccm_m,
input io_addr_in_dccm_r,
input io_addr_in_pic_d,
input io_addr_in_pic_m,
input io_addr_in_pic_r,
input io_lsu_raw_fwd_lo_r,
input io_lsu_raw_fwd_hi_r,
input io_lsu_commit_r,
input [31:0] io_lsu_addr_d,
input [15:0] io_lsu_addr_m,
input [31:0] io_lsu_addr_r,
input [15:0] io_end_addr_d,
input [15:0] io_end_addr_m,
input [15:0] io_end_addr_r,
input io_stbuf_reqvld_any,
input [15:0] io_stbuf_addr_any,
input [31:0] io_stbuf_data_any,
input [6:0] io_stbuf_ecc_any,
input [31:0] io_stbuf_fwddata_hi_m,
input [31:0] io_stbuf_fwddata_lo_m,
input [3:0] io_stbuf_fwdbyteen_lo_m,
input [3:0] io_stbuf_fwdbyteen_hi_m,
output [31:0] io_dccm_rdata_hi_r,
output [31:0] io_dccm_rdata_lo_r,
output [6:0] io_dccm_data_ecc_hi_r,
output [6:0] io_dccm_data_ecc_lo_r,
output [31:0] io_lsu_ld_data_r,
output [31:0] io_lsu_ld_data_corr_r,
input io_lsu_double_ecc_error_r,
input io_single_ecc_error_hi_r,
input io_single_ecc_error_lo_r,
input [31:0] io_sec_data_hi_r,
input [31:0] io_sec_data_lo_r,
input [31:0] io_sec_data_hi_r_ff,
input [31:0] io_sec_data_lo_r_ff,
input [6:0] io_sec_data_ecc_hi_r_ff,
input [6:0] io_sec_data_ecc_lo_r_ff,
output [31:0] io_dccm_rdata_hi_m,
output [31:0] io_dccm_rdata_lo_m,
output [6:0] io_dccm_data_ecc_hi_m,
output [6:0] io_dccm_data_ecc_lo_m,
output [31:0] io_lsu_ld_data_m,
input io_lsu_double_ecc_error_m,
input [31:0] io_sec_data_hi_m,
input [31:0] io_sec_data_lo_m,
input [31:0] io_store_data_m,
input io_dma_dccm_wen,
input io_dma_pic_wen,
input [2:0] io_dma_mem_tag_m,
input [31:0] io_dma_mem_addr,
input [63:0] io_dma_mem_wdata,
input [31:0] io_dma_dccm_wdata_lo,
input [31:0] io_dma_dccm_wdata_hi,
input [6:0] io_dma_dccm_wdata_ecc_hi,
input [6:0] io_dma_dccm_wdata_ecc_lo,
output [31:0] io_store_data_hi_r,
output [31:0] io_store_data_lo_r,
output [31:0] io_store_datafn_hi_r,
output [31:0] io_store_datafn_lo_r,
output [31:0] io_store_data_r,
output io_ld_single_ecc_error_r,
output io_ld_single_ecc_error_r_ff,
output [31:0] io_picm_mask_data_m,
output io_lsu_stbuf_commit_any,
output io_lsu_dccm_rden_m,
output io_lsu_dccm_rden_r,
output io_dccm_dma_rvalid,
output io_dccm_dma_ecc_error,
output [2:0] io_dccm_dma_rtag,
output [63:0] io_dccm_dma_rdata,
output io_dccm_wren,
output io_dccm_rden,
output [15:0] io_dccm_wr_addr_lo,
output [38:0] io_dccm_wr_data_lo,
output [15:0] io_dccm_rd_addr_lo,
input [38:0] io_dccm_rd_data_lo,
output [15:0] io_dccm_wr_addr_hi,
output [38:0] io_dccm_wr_data_hi,
output [15:0] io_dccm_rd_addr_hi,
input [38:0] io_dccm_rd_data_hi,
output io_picm_wren,
output io_picm_rden,
output io_picm_mken,
output [31:0] io_picm_rdaddr,
output [31:0] io_picm_wraddr,
output [31:0] io_picm_wr_data,
input [31:0] io_picm_rd_data,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 350:21]
wire rvclkhdr_io_clk; // @[beh_lib.scala 350:21]
wire rvclkhdr_io_en; // @[beh_lib.scala 350:21]
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 350:21]
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 350:21]
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 350:21]
wire rvclkhdr_1_io_en; // @[beh_lib.scala 350:21]
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 350:21]
wire [63:0] picm_rd_data_m = {io_picm_rd_data,io_picm_rd_data}; // @[Cat.scala 29:58]
wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58]
wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58]
wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_load; // @[el2_lsu_dccm_ctl.scala 168:50]
wire [7:0] _T_30 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58]
wire [63:0] _T_33 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58]
wire [7:0] _T_38 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_corr_m[15:8]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_1 = _T_30[1] ? _T_33[15:8] : _T_38; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [7:0] _T_18 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_corr_m[7:0]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_0 = _T_30[0] ? _T_33[7:0] : _T_18; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [7:0] _T_78 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_corr_m[31:24]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_3 = _T_30[3] ? _T_33[31:24] : _T_78; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [7:0] _T_58 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_corr_m[23:16]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_2 = _T_30[2] ? _T_33[23:16] : _T_58; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [31:0] _T_4 = {lsu_rdata_corr_m_3,lsu_rdata_corr_m_2,lsu_rdata_corr_m_1,lsu_rdata_corr_m_0}; // @[el2_lsu_dccm_ctl.scala 170:48]
wire [7:0] _T_118 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_corr_m[47:40]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_5 = _T_30[5] ? _T_33[47:40] : _T_118; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [7:0] _T_98 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_corr_m[39:32]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_4 = _T_30[4] ? _T_33[39:32] : _T_98; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [7:0] _T_158 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_corr_m[63:56]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_7 = _T_30[7] ? _T_33[63:56] : _T_158; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [7:0] _T_138 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_corr_m[55:48]; // @[el2_lsu_dccm_ctl.scala 184:171]
wire [7:0] lsu_rdata_corr_m_6 = _T_30[6] ? _T_33[55:48] : _T_138; // @[el2_lsu_dccm_ctl.scala 184:36]
wire [31:0] _T_7 = {lsu_rdata_corr_m_7,lsu_rdata_corr_m_6,lsu_rdata_corr_m_5,lsu_rdata_corr_m_4}; // @[el2_lsu_dccm_ctl.scala 170:48]
wire [63:0] _T_8 = {lsu_rdata_corr_m_7,lsu_rdata_corr_m_6,lsu_rdata_corr_m_5,lsu_rdata_corr_m_4,lsu_rdata_corr_m_3,lsu_rdata_corr_m_2,lsu_rdata_corr_m_1,lsu_rdata_corr_m_0}; // @[el2_lsu_dccm_ctl.scala 170:48]
reg [63:0] _T_9; // @[el2_lsu_dccm_ctl.scala 178:65]
wire [7:0] _T_28 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_m[7:0]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_0 = _T_30[0] ? _T_33[7:0] : _T_28; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_48 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_m[15:8]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_1 = _T_30[1] ? _T_33[15:8] : _T_48; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_68 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_m[23:16]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_2 = _T_30[2] ? _T_33[23:16] : _T_68; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_88 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_m[31:24]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_3 = _T_30[3] ? _T_33[31:24] : _T_88; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_108 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_m[39:32]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_4 = _T_30[4] ? _T_33[39:32] : _T_108; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_128 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_m[47:40]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_5 = _T_30[5] ? _T_33[47:40] : _T_128; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_148 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_m[55:48]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_6 = _T_30[6] ? _T_33[55:48] : _T_148; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [7:0] _T_168 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_m[63:56]; // @[el2_lsu_dccm_ctl.scala 185:171]
wire [7:0] lsu_rdata_m_7 = _T_30[7] ? _T_33[63:56] : _T_168; // @[el2_lsu_dccm_ctl.scala 185:36]
wire [63:0] _T_176 = {lsu_rdata_m_7,lsu_rdata_m_6,lsu_rdata_m_5,lsu_rdata_m_4,lsu_rdata_m_3,lsu_rdata_m_2,lsu_rdata_m_1,lsu_rdata_m_0}; // @[el2_lsu_dccm_ctl.scala 186:43]
wire [3:0] _GEN_0 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_dccm_ctl.scala 186:56]
wire [5:0] _T_178 = 4'h8 * _GEN_0; // @[el2_lsu_dccm_ctl.scala 186:56]
wire [63:0] _T_179 = _T_176 >> _T_178; // @[el2_lsu_dccm_ctl.scala 186:50]
wire _T_192 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 190:64]
wire _T_195 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 190:145]
wire _T_196 = _T_192 | _T_195; // @[el2_lsu_dccm_ctl.scala 190:109]
wire _T_197 = _T_196 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 190:191]
wire _T_198 = _T_197 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 190:212]
wire _T_199 = _T_198 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 190:233]
wire _T_200 = _T_199 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 190:252]
wire _T_203 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 191:41]
wire _T_206 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 191:122]
wire _T_207 = _T_203 | _T_206; // @[el2_lsu_dccm_ctl.scala 191:86]
wire _T_208 = _T_207 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 191:168]
wire _T_209 = _T_208 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 191:189]
wire _T_210 = _T_209 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 191:210]
wire _T_211 = _T_210 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 191:229]
wire kill_ecc_corr_lo_r = _T_200 | _T_211; // @[el2_lsu_dccm_ctl.scala 190:273]
wire _T_214 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 192:64]
wire _T_217 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 192:145]
wire _T_218 = _T_214 | _T_217; // @[el2_lsu_dccm_ctl.scala 192:109]
wire _T_219 = _T_218 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 192:191]
wire _T_220 = _T_219 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 192:212]
wire _T_221 = _T_220 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 192:233]
wire _T_222 = _T_221 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 192:252]
wire _T_225 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 193:41]
wire _T_228 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 193:122]
wire _T_229 = _T_225 | _T_228; // @[el2_lsu_dccm_ctl.scala 193:86]
wire _T_230 = _T_229 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 193:168]
wire _T_231 = _T_230 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 193:189]
wire _T_232 = _T_231 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 193:210]
wire _T_233 = _T_232 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 193:229]
wire kill_ecc_corr_hi_r = _T_222 | _T_233; // @[el2_lsu_dccm_ctl.scala 192:273]
wire _T_234 = io_lsu_pkt_r_load & io_single_ecc_error_lo_r; // @[el2_lsu_dccm_ctl.scala 194:55]
wire _T_235 = ~io_lsu_raw_fwd_lo_r; // @[el2_lsu_dccm_ctl.scala 194:84]
wire ld_single_ecc_error_lo_r = _T_234 & _T_235; // @[el2_lsu_dccm_ctl.scala 194:82]
wire _T_236 = io_lsu_pkt_r_load & io_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 195:55]
wire _T_237 = ~io_lsu_raw_fwd_hi_r; // @[el2_lsu_dccm_ctl.scala 195:84]
wire ld_single_ecc_error_hi_r = _T_236 & _T_237; // @[el2_lsu_dccm_ctl.scala 195:82]
wire _T_238 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 196:62]
wire _T_239 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_dccm_ctl.scala 196:92]
wire _T_241 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_dccm_ctl.scala 197:81]
wire _T_242 = ld_single_ecc_error_lo_r & _T_241; // @[el2_lsu_dccm_ctl.scala 197:62]
wire _T_243 = ~kill_ecc_corr_lo_r; // @[el2_lsu_dccm_ctl.scala 197:103]
wire _T_245 = ld_single_ecc_error_hi_r & _T_241; // @[el2_lsu_dccm_ctl.scala 198:62]
wire _T_246 = ~kill_ecc_corr_hi_r; // @[el2_lsu_dccm_ctl.scala 198:103]
reg lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 200:74]
reg ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 201:74]
reg ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 202:74]
reg [15:0] ld_sec_addr_hi_r_ff; // @[beh_lib.scala 356:14]
reg [15:0] ld_sec_addr_lo_r_ff; // @[beh_lib.scala 356:14]
wire _T_253 = io_lsu_pkt_d_word | io_lsu_pkt_d_dword; // @[el2_lsu_dccm_ctl.scala 208:110]
wire _T_254 = ~_T_253; // @[el2_lsu_dccm_ctl.scala 208:90]
wire _T_256 = io_lsu_addr_d[1:0] != 2'h0; // @[el2_lsu_dccm_ctl.scala 208:154]
wire _T_257 = _T_254 | _T_256; // @[el2_lsu_dccm_ctl.scala 208:132]
wire _T_258 = io_lsu_pkt_d_store & _T_257; // @[el2_lsu_dccm_ctl.scala 208:87]
wire _T_259 = io_lsu_pkt_d_load | _T_258; // @[el2_lsu_dccm_ctl.scala 208:65]
wire _T_260 = io_lsu_pkt_d_valid & _T_259; // @[el2_lsu_dccm_ctl.scala 208:44]
wire lsu_dccm_rden_d = _T_260 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 208:171]
wire _T_261 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 211:63]
wire _T_262 = ~lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 211:96]
wire _T_264 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[el2_lsu_dccm_ctl.scala 212:71]
wire _T_265 = _T_264 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 212:89]
wire _T_266 = ~_T_265; // @[el2_lsu_dccm_ctl.scala 212:53]
wire _T_269 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 213:107]
wire _T_272 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 214:88]
wire _T_273 = _T_269 | _T_272; // @[el2_lsu_dccm_ctl.scala 213:195]
wire _T_274 = ~_T_273; // @[el2_lsu_dccm_ctl.scala 213:24]
wire _T_275 = lsu_dccm_rden_d & _T_274; // @[el2_lsu_dccm_ctl.scala 213:22]
wire _T_276 = _T_266 | _T_275; // @[el2_lsu_dccm_ctl.scala 212:120]
wire _T_278 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[el2_lsu_dccm_ctl.scala 217:41]
wire [15:0] _T_285 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 220:8]
wire [15:0] _T_289 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 221:8]
wire [15:0] _T_295 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 223:8]
wire [15:0] _T_299 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 224:8]
wire _T_304 = ~ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 228:36]
wire [38:0] _T_307 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
wire [38:0] _T_310 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
wire [38:0] _T_311 = _T_304 ? _T_307 : _T_310; // @[el2_lsu_dccm_ctl.scala 228:8]
wire [38:0] _T_315 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
wire [38:0] _T_318 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
wire [38:0] _T_319 = io_dma_dccm_wen ? _T_315 : _T_318; // @[el2_lsu_dccm_ctl.scala 230:8]
wire _T_322 = ~ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 234:36]
wire [38:0] _T_329 = _T_322 ? _T_310 : _T_307; // @[el2_lsu_dccm_ctl.scala 234:8]
wire [38:0] _T_333 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
wire [38:0] _T_337 = io_dma_dccm_wen ? _T_333 : _T_318; // @[el2_lsu_dccm_ctl.scala 236:8]
wire [3:0] _T_340 = io_lsu_pkt_m_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_342 = io_lsu_pkt_m_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_343 = _T_342 & 4'h1; // @[el2_lsu_dccm_ctl.scala 240:84]
wire [3:0] _T_345 = io_lsu_pkt_m_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_346 = _T_345 & 4'h3; // @[el2_lsu_dccm_ctl.scala 241:33]
wire [3:0] _T_347 = _T_343 | _T_346; // @[el2_lsu_dccm_ctl.scala 240:97]
wire [3:0] _T_349 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_351 = _T_347 | _T_349; // @[el2_lsu_dccm_ctl.scala 241:46]
wire [3:0] store_byteen_m = _T_340 & _T_351; // @[el2_lsu_dccm_ctl.scala 240:53]
wire [3:0] _T_353 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_355 = io_lsu_pkt_r_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_356 = _T_355 & 4'h1; // @[el2_lsu_dccm_ctl.scala 243:84]
wire [3:0] _T_358 = io_lsu_pkt_r_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_359 = _T_358 & 4'h3; // @[el2_lsu_dccm_ctl.scala 244:33]
wire [3:0] _T_360 = _T_356 | _T_359; // @[el2_lsu_dccm_ctl.scala 243:97]
wire [3:0] _T_362 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_364 = _T_360 | _T_362; // @[el2_lsu_dccm_ctl.scala 244:46]
wire [3:0] store_byteen_r = _T_353 & _T_364; // @[el2_lsu_dccm_ctl.scala 243:53]
wire [7:0] _T_366 = {4'h0,store_byteen_m}; // @[Cat.scala 29:58]
wire [10:0] _GEN_2 = {{3'd0}, _T_366}; // @[el2_lsu_dccm_ctl.scala 246:62]
wire [10:0] store_byteen_ext_m = _GEN_2 << io_lsu_addr_m[1:0]; // @[el2_lsu_dccm_ctl.scala 246:62]
wire [7:0] _T_369 = {4'h0,store_byteen_r}; // @[Cat.scala 29:58]
wire [10:0] _GEN_3 = {{3'd0}, _T_369}; // @[el2_lsu_dccm_ctl.scala 247:62]
wire [10:0] store_byteen_ext_r = _GEN_3 << io_lsu_addr_r[1:0]; // @[el2_lsu_dccm_ctl.scala 247:62]
wire _T_373 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 250:71]
wire dccm_wr_bypass_d_m_lo = _T_373 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 250:109]
wire _T_376 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 251:71]
wire dccm_wr_bypass_d_m_hi = _T_376 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 251:109]
wire _T_379 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 253:71]
wire dccm_wr_bypass_d_r_lo = _T_379 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 253:109]
wire [63:0] _T_385 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58]
wire [126:0] _GEN_5 = {{63'd0}, _T_385}; // @[el2_lsu_dccm_ctl.scala 287:72]
wire [126:0] _T_388 = _GEN_5 << _T_178; // @[el2_lsu_dccm_ctl.scala 287:72]
wire [63:0] store_data_pre_m = _T_388[63:0]; // @[el2_lsu_dccm_ctl.scala 287:29]
wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[el2_lsu_dccm_ctl.scala 288:48]
wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[el2_lsu_dccm_ctl.scala 289:48]
wire _T_394 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[el2_lsu_dccm_ctl.scala 290:195]
wire [7:0] _T_398 = _T_394 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[el2_lsu_dccm_ctl.scala 290:169]
wire [7:0] _T_399 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_398; // @[el2_lsu_dccm_ctl.scala 290:104]
wire [7:0] _T_407 = _T_394 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[el2_lsu_dccm_ctl.scala 290:169]
wire [7:0] _T_408 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_407; // @[el2_lsu_dccm_ctl.scala 290:104]
wire [7:0] _T_416 = _T_394 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[el2_lsu_dccm_ctl.scala 290:169]
wire [7:0] _T_417 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_416; // @[el2_lsu_dccm_ctl.scala 290:104]
wire [7:0] _T_425 = _T_394 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[el2_lsu_dccm_ctl.scala 290:169]
wire [7:0] _T_426 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_425; // @[el2_lsu_dccm_ctl.scala 290:104]
wire [15:0] _T_428 = {_T_417,_T_426}; // @[Cat.scala 29:58]
wire [15:0] _T_429 = {_T_399,_T_408}; // @[Cat.scala 29:58]
reg [31:0] _T_431; // @[el2_lsu_dccm_ctl.scala 290:72]
wire _T_435 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[el2_lsu_dccm_ctl.scala 291:195]
wire [7:0] _T_439 = _T_435 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[el2_lsu_dccm_ctl.scala 291:169]
wire [7:0] _T_440 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_439; // @[el2_lsu_dccm_ctl.scala 291:104]
wire [7:0] _T_448 = _T_435 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[el2_lsu_dccm_ctl.scala 291:169]
wire [7:0] _T_449 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_448; // @[el2_lsu_dccm_ctl.scala 291:104]
wire [7:0] _T_457 = _T_435 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[el2_lsu_dccm_ctl.scala 291:169]
wire [7:0] _T_458 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_457; // @[el2_lsu_dccm_ctl.scala 291:104]
wire [7:0] _T_466 = _T_435 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[el2_lsu_dccm_ctl.scala 291:169]
wire [7:0] _T_467 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_466; // @[el2_lsu_dccm_ctl.scala 291:104]
wire [15:0] _T_469 = {_T_458,_T_467}; // @[Cat.scala 29:58]
wire [15:0] _T_470 = {_T_440,_T_449}; // @[Cat.scala 29:58]
reg [31:0] _T_472; // @[el2_lsu_dccm_ctl.scala 291:72]
wire _T_473 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[el2_lsu_dccm_ctl.scala 292:89]
wire _T_475 = ~store_byteen_ext_r[0]; // @[el2_lsu_dccm_ctl.scala 292:115]
wire _T_476 = _T_473 & _T_475; // @[el2_lsu_dccm_ctl.scala 292:113]
wire [7:0] _T_480 = _T_476 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[el2_lsu_dccm_ctl.scala 292:63]
wire _T_483 = ~store_byteen_ext_r[1]; // @[el2_lsu_dccm_ctl.scala 292:115]
wire _T_484 = _T_473 & _T_483; // @[el2_lsu_dccm_ctl.scala 292:113]
wire [7:0] _T_488 = _T_484 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[el2_lsu_dccm_ctl.scala 292:63]
wire _T_491 = ~store_byteen_ext_r[2]; // @[el2_lsu_dccm_ctl.scala 292:115]
wire _T_492 = _T_473 & _T_491; // @[el2_lsu_dccm_ctl.scala 292:113]
wire [7:0] _T_496 = _T_492 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[el2_lsu_dccm_ctl.scala 292:63]
wire _T_499 = ~store_byteen_ext_r[3]; // @[el2_lsu_dccm_ctl.scala 292:115]
wire _T_500 = _T_473 & _T_499; // @[el2_lsu_dccm_ctl.scala 292:113]
wire [7:0] _T_504 = _T_500 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[el2_lsu_dccm_ctl.scala 292:63]
wire [15:0] _T_506 = {_T_496,_T_504}; // @[Cat.scala 29:58]
wire [15:0] _T_507 = {_T_480,_T_488}; // @[Cat.scala 29:58]
wire [7:0] _T_516 = _T_476 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[el2_lsu_dccm_ctl.scala 293:63]
wire [7:0] _T_524 = _T_484 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[el2_lsu_dccm_ctl.scala 293:63]
wire [7:0] _T_532 = _T_492 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[el2_lsu_dccm_ctl.scala 293:63]
wire [7:0] _T_540 = _T_500 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[el2_lsu_dccm_ctl.scala 293:63]
wire [15:0] _T_542 = {_T_532,_T_540}; // @[Cat.scala 29:58]
wire [15:0] _T_543 = {_T_516,_T_524}; // @[Cat.scala 29:58]
wire [63:0] _T_547 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58]
wire [3:0] _GEN_6 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[el2_lsu_dccm_ctl.scala 294:102]
wire [5:0] _T_549 = 4'h8 * _GEN_6; // @[el2_lsu_dccm_ctl.scala 294:102]
wire [63:0] _T_550 = _T_547 >> _T_549; // @[el2_lsu_dccm_ctl.scala 294:96]
wire [511:0] _T_553 = {_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_550}; // @[Cat.scala 29:58]
wire [1023:0] _T_554 = {_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_553}; // @[Cat.scala 29:58]
wire [2047:0] _T_555 = {_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_550,_T_553,_T_554}; // @[Cat.scala 29:58]
wire [7:0] _T_558 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_561 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_564 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_567 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_571 = {_T_558,_T_561,_T_564,_T_567}; // @[Cat.scala 29:58]
wire [2047:0] _GEN_7 = {{2016'd0}, _T_571}; // @[el2_lsu_dccm_ctl.scala 294:123]
wire [2047:0] _T_572 = _T_555 & _GEN_7; // @[el2_lsu_dccm_ctl.scala 294:123]
wire _T_577 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_dccm_ctl.scala 302:50]
wire _T_578 = _T_577 & io_addr_in_pic_r; // @[el2_lsu_dccm_ctl.scala 302:71]
wire _T_579 = _T_578 & io_lsu_commit_r; // @[el2_lsu_dccm_ctl.scala 302:90]
wire _T_581 = io_lsu_pkt_d_valid & io_lsu_pkt_d_load; // @[el2_lsu_dccm_ctl.scala 303:50]
wire _T_583 = io_lsu_pkt_d_valid & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 304:50]
wire [5:0] _T_586 = 6'h20 - 6'h1; // @[el2_lsu_dccm_ctl.scala 306:58]
wire [20:0] _T_588 = {_T_586,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
wire [31:0] _GEN_8 = {{11'd0}, _T_588}; // @[el2_lsu_dccm_ctl.scala 306:47]
wire [14:0] _T_595 = io_dma_pic_wen ? io_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[el2_lsu_dccm_ctl.scala 307:78]
wire [20:0] _T_596 = {_T_586,_T_595}; // @[Cat.scala 29:58]
wire [31:0] _GEN_9 = {{11'd0}, _T_596}; // @[el2_lsu_dccm_ctl.scala 307:47]
reg _T_603; // @[el2_lsu_dccm_ctl.scala 312:61]
reg _T_604; // @[el2_lsu_dccm_ctl.scala 313:61]
rvclkhdr rvclkhdr ( // @[beh_lib.scala 350:21]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 350:21]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
assign io_dccm_rdata_hi_r = 32'h0; // @[el2_lsu_dccm_ctl.scala 173:28]
assign io_dccm_rdata_lo_r = 32'h0; // @[el2_lsu_dccm_ctl.scala 172:28]
assign io_dccm_data_ecc_hi_r = 7'h0; // @[el2_lsu_dccm_ctl.scala 174:28]
assign io_dccm_data_ecc_lo_r = 7'h0; // @[el2_lsu_dccm_ctl.scala 175:28]
assign io_lsu_ld_data_r = 32'h0; // @[el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27 el2_lsu_dccm_ctl.scala 181:27]
assign io_lsu_ld_data_corr_r = _T_9[31:0]; // @[el2_lsu_dccm_ctl.scala 178:28]
assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[el2_lsu_dccm_ctl.scala 298:27]
assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[el2_lsu_dccm_ctl.scala 297:27]
assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[el2_lsu_dccm_ctl.scala 300:27]
assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[el2_lsu_dccm_ctl.scala 299:27]
assign io_lsu_ld_data_m = _T_179[31:0]; // @[el2_lsu_dccm_ctl.scala 186:28]
assign io_store_data_hi_r = _T_472; // @[el2_lsu_dccm_ctl.scala 291:29]
assign io_store_data_lo_r = _T_431; // @[el2_lsu_dccm_ctl.scala 290:29]
assign io_store_datafn_hi_r = {_T_543,_T_542}; // @[el2_lsu_dccm_ctl.scala 293:29]
assign io_store_datafn_lo_r = {_T_507,_T_506}; // @[el2_lsu_dccm_ctl.scala 292:29]
assign io_store_data_r = _T_572[31:0]; // @[el2_lsu_dccm_ctl.scala 294:29]
assign io_ld_single_ecc_error_r = _T_238 & _T_239; // @[el2_lsu_dccm_ctl.scala 196:33]
assign io_ld_single_ecc_error_r_ff = _T_261 & _T_262; // @[el2_lsu_dccm_ctl.scala 211:31]
assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[el2_lsu_dccm_ctl.scala 308:27]
assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_276; // @[el2_lsu_dccm_ctl.scala 212:27]
assign io_lsu_dccm_rden_m = _T_603; // @[el2_lsu_dccm_ctl.scala 312:24]
assign io_lsu_dccm_rden_r = _T_604; // @[el2_lsu_dccm_ctl.scala 313:24]
assign io_dccm_dma_rvalid = _T & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 168:28]
assign io_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[el2_lsu_dccm_ctl.scala 169:28]
assign io_dccm_dma_rtag = io_dma_mem_tag_m; // @[el2_lsu_dccm_ctl.scala 171:28]
assign io_dccm_dma_rdata = {_T_7,_T_4}; // @[el2_lsu_dccm_ctl.scala 170:28]
assign io_dccm_wren = _T_278 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 217:22]
assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 218:22]
assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_285 : _T_289; // @[el2_lsu_dccm_ctl.scala 219:22]
assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_311 : _T_319; // @[el2_lsu_dccm_ctl.scala 227:22]
assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[el2_lsu_dccm_ctl.scala 225:22]
assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_295 : _T_299; // @[el2_lsu_dccm_ctl.scala 222:22]
assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_329 : _T_337; // @[el2_lsu_dccm_ctl.scala 233:22]
assign io_dccm_rd_addr_hi = io_end_addr_d; // @[el2_lsu_dccm_ctl.scala 226:22]
assign io_picm_wren = _T_579 | io_dma_pic_wen; // @[el2_lsu_dccm_ctl.scala 302:27]
assign io_picm_rden = _T_581 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 303:27]
assign io_picm_mken = _T_583 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 304:27]
assign io_picm_rdaddr = 32'hf00c0000 | _GEN_8; // @[el2_lsu_dccm_ctl.scala 306:27]
assign io_picm_wraddr = 32'hf00c0000 | _GEN_9; // @[el2_lsu_dccm_ctl.scala 307:27]
assign io_picm_wr_data = io_dma_pic_wen ? io_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[el2_lsu_dccm_ctl.scala 309:27]
assign rvclkhdr_io_clk = io_clk; // @[beh_lib.scala 352:16]
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 353:15]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22]
assign rvclkhdr_1_io_clk = io_clk; // @[beh_lib.scala 352:16]
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 353:15]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
_T_9 = _RAND_0[63:0];
_RAND_1 = {1{`RANDOM}};
lsu_double_ecc_error_r_ff = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
ld_single_ecc_error_hi_r_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
ld_single_ecc_error_lo_r_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
ld_sec_addr_hi_r_ff = _RAND_4[15:0];
_RAND_5 = {1{`RANDOM}};
ld_sec_addr_lo_r_ff = _RAND_5[15:0];
_RAND_6 = {1{`RANDOM}};
_T_431 = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
_T_472 = _RAND_7[31:0];
_RAND_8 = {1{`RANDOM}};
_T_603 = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
_T_604 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_9 = 64'h0;
end
if (reset) begin
lsu_double_ecc_error_r_ff = 1'h0;
end
if (reset) begin
ld_single_ecc_error_hi_r_ff = 1'h0;
end
if (reset) begin
ld_single_ecc_error_lo_r_ff = 1'h0;
end
if (reset) begin
ld_sec_addr_hi_r_ff = 16'h0;
end
if (reset) begin
ld_sec_addr_lo_r_ff = 16'h0;
end
if (reset) begin
_T_603 = 1'h0;
end
if (reset) begin
_T_604 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_store_c1_r_clk) begin
_T_431 <= {_T_429,_T_428};
_T_472 <= {_T_470,_T_469};
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_9 <= 64'h0;
end else begin
_T_9 <= _T_8 >> _T_178;
end
end
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
lsu_double_ecc_error_r_ff <= 1'h0;
end else begin
lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r;
end
end
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
ld_single_ecc_error_hi_r_ff <= 1'h0;
end else begin
ld_single_ecc_error_hi_r_ff <= _T_245 & _T_246;
end
end
always @(posedge io_lsu_free_c2_clk or posedge reset) begin
if (reset) begin
ld_single_ecc_error_lo_r_ff <= 1'h0;
end else begin
ld_single_ecc_error_lo_r_ff <= _T_242 & _T_243;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin
ld_sec_addr_hi_r_ff <= 16'h0;
end else begin
ld_sec_addr_hi_r_ff <= io_end_addr_r;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin
ld_sec_addr_lo_r_ff <= 16'h0;
end else begin
ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0];
end
end
always @(posedge io_lsu_c2_m_clk or posedge reset) begin
if (reset) begin
_T_603 <= 1'h0;
end else begin
_T_603 <= _T_260 & io_addr_in_dccm_d;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_604 <= 1'h0;
end else begin
_T_604 <= io_lsu_dccm_rden_m;
end
end
endmodule

343
el2_lsu_ecc.anno.json Normal file
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@ -0,0 +1,343 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_single_ecc_error_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_ecc_lo_r_ff",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_lo",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_lo_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_ecc_hi_r_ff",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_hi",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_double_ecc_error_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_single_ecc_error_hi_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_r",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_single_ecc_error_m",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_dec_tlu_core_ecc_disable",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_data_ecc_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_dma",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_hi_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_dccm_rden_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_dccm_rdata_lo_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_addr_in_dccm_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_valid",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_r",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_end_addr_m",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_r_store",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_load",
"~el2_lsu_ecc|el2_lsu_ecc>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_ecc_hi",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_hi_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_hi",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_ecc_lo",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_lo",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_ecc_any",
"sources":[
"~el2_lsu_ecc|el2_lsu_ecc>io_sec_data_lo_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_ld_single_ecc_error_r_ff",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wdata_lo",
"~el2_lsu_ecc|el2_lsu_ecc>io_stbuf_data_any",
"~el2_lsu_ecc|el2_lsu_ecc>io_dma_dccm_wen"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_ecc"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1755
el2_lsu_ecc.fir Normal file
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File diff suppressed because it is too large Load Diff

466
el2_lsu_ecc.v Normal file
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@ -0,0 +1,466 @@
module el2_lsu_ecc(
input clock,
input reset,
input io_lsu_c2_r_clk,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_r_fast_int,
input io_lsu_pkt_r_by,
input io_lsu_pkt_r_half,
input io_lsu_pkt_r_word,
input io_lsu_pkt_r_dword,
input io_lsu_pkt_r_load,
input io_lsu_pkt_r_store,
input io_lsu_pkt_r_unsign,
input io_lsu_pkt_r_dma,
input io_lsu_pkt_r_store_data_bypass_d,
input io_lsu_pkt_r_load_ldst_bypass_d,
input io_lsu_pkt_r_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input [31:0] io_stbuf_data_any,
input io_dec_tlu_core_ecc_disable,
input io_lsu_dccm_rden_r,
input io_addr_in_dccm_r,
input [15:0] io_lsu_addr_r,
input [15:0] io_end_addr_r,
input [15:0] io_lsu_addr_m,
input [15:0] io_end_addr_m,
input [31:0] io_dccm_rdata_hi_r,
input [31:0] io_dccm_rdata_lo_r,
input [31:0] io_dccm_rdata_hi_m,
input [31:0] io_dccm_rdata_lo_m,
input [6:0] io_dccm_data_ecc_hi_r,
input [6:0] io_dccm_data_ecc_lo_r,
input [6:0] io_dccm_data_ecc_hi_m,
input [6:0] io_dccm_data_ecc_lo_m,
input io_ld_single_ecc_error_r,
input io_ld_single_ecc_error_r_ff,
input io_lsu_dccm_rden_m,
input io_addr_in_dccm_m,
input io_dma_dccm_wen,
input [31:0] io_dma_dccm_wdata_lo,
input [31:0] io_dma_dccm_wdata_hi,
input io_scan_mode,
output [31:0] io_sec_data_hi_r,
output [31:0] io_sec_data_lo_r,
output [31:0] io_sec_data_hi_m,
output [31:0] io_sec_data_lo_m,
output [31:0] io_sec_data_hi_r_ff,
output [31:0] io_sec_data_lo_r_ff,
output [6:0] io_dma_dccm_wdata_ecc_hi,
output [6:0] io_dma_dccm_wdata_ecc_lo,
output [6:0] io_stbuf_ecc_any,
output [6:0] io_sec_data_ecc_hi_r_ff,
output [6:0] io_sec_data_ecc_lo_r_ff,
output io_single_ecc_error_hi_r,
output io_single_ecc_error_lo_r,
output io_lsu_single_ecc_error_r,
output io_lsu_double_ecc_error_r,
output io_lsu_single_ecc_error_m,
output io_lsu_double_ecc_error_m
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 329:30]
wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 329:44]
wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 329:35]
wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 329:78]
wire _T_107 = ^_T_106; // @[el2_lib.scala 329:85]
wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 329:72]
wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 329:108]
wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 329:108]
wire _T_124 = ^_T_123; // @[el2_lib.scala 329:115]
wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 329:102]
wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 329:138]
wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 329:138]
wire _T_141 = ^_T_140; // @[el2_lib.scala 329:145]
wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 329:132]
wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 329:168]
wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 329:168]
wire _T_161 = ^_T_160; // @[el2_lib.scala 329:175]
wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 329:162]
wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 329:198]
wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 329:198]
wire _T_181 = ^_T_180; // @[el2_lib.scala 329:205]
wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 329:192]
wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 329:228]
wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 329:228]
wire _T_201 = ^_T_200; // @[el2_lib.scala 329:235]
wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 329:222]
wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 330:44]
wire _T_1155 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:70]
wire _T_1162 = io_lsu_pkt_m_load | io_lsu_pkt_m_store; // @[el2_lsu_ecc.scala 125:60]
wire _T_1163 = io_lsu_pkt_m_valid & _T_1162; // @[el2_lsu_ecc.scala 125:39]
wire _T_1164 = _T_1163 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:82]
wire is_ldst_m = _T_1164 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:102]
wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[el2_lsu_ecc.scala 124:39]
wire _T_1168 = ldst_dual_m | io_lsu_pkt_m_dma; // @[el2_lsu_ecc.scala 127:48]
wire _T_1169 = is_ldst_m & _T_1168; // @[el2_lsu_ecc.scala 127:33]
wire is_ldst_hi_m = _T_1169 & _T_1155; // @[el2_lsu_ecc.scala 127:68]
wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 330:31]
wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 330:53]
wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 331:55]
wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 331:53]
wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 335:44]
wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 335:44]
wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 335:44]
wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 335:44]
wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 335:44]
wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 335:44]
wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 335:44]
wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 335:44]
wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 335:44]
wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 335:44]
wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 335:44]
wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 335:44]
wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 335:44]
wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 335:44]
wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 335:44]
wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 335:44]
wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 335:44]
wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 335:44]
wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 335:44]
wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 335:44]
wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 335:44]
wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 335:44]
wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 335:44]
wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 335:44]
wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 335:44]
wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 335:44]
wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 335:44]
wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 335:44]
wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 335:44]
wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 335:44]
wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 335:44]
wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 335:44]
wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 335:44]
wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 335:44]
wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 335:44]
wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 335:44]
wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 335:44]
wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 335:44]
wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 335:44]
wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 338:69]
wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 338:69]
wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 338:69]
wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 338:69]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 338:69]
wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 338:76]
wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 338:31]
wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 329:30]
wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 329:44]
wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 329:35]
wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 329:78]
wire _T_485 = ^_T_484; // @[el2_lib.scala 329:85]
wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 329:72]
wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 329:108]
wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 329:108]
wire _T_502 = ^_T_501; // @[el2_lib.scala 329:115]
wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 329:102]
wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 329:138]
wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 329:138]
wire _T_519 = ^_T_518; // @[el2_lib.scala 329:145]
wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 329:132]
wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 329:168]
wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 329:168]
wire _T_539 = ^_T_538; // @[el2_lib.scala 329:175]
wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 329:162]
wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 329:198]
wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 329:198]
wire _T_559 = ^_T_558; // @[el2_lib.scala 329:205]
wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 329:192]
wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 329:228]
wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 329:228]
wire _T_579 = ^_T_578; // @[el2_lib.scala 329:235]
wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 329:222]
wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 330:44]
wire is_ldst_lo_m = is_ldst_m & _T_1155; // @[el2_lsu_ecc.scala 126:33]
wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 330:31]
wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 330:53]
wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 331:55]
wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 331:53]
wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 335:44]
wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 335:44]
wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 335:44]
wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 335:44]
wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 335:44]
wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 335:44]
wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 335:44]
wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 335:44]
wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 335:44]
wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 335:44]
wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 335:44]
wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 335:44]
wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 335:44]
wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 335:44]
wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 335:44]
wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 335:44]
wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 335:44]
wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 335:44]
wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 335:44]
wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 335:44]
wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 335:44]
wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 335:44]
wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 335:44]
wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 335:44]
wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 335:44]
wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 335:44]
wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 335:44]
wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 335:44]
wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 335:44]
wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 335:44]
wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 335:44]
wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 335:44]
wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 335:44]
wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 335:44]
wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 335:44]
wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 335:44]
wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 335:44]
wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 335:44]
wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 335:44]
wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 338:69]
wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 338:69]
wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 338:69]
wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 338:69]
wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 338:69]
wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 338:76]
wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 338:31]
wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58]
wire [31:0] _T_1182 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:89]
wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1182; // @[el2_lsu_ecc.scala 149:29]
wire [5:0] _T_856 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[26]}; // @[el2_lib.scala 280:22]
wire _T_857 = ^_T_856; // @[el2_lib.scala 280:29]
wire [6:0] _T_863 = {dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[11]}; // @[el2_lib.scala 280:40]
wire [14:0] _T_871 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_863}; // @[el2_lib.scala 280:40]
wire _T_872 = ^_T_871; // @[el2_lib.scala 280:47]
wire [6:0] _T_878 = {dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[4]}; // @[el2_lib.scala 280:58]
wire [14:0] _T_886 = {dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[19],dccm_wdata_lo_any[18],_T_878}; // @[el2_lib.scala 280:58]
wire _T_887 = ^_T_886; // @[el2_lib.scala 280:65]
wire [8:0] _T_895 = {dccm_wdata_lo_any[15],dccm_wdata_lo_any[14],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[8],dccm_wdata_lo_any[7],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[1]}; // @[el2_lib.scala 280:76]
wire [17:0] _T_904 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[30],dccm_wdata_lo_any[29],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[23],dccm_wdata_lo_any[22],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_895}; // @[el2_lib.scala 280:76]
wire _T_905 = ^_T_904; // @[el2_lib.scala 280:83]
wire [8:0] _T_913 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[12],dccm_wdata_lo_any[10],dccm_wdata_lo_any[9],dccm_wdata_lo_any[6],dccm_wdata_lo_any[5],dccm_wdata_lo_any[3],dccm_wdata_lo_any[2],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 280:94]
wire [17:0] _T_922 = {dccm_wdata_lo_any[31],dccm_wdata_lo_any[28],dccm_wdata_lo_any[27],dccm_wdata_lo_any[25],dccm_wdata_lo_any[24],dccm_wdata_lo_any[21],dccm_wdata_lo_any[20],dccm_wdata_lo_any[17],dccm_wdata_lo_any[16],_T_913}; // @[el2_lib.scala 280:94]
wire _T_923 = ^_T_922; // @[el2_lib.scala 280:101]
wire [8:0] _T_931 = {dccm_wdata_lo_any[13],dccm_wdata_lo_any[11],dccm_wdata_lo_any[10],dccm_wdata_lo_any[8],dccm_wdata_lo_any[6],dccm_wdata_lo_any[4],dccm_wdata_lo_any[3],dccm_wdata_lo_any[1],dccm_wdata_lo_any[0]}; // @[el2_lib.scala 280:112]
wire [17:0] _T_940 = {dccm_wdata_lo_any[30],dccm_wdata_lo_any[28],dccm_wdata_lo_any[26],dccm_wdata_lo_any[25],dccm_wdata_lo_any[23],dccm_wdata_lo_any[21],dccm_wdata_lo_any[19],dccm_wdata_lo_any[17],dccm_wdata_lo_any[15],_T_931}; // @[el2_lib.scala 280:112]
wire _T_941 = ^_T_940; // @[el2_lib.scala 280:119]
wire [5:0] _T_946 = {_T_857,_T_872,_T_887,_T_905,_T_923,_T_941}; // @[Cat.scala 29:58]
wire _T_947 = ^dccm_wdata_lo_any; // @[el2_lib.scala 281:27]
wire _T_948 = ^_T_946; // @[el2_lib.scala 281:37]
wire _T_949 = _T_947 ^ _T_948; // @[el2_lib.scala 281:32]
wire [31:0] _T_1186 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:89]
wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1186; // @[el2_lsu_ecc.scala 150:29]
wire [5:0] _T_1050 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[26]}; // @[el2_lib.scala 280:22]
wire _T_1051 = ^_T_1050; // @[el2_lib.scala 280:29]
wire [6:0] _T_1057 = {dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[11]}; // @[el2_lib.scala 280:40]
wire [14:0] _T_1065 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1057}; // @[el2_lib.scala 280:40]
wire _T_1066 = ^_T_1065; // @[el2_lib.scala 280:47]
wire [6:0] _T_1072 = {dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[4]}; // @[el2_lib.scala 280:58]
wire [14:0] _T_1080 = {dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[19],dccm_wdata_hi_any[18],_T_1072}; // @[el2_lib.scala 280:58]
wire _T_1081 = ^_T_1080; // @[el2_lib.scala 280:65]
wire [8:0] _T_1089 = {dccm_wdata_hi_any[15],dccm_wdata_hi_any[14],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[8],dccm_wdata_hi_any[7],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[1]}; // @[el2_lib.scala 280:76]
wire [17:0] _T_1098 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[30],dccm_wdata_hi_any[29],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[23],dccm_wdata_hi_any[22],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1089}; // @[el2_lib.scala 280:76]
wire _T_1099 = ^_T_1098; // @[el2_lib.scala 280:83]
wire [8:0] _T_1107 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[12],dccm_wdata_hi_any[10],dccm_wdata_hi_any[9],dccm_wdata_hi_any[6],dccm_wdata_hi_any[5],dccm_wdata_hi_any[3],dccm_wdata_hi_any[2],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 280:94]
wire [17:0] _T_1116 = {dccm_wdata_hi_any[31],dccm_wdata_hi_any[28],dccm_wdata_hi_any[27],dccm_wdata_hi_any[25],dccm_wdata_hi_any[24],dccm_wdata_hi_any[21],dccm_wdata_hi_any[20],dccm_wdata_hi_any[17],dccm_wdata_hi_any[16],_T_1107}; // @[el2_lib.scala 280:94]
wire _T_1117 = ^_T_1116; // @[el2_lib.scala 280:101]
wire [8:0] _T_1125 = {dccm_wdata_hi_any[13],dccm_wdata_hi_any[11],dccm_wdata_hi_any[10],dccm_wdata_hi_any[8],dccm_wdata_hi_any[6],dccm_wdata_hi_any[4],dccm_wdata_hi_any[3],dccm_wdata_hi_any[1],dccm_wdata_hi_any[0]}; // @[el2_lib.scala 280:112]
wire [17:0] _T_1134 = {dccm_wdata_hi_any[30],dccm_wdata_hi_any[28],dccm_wdata_hi_any[26],dccm_wdata_hi_any[25],dccm_wdata_hi_any[23],dccm_wdata_hi_any[21],dccm_wdata_hi_any[19],dccm_wdata_hi_any[17],dccm_wdata_hi_any[15],_T_1125}; // @[el2_lib.scala 280:112]
wire _T_1135 = ^_T_1134; // @[el2_lib.scala 280:119]
wire [5:0] _T_1140 = {_T_1051,_T_1066,_T_1081,_T_1099,_T_1117,_T_1135}; // @[Cat.scala 29:58]
wire _T_1141 = ^dccm_wdata_hi_any; // @[el2_lib.scala 281:27]
wire _T_1142 = ^_T_1140; // @[el2_lib.scala 281:37]
wire _T_1143 = _T_1141 ^ _T_1142; // @[el2_lib.scala 281:32]
reg _T_1174; // @[el2_lsu_ecc.scala 141:72]
reg _T_1175; // @[el2_lsu_ecc.scala 142:72]
reg _T_1176; // @[el2_lsu_ecc.scala 143:72]
reg _T_1177; // @[el2_lsu_ecc.scala 144:72]
reg [31:0] _T_1178; // @[el2_lsu_ecc.scala 145:72]
reg [31:0] _T_1179; // @[el2_lsu_ecc.scala 146:72]
reg [31:0] _T_1188; // @[Reg.scala 27:20]
reg [31:0] _T_1189; // @[Reg.scala 27:20]
assign io_sec_data_hi_r = _T_1178; // @[el2_lsu_ecc.scala 114:24 el2_lsu_ecc.scala 145:62]
assign io_sec_data_lo_r = _T_1179; // @[el2_lsu_ecc.scala 117:27 el2_lsu_ecc.scala 146:62]
assign io_sec_data_hi_m = {_T_364,_T_362}; // @[el2_lsu_ecc.scala 90:32 el2_lsu_ecc.scala 134:27]
assign io_sec_data_lo_m = {_T_742,_T_740}; // @[el2_lsu_ecc.scala 91:32 el2_lsu_ecc.scala 136:27]
assign io_sec_data_hi_r_ff = _T_1188; // @[el2_lsu_ecc.scala 157:23]
assign io_sec_data_lo_r_ff = _T_1189; // @[el2_lsu_ecc.scala 158:23]
assign io_dma_dccm_wdata_ecc_hi = {_T_1143,_T_1140}; // @[el2_lsu_ecc.scala 154:30]
assign io_dma_dccm_wdata_ecc_lo = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 155:30]
assign io_stbuf_ecc_any = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 153:30]
assign io_sec_data_ecc_hi_r_ff = {_T_1143,_T_1140}; // @[el2_lsu_ecc.scala 151:30]
assign io_sec_data_ecc_lo_r_ff = {_T_949,_T_946}; // @[el2_lsu_ecc.scala 152:30]
assign io_single_ecc_error_hi_r = _T_1177; // @[el2_lsu_ecc.scala 115:33 el2_lsu_ecc.scala 144:62]
assign io_single_ecc_error_lo_r = _T_1176; // @[el2_lsu_ecc.scala 118:33 el2_lsu_ecc.scala 143:62]
assign io_lsu_single_ecc_error_r = _T_1174; // @[el2_lsu_ecc.scala 120:33 el2_lsu_ecc.scala 141:62]
assign io_lsu_double_ecc_error_r = _T_1175; // @[el2_lsu_ecc.scala 121:33 el2_lsu_ecc.scala 142:62]
assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 92:30 el2_lsu_ecc.scala 138:33]
assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[el2_lsu_ecc.scala 93:30 el2_lsu_ecc.scala 139:33]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1174 = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
_T_1175 = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
_T_1176 = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
_T_1177 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T_1178 = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
_T_1179 = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
_T_1188 = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
_T_1189 = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_1174 = 1'h0;
end
if (reset) begin
_T_1175 = 1'h0;
end
if (reset) begin
_T_1176 = 1'h0;
end
if (reset) begin
_T_1177 = 1'h0;
end
if (reset) begin
_T_1178 = 32'h0;
end
if (reset) begin
_T_1179 = 32'h0;
end
if (reset) begin
_T_1188 = 32'h0;
end
if (reset) begin
_T_1189 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1174 <= 1'h0;
end else begin
_T_1174 <= io_lsu_single_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1175 <= 1'h0;
end else begin
_T_1175 <= io_lsu_double_ecc_error_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1176 <= 1'h0;
end else begin
_T_1176 <= _T_588 & _T_586[6];
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1177 <= 1'h0;
end else begin
_T_1177 <= _T_210 & _T_208[6];
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1178 <= 32'h0;
end else begin
_T_1178 <= io_sec_data_hi_m;
end
end
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
if (reset) begin
_T_1179 <= 32'h0;
end else begin
_T_1179 <= io_sec_data_lo_m;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_1188 <= 32'h0;
end else if (io_ld_single_ecc_error_r) begin
_T_1188 <= io_sec_data_hi_r;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_1189 <= 32'h0;
end else if (io_ld_single_ecc_error_r) begin
_T_1189 <= io_sec_data_lo_r;
end
end
endmodule

304
el2_lsu_lsc_ctl.anno.json Normal file
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@ -0,0 +1,304 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_by",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"sources":[
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"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
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"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store",
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"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
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]
},
{
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"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
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"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
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"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store_data_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_unsign",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_fir_addr",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_dccm_req",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_m_up",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_exu_lsu_rs1_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_addr",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_offset_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dword",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_store_data_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_picm_mask_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_m_store_data_bypass_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_in_pic_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_half",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_word",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_bus_read_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_ld_data_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_half",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_addr_external_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_by",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_load_ldst_bypass_d",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_load_ldst_bypass_d",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_store_data_bypass_m",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_store_data_bypass_m",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_dma",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_d_fast_int",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_p_fast_int",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_dma",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_flush_r",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_store",
"~el2_lsu_lsc_ctl|el2_lsu_lsc_ctl>io_lsu_pkt_r_load"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_lsc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1020
el2_lsu_lsc_ctl.fir Normal file
View File

File diff suppressed because it is too large Load Diff

1230
el2_lsu_lsc_ctl.v Normal file
View File

File diff suppressed because it is too large Load Diff

36
el2_lsu_stbuf.anno.json
View File

@ -1,10 +1,20 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m"
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
]
},
{
@ -50,11 +60,11 @@
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
@ -70,11 +80,11 @@
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
@ -86,10 +96,20 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m"
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
]
},
{

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el2_lsu_stbuf.fir
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el2_lsu_stbuf.v
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8
el2_lsu_trigger.anno.json
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@ -4,10 +4,10 @@
"sink":"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_valid",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_dma",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_dma",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_select",
@ -20,12 +20,12 @@
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_addr_m",
"~el2_lsu_trigger|el2_lsu_trigger>io_store_data_m",

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el2_lsu_trigger.v
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30
el2_pic_ctrl.anno.json Normal file
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@ -0,0 +1,30 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_pic_ctrl|el2_pic_ctrl>io_test",
"sources":[
"~el2_pic_ctrl|el2_pic_ctrl>io_extintsrc_req"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_pic_ctrl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_pic_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

372
el2_pic_ctrl.fir Normal file
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@ -0,0 +1,372 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_pic_ctrl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 331:24]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12]
clkhdr.CK <= io.clk @[beh_lib.scala 333:16]
clkhdr.EN <= io.en @[beh_lib.scala 334:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 331:24]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12]
clkhdr.CK <= io.clk @[beh_lib.scala 333:16]
clkhdr.EN <= io.en @[beh_lib.scala 334:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16]
extmodule TEC_RV_ICG_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 331:24]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12]
clkhdr.CK <= io.clk @[beh_lib.scala 333:16]
clkhdr.EN <= io.en @[beh_lib.scala 334:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16]
extmodule TEC_RV_ICG_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 331:24]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12]
clkhdr.CK <= io.clk @[beh_lib.scala 333:16]
clkhdr.EN <= io.en @[beh_lib.scala 334:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16]
extmodule TEC_RV_ICG_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 331:24]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12]
clkhdr.CK <= io.clk @[beh_lib.scala 333:16]
clkhdr.EN <= io.en @[beh_lib.scala 334:16]
clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16]
module rvsyncss :
input clock : Clock
input reset : Reset
output io : {flip din : UInt<31>, dout : UInt<31>, flip clk : Clock}
reg sync_ff1 : UInt, io.clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 32:43]
sync_ff1 <= io.din @[beh_lib.scala 32:43]
reg sync_ff2 : UInt, io.clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 33:43]
sync_ff2 <= sync_ff1 @[beh_lib.scala 33:43]
io.dout <= sync_ff2 @[beh_lib.scala 37:12]
module el2_pic_ctrl :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, flip extintsrc_req : UInt<32>, flip picm_rdaddr : UInt<32>, flip picm_wraddr : UInt<32>, flip picm_wr_data : UInt<32>, flip picm_wren : UInt<1>, flip picm_rden : UInt<1>, flip picm_mken : UInt<1>, flip meicurpl : UInt<4>, flip meipt : UInt<4>, mexintpend : UInt<1>, claimid : UInt<8>, pl : UInt<4>, picm_rd_data : UInt<32>, mhwakeup : UInt<1>, test : UInt}
io.mexintpend <= UInt<1>("h00") @[el2_pic_ctrl.scala 31:20]
io.claimid <= UInt<1>("h00") @[el2_pic_ctrl.scala 32:20]
io.pl <= UInt<1>("h00") @[el2_pic_ctrl.scala 33:20]
io.picm_rd_data <= UInt<1>("h00") @[el2_pic_ctrl.scala 34:20]
io.mhwakeup <= UInt<1>("h00") @[el2_pic_ctrl.scala 35:20]
wire GW_CONFIG : UInt<32>
GW_CONFIG <= UInt<1>("h00")
wire picm_rd_data_in : UInt<32>
picm_rd_data_in <= UInt<32>("h00")
wire intpend_rd_out : UInt<32>
intpend_rd_out <= UInt<32>("h00")
wire intenable_rd_out : UInt<1>
intenable_rd_out <= UInt<1>("h00")
wire intpriority_rd_out : UInt<4>
intpriority_rd_out <= UInt<4>("h00")
wire gw_config_rd_out : UInt<2>
gw_config_rd_out <= UInt<2>("h00")
wire intpriority_reg_we : UInt<32>
intpriority_reg_we <= UInt<32>("h00")
wire intpriority_reg_re : UInt<32>
intpriority_reg_re <= UInt<32>("h00")
wire intenable_reg : UInt<32>
intenable_reg <= UInt<32>("h00")
wire intenable_reg_we : UInt<32>
intenable_reg_we <= UInt<32>("h00")
wire intenable_reg_re : UInt<32>
intenable_reg_re <= UInt<32>("h00")
wire gw_config_reg_we : UInt<32>
gw_config_reg_we <= UInt<32>("h00")
wire gw_config_reg_re : UInt<32>
gw_config_reg_re <= UInt<32>("h00")
wire gw_clear_reg_we : UInt<32>
gw_clear_reg_we <= UInt<32>("h00")
wire intpend_reg_extended : UInt<64>
intpend_reg_extended <= UInt<64>("h00")
wire selected_int_priority : UInt<4>
selected_int_priority <= UInt<4>("h00")
wire config_reg : UInt<1>
config_reg <= UInt<1>("h00")
wire prithresh_reg_write : UInt<1>
prithresh_reg_write <= UInt<1>("h00")
wire prithresh_reg_read : UInt<1>
prithresh_reg_read <= UInt<1>("h00")
wire picm_wren_ff : UInt<1>
picm_wren_ff <= UInt<1>("h00")
wire picm_rden_ff : UInt<1>
picm_rden_ff <= UInt<1>("h00")
wire picm_raddr_ff : UInt<32>
picm_raddr_ff <= UInt<32>("h00")
wire picm_waddr_ff : UInt<32>
picm_waddr_ff <= UInt<32>("h00")
wire picm_wr_data_ff : UInt<32>
picm_wr_data_ff <= UInt<32>("h00")
wire mask : UInt<4>
mask <= UInt<4>("h00")
wire picm_mken_ff : UInt<1>
picm_mken_ff <= UInt<1>("h00")
wire claimid_in : UInt<8>
claimid_in <= UInt<8>("h00")
wire pl_in : UInt<4>
pl_in <= UInt<4>("h00")
wire extintsrc_req_sync : UInt<32>
extintsrc_req_sync <= UInt<32>("h00")
wire extintsrc_req_gw : UInt<32>
extintsrc_req_gw <= UInt<32>("h00")
wire pic_raddr_c1_clk : Clock @[el2_pic_ctrl.scala 127:42]
wire pic_data_c1_clk : Clock @[el2_pic_ctrl.scala 128:42]
wire pic_pri_c1_clk : Clock @[el2_pic_ctrl.scala 129:42]
wire pic_int_c1_clk : Clock @[el2_pic_ctrl.scala 130:42]
wire gw_config_c1_clk : Clock @[el2_pic_ctrl.scala 131:42]
reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 133:56]
_T <= io.picm_rdaddr @[el2_pic_ctrl.scala 133:56]
picm_raddr_ff <= _T @[el2_pic_ctrl.scala 133:46]
reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 134:57]
_T_1 <= io.picm_wraddr @[el2_pic_ctrl.scala 134:57]
picm_waddr_ff <= _T_1 @[el2_pic_ctrl.scala 134:46]
reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 135:55]
_T_2 <= io.picm_wren @[el2_pic_ctrl.scala 135:55]
picm_wren_ff <= _T_2 @[el2_pic_ctrl.scala 135:45]
reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 136:55]
_T_3 <= io.picm_rden @[el2_pic_ctrl.scala 136:55]
picm_rden_ff <= _T_3 @[el2_pic_ctrl.scala 136:45]
reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 137:55]
_T_4 <= io.picm_mken @[el2_pic_ctrl.scala 137:55]
picm_mken_ff <= _T_4 @[el2_pic_ctrl.scala 137:45]
reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 138:58]
_T_5 <= io.picm_wr_data @[el2_pic_ctrl.scala 138:58]
picm_wr_data_ff <= _T_5 @[el2_pic_ctrl.scala 138:48]
node _T_6 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctrl.scala 140:53]
node raddr_intenable_base_match = eq(_T_6, UInt<25>("h01e01840")) @[el2_pic_ctrl.scala 140:71]
node _T_7 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctrl.scala 141:53]
node raddr_intpriority_base_match = eq(_T_7, UInt<25>("h01e01800")) @[el2_pic_ctrl.scala 141:71]
node _T_8 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctrl.scala 142:53]
node raddr_config_gw_base_match = eq(_T_8, UInt<25>("h01e01880")) @[el2_pic_ctrl.scala 142:71]
node _T_9 = bits(picm_raddr_ff, 31, 0) @[el2_pic_ctrl.scala 143:53]
node raddr_config_pic_match = eq(_T_9, UInt<32>("h0f00c3000")) @[el2_pic_ctrl.scala 143:71]
node _T_10 = bits(picm_raddr_ff, 31, 6) @[el2_pic_ctrl.scala 144:53]
node addr_intpend_base_match = eq(_T_10, UInt<26>("h03c03040")) @[el2_pic_ctrl.scala 144:71]
node _T_11 = bits(picm_waddr_ff, 31, 0) @[el2_pic_ctrl.scala 146:53]
node waddr_config_pic_match = eq(_T_11, UInt<32>("h0f00c3000")) @[el2_pic_ctrl.scala 146:71]
node _T_12 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 147:53]
node addr_clear_gw_base_match = eq(_T_12, UInt<25>("h01e018a0")) @[el2_pic_ctrl.scala 147:71]
node _T_13 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 148:53]
node waddr_intpriority_base_match = eq(_T_13, UInt<25>("h01e01800")) @[el2_pic_ctrl.scala 148:71]
node _T_14 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 149:53]
node waddr_intenable_base_match = eq(_T_14, UInt<25>("h01e01840")) @[el2_pic_ctrl.scala 149:71]
node _T_15 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 150:53]
node waddr_config_gw_base_match = eq(_T_15, UInt<25>("h01e01880")) @[el2_pic_ctrl.scala 150:71]
node _T_16 = and(picm_rden_ff, picm_wren_ff) @[el2_pic_ctrl.scala 151:53]
node _T_17 = eq(picm_raddr_ff, picm_waddr_ff) @[el2_pic_ctrl.scala 151:86]
node picm_bypass_ff = and(_T_16, _T_17) @[el2_pic_ctrl.scala 151:68]
node _T_18 = or(io.picm_mken, io.picm_rden) @[el2_pic_ctrl.scala 155:42]
node pic_raddr_c1_clken = or(_T_18, io.clk_override) @[el2_pic_ctrl.scala 155:57]
node pic_data_c1_clken = or(io.picm_wren, io.clk_override) @[el2_pic_ctrl.scala 156:42]
node _T_19 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctrl.scala 157:59]
node _T_20 = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 157:108]
node _T_21 = or(_T_19, _T_20) @[el2_pic_ctrl.scala 157:76]
node pic_pri_c1_clken = or(_T_21, io.clk_override) @[el2_pic_ctrl.scala 157:124]
node _T_22 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctrl.scala 158:59]
node _T_23 = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 158:106]
node _T_24 = or(_T_22, _T_23) @[el2_pic_ctrl.scala 158:76]
node pic_int_c1_clken = or(_T_24, io.clk_override) @[el2_pic_ctrl.scala 158:122]
node _T_25 = and(waddr_config_gw_base_match, picm_wren_ff) @[el2_pic_ctrl.scala 159:59]
node _T_26 = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 159:108]
node _T_27 = or(_T_25, _T_26) @[el2_pic_ctrl.scala 159:76]
node gw_config_c1_clken = or(_T_27, io.clk_override) @[el2_pic_ctrl.scala 159:124]
inst pic_addr_c1_cgc of rvclkhdr @[el2_pic_ctrl.scala 162:32]
pic_addr_c1_cgc.clock <= clock
pic_addr_c1_cgc.reset <= reset
pic_addr_c1_cgc.io.en <= pic_raddr_c1_clken @[el2_pic_ctrl.scala 163:34]
pic_raddr_c1_clk <= pic_addr_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 163:89]
pic_addr_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 164:34]
pic_addr_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 164:89]
inst pic_data_c1_cgc of rvclkhdr_1 @[el2_pic_ctrl.scala 166:32]
pic_data_c1_cgc.clock <= clock
pic_data_c1_cgc.reset <= reset
pic_data_c1_cgc.io.en <= pic_data_c1_clken @[el2_pic_ctrl.scala 167:34]
pic_data_c1_clk <= pic_data_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 167:89]
pic_data_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 168:34]
pic_data_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 168:89]
inst pic_pri_c1_cgc of rvclkhdr_2 @[el2_pic_ctrl.scala 170:31]
pic_pri_c1_cgc.clock <= clock
pic_pri_c1_cgc.reset <= reset
pic_pri_c1_cgc.io.en <= pic_pri_c1_clken @[el2_pic_ctrl.scala 171:33]
pic_pri_c1_clk <= pic_pri_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 171:87]
pic_pri_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 172:33]
pic_pri_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 172:87]
inst pic_int_c1_cgc of rvclkhdr_3 @[el2_pic_ctrl.scala 174:32]
pic_int_c1_cgc.clock <= clock
pic_int_c1_cgc.reset <= reset
pic_int_c1_cgc.io.en <= pic_int_c1_clken @[el2_pic_ctrl.scala 175:33]
pic_int_c1_clk <= pic_int_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 175:87]
pic_int_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 176:33]
pic_int_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 176:87]
inst gw_config_c1_cgc of rvclkhdr_4 @[el2_pic_ctrl.scala 178:33]
gw_config_c1_cgc.clock <= clock
gw_config_c1_cgc.reset <= reset
gw_config_c1_cgc.io.en <= gw_config_c1_clken @[el2_pic_ctrl.scala 179:35]
gw_config_c1_clk <= gw_config_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 179:90]
gw_config_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 180:35]
gw_config_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 180:91]
inst sync_inst of rvsyncss @[el2_pic_ctrl.scala 185:26]
sync_inst.clock <= clock
sync_inst.reset <= reset
node _T_28 = shr(io.extintsrc_req, 1) @[el2_pic_ctrl.scala 186:48]
sync_inst.io.din <= _T_28 @[el2_pic_ctrl.scala 186:29]
node _T_29 = bits(io.extintsrc_req, 0, 0) @[el2_pic_ctrl.scala 187:71]
node _T_30 = cat(sync_inst.io.dout, _T_29) @[Cat.scala 29:58]
extintsrc_req_sync <= _T_30 @[el2_pic_ctrl.scala 187:29]
sync_inst.io.clk <= io.free_clk @[el2_pic_ctrl.scala 188:29]
io.test <= extintsrc_req_sync @[el2_pic_ctrl.scala 190:11]
node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[el2_pic_ctrl.scala 195:47]
node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[el2_pic_ctrl.scala 196:47]
node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctrl.scala 197:39]
node _T_31 = bits(config_reg_we, 0, 0) @[el2_pic_ctrl.scala 198:82]
reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_31 : @[Reg.scala 28:19]
_T_32 <= config_reg_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
config_reg <= _T_32 @[el2_pic_ctrl.scala 198:37]
node _T_33 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 204:31]
node _T_34 = not(pl_in) @[el2_pic_ctrl.scala 204:38]
node pl_in_q = mux(_T_33, _T_34, pl_in) @[el2_pic_ctrl.scala 204:20]
reg _T_35 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 205:47]
_T_35 <= claimid_in @[el2_pic_ctrl.scala 205:47]
io.claimid <= _T_35 @[el2_pic_ctrl.scala 205:37]
reg _T_36 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 206:42]
_T_36 <= pl_in_q @[el2_pic_ctrl.scala 206:42]
io.pl <= _T_36 @[el2_pic_ctrl.scala 206:32]
node _T_37 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 207:33]
node _T_38 = eq(io.meipt, UInt<1>("h00")) @[el2_pic_ctrl.scala 207:40]
node meipt_inv = mux(_T_37, _T_38, io.meipt) @[el2_pic_ctrl.scala 207:22]
node _T_39 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 208:36]
node _T_40 = eq(io.meicurpl, UInt<1>("h00")) @[el2_pic_ctrl.scala 208:43]
node meicurpl_inv = mux(_T_39, _T_40, io.meicurpl) @[el2_pic_ctrl.scala 208:25]
node _T_41 = gt(selected_int_priority, meipt_inv) @[el2_pic_ctrl.scala 209:47]
node _T_42 = gt(selected_int_priority, meicurpl_inv) @[el2_pic_ctrl.scala 209:86]
node mexintpend_in = and(_T_41, _T_42) @[el2_pic_ctrl.scala 209:60]
reg _T_43 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 210:50]
_T_43 <= mexintpend_in @[el2_pic_ctrl.scala 210:50]
io.mexintpend <= _T_43 @[el2_pic_ctrl.scala 210:40]
node _T_44 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 211:30]
node maxint = mux(_T_44, UInt<1>("h00"), UInt<4>("h0f")) @[el2_pic_ctrl.scala 211:19]
node mhwakeup_in = eq(pl_in_q, maxint) @[el2_pic_ctrl.scala 212:29]
reg _T_45 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 213:48]
_T_45 <= mhwakeup_in @[el2_pic_ctrl.scala 213:48]
io.mhwakeup <= _T_45 @[el2_pic_ctrl.scala 213:38]
node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 219:60]
node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 220:60]
node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 221:60]
node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 222:60]
node _T_46 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctrl.scala 227:98]
node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_pic_ctrl.scala 227:104]
node _T_48 = and(intpend_reg_read, _T_47) @[el2_pic_ctrl.scala 227:83]
node _T_49 = bits(_T_48, 0, 0) @[Bitwise.scala 72:15]
node _T_50 = mux(_T_49, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_51 = bits(intpend_reg_extended, 31, 0) @[el2_pic_ctrl.scala 227:140]
node _T_52 = and(_T_50, _T_51) @[el2_pic_ctrl.scala 227:118]
node _T_53 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctrl.scala 227:98]
node _T_54 = eq(_T_53, UInt<1>("h01")) @[el2_pic_ctrl.scala 227:104]
node _T_55 = and(intpend_reg_read, _T_54) @[el2_pic_ctrl.scala 227:83]
node _T_56 = bits(_T_55, 0, 0) @[Bitwise.scala 72:15]
node _T_57 = mux(_T_56, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_58 = bits(intpend_reg_extended, 63, 32) @[el2_pic_ctrl.scala 227:140]
node _T_59 = and(_T_57, _T_58) @[el2_pic_ctrl.scala 227:118]
node intpend_rd_part_out = cat(_T_59, _T_52) @[Cat.scala 29:58]
node _T_60 = bits(intpend_rd_part_out, 0, 0) @[el2_pic_ctrl.scala 228:79]
node _T_61 = bits(intpend_rd_part_out, 1, 1) @[el2_pic_ctrl.scala 228:79]
wire _T_62 : UInt<1>[2] @[el2_pic_ctrl.scala 228:56]
_T_62[0] <= _T_60 @[el2_pic_ctrl.scala 228:56]
_T_62[1] <= _T_61 @[el2_pic_ctrl.scala 228:56]
node _T_63 = or(_T_62[0], _T_62[1]) @[el2_pic_ctrl.scala 228:93]
intpend_rd_out <= _T_63 @[el2_pic_ctrl.scala 228:27]

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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[beh_lib.scala 331:24]
wire clkhdr_CK; // @[beh_lib.scala 331:24]
wire clkhdr_EN; // @[beh_lib.scala 331:24]
wire clkhdr_SE; // @[beh_lib.scala 331:24]
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 331:24]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 332:12]
assign clkhdr_CK = io_clk; // @[beh_lib.scala 333:16]
assign clkhdr_EN = io_en; // @[beh_lib.scala 334:16]
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 335:16]
endmodule
module rvsyncss(
input reset,
input [30:0] io_din,
output [30:0] io_dout,
input io_clk
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [30:0] sync_ff1; // @[beh_lib.scala 32:43]
reg [30:0] sync_ff2; // @[beh_lib.scala 33:43]
assign io_dout = sync_ff2; // @[beh_lib.scala 37:12]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_ff1 = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
sync_ff2 = _RAND_1[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
sync_ff1 = 31'h0;
end
if (reset) begin
sync_ff2 = 31'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_clk or posedge reset) begin
if (reset) begin
sync_ff1 <= 31'h0;
end else begin
sync_ff1 <= io_din;
end
end
always @(posedge io_clk or posedge reset) begin
if (reset) begin
sync_ff2 <= 31'h0;
end else begin
sync_ff2 <= sync_ff1;
end
end
endmodule
module el2_pic_ctrl(
input clock,
input reset,
input io_scan_mode,
input io_free_clk,
input io_active_clk,
input io_clk_override,
input [31:0] io_extintsrc_req,
input [31:0] io_picm_rdaddr,
input [31:0] io_picm_wraddr,
input [31:0] io_picm_wr_data,
input io_picm_wren,
input io_picm_rden,
input io_picm_mken,
input [3:0] io_meicurpl,
input [3:0] io_meipt,
output io_mexintpend,
output [7:0] io_claimid,
output [3:0] io_pl,
output [31:0] io_picm_rd_data,
output io_mhwakeup,
output [31:0] io_test
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
wire pic_addr_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 162:32]
wire pic_addr_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 162:32]
wire pic_addr_c1_cgc_io_en; // @[el2_pic_ctrl.scala 162:32]
wire pic_addr_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 162:32]
wire pic_data_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 166:32]
wire pic_data_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 166:32]
wire pic_data_c1_cgc_io_en; // @[el2_pic_ctrl.scala 166:32]
wire pic_data_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 166:32]
wire pic_pri_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 170:31]
wire pic_pri_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 170:31]
wire pic_pri_c1_cgc_io_en; // @[el2_pic_ctrl.scala 170:31]
wire pic_pri_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 170:31]
wire pic_int_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 174:32]
wire pic_int_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 174:32]
wire pic_int_c1_cgc_io_en; // @[el2_pic_ctrl.scala 174:32]
wire pic_int_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 174:32]
wire gw_config_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 178:33]
wire gw_config_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 178:33]
wire gw_config_c1_cgc_io_en; // @[el2_pic_ctrl.scala 178:33]
wire gw_config_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 178:33]
wire sync_inst_reset; // @[el2_pic_ctrl.scala 185:26]
wire [30:0] sync_inst_io_din; // @[el2_pic_ctrl.scala 185:26]
wire [30:0] sync_inst_io_dout; // @[el2_pic_ctrl.scala 185:26]
wire sync_inst_io_clk; // @[el2_pic_ctrl.scala 185:26]
wire pic_raddr_c1_clk = pic_addr_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 127:42 el2_pic_ctrl.scala 163:89]
reg [31:0] picm_raddr_ff; // @[el2_pic_ctrl.scala 133:56]
wire pic_data_c1_clk = pic_data_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 128:42 el2_pic_ctrl.scala 167:89]
reg [31:0] picm_waddr_ff; // @[el2_pic_ctrl.scala 134:57]
reg picm_wren_ff; // @[el2_pic_ctrl.scala 135:55]
reg picm_rden_ff; // @[el2_pic_ctrl.scala 136:55]
reg [31:0] picm_wr_data_ff; // @[el2_pic_ctrl.scala 138:58]
wire raddr_intenable_base_match = picm_raddr_ff[31:7] == 25'h1e01840; // @[el2_pic_ctrl.scala 140:71]
wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctrl.scala 141:71]
wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctrl.scala 142:71]
wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[el2_pic_ctrl.scala 146:71]
wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctrl.scala 148:71]
wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctrl.scala 150:71]
wire _T_18 = io_picm_mken | io_picm_rden; // @[el2_pic_ctrl.scala 155:42]
wire _T_19 = waddr_intpriority_base_match & picm_wren_ff; // @[el2_pic_ctrl.scala 157:59]
wire _T_20 = raddr_intpriority_base_match & picm_rden_ff; // @[el2_pic_ctrl.scala 157:108]
wire _T_21 = _T_19 | _T_20; // @[el2_pic_ctrl.scala 157:76]
wire _T_23 = raddr_intenable_base_match & picm_rden_ff; // @[el2_pic_ctrl.scala 158:106]
wire _T_24 = _T_19 | _T_23; // @[el2_pic_ctrl.scala 158:76]
wire _T_25 = waddr_config_gw_base_match & picm_wren_ff; // @[el2_pic_ctrl.scala 159:59]
wire _T_26 = raddr_config_gw_base_match & picm_rden_ff; // @[el2_pic_ctrl.scala 159:108]
wire _T_27 = _T_25 | _T_26; // @[el2_pic_ctrl.scala 159:76]
wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[el2_pic_ctrl.scala 195:47]
wire config_reg_in = picm_wr_data_ff[0]; // @[el2_pic_ctrl.scala 197:39]
reg config_reg; // @[Reg.scala 27:20]
wire [3:0] pl_in_q = config_reg ? 4'hf : 4'h0; // @[el2_pic_ctrl.scala 204:20]
reg [3:0] _T_36; // @[el2_pic_ctrl.scala 206:42]
wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[el2_pic_ctrl.scala 211:19]
reg _T_45; // @[el2_pic_ctrl.scala 213:48]
rvclkhdr pic_addr_c1_cgc ( // @[el2_pic_ctrl.scala 162:32]
.io_l1clk(pic_addr_c1_cgc_io_l1clk),
.io_clk(pic_addr_c1_cgc_io_clk),
.io_en(pic_addr_c1_cgc_io_en),
.io_scan_mode(pic_addr_c1_cgc_io_scan_mode)
);
rvclkhdr pic_data_c1_cgc ( // @[el2_pic_ctrl.scala 166:32]
.io_l1clk(pic_data_c1_cgc_io_l1clk),
.io_clk(pic_data_c1_cgc_io_clk),
.io_en(pic_data_c1_cgc_io_en),
.io_scan_mode(pic_data_c1_cgc_io_scan_mode)
);
rvclkhdr pic_pri_c1_cgc ( // @[el2_pic_ctrl.scala 170:31]
.io_l1clk(pic_pri_c1_cgc_io_l1clk),
.io_clk(pic_pri_c1_cgc_io_clk),
.io_en(pic_pri_c1_cgc_io_en),
.io_scan_mode(pic_pri_c1_cgc_io_scan_mode)
);
rvclkhdr pic_int_c1_cgc ( // @[el2_pic_ctrl.scala 174:32]
.io_l1clk(pic_int_c1_cgc_io_l1clk),
.io_clk(pic_int_c1_cgc_io_clk),
.io_en(pic_int_c1_cgc_io_en),
.io_scan_mode(pic_int_c1_cgc_io_scan_mode)
);
rvclkhdr gw_config_c1_cgc ( // @[el2_pic_ctrl.scala 178:33]
.io_l1clk(gw_config_c1_cgc_io_l1clk),
.io_clk(gw_config_c1_cgc_io_clk),
.io_en(gw_config_c1_cgc_io_en),
.io_scan_mode(gw_config_c1_cgc_io_scan_mode)
);
rvsyncss sync_inst ( // @[el2_pic_ctrl.scala 185:26]
.reset(sync_inst_reset),
.io_din(sync_inst_io_din),
.io_dout(sync_inst_io_dout),
.io_clk(sync_inst_io_clk)
);
assign io_mexintpend = 1'h0; // @[el2_pic_ctrl.scala 31:20 el2_pic_ctrl.scala 210:40]
assign io_claimid = 8'h0; // @[el2_pic_ctrl.scala 32:20 el2_pic_ctrl.scala 205:37]
assign io_pl = _T_36; // @[el2_pic_ctrl.scala 33:20 el2_pic_ctrl.scala 206:32]
assign io_picm_rd_data = 32'h0; // @[el2_pic_ctrl.scala 34:20]
assign io_mhwakeup = _T_45; // @[el2_pic_ctrl.scala 35:20 el2_pic_ctrl.scala 213:38]
assign io_test = {sync_inst_io_dout,io_extintsrc_req[0]}; // @[el2_pic_ctrl.scala 190:11]
assign pic_addr_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 164:34]
assign pic_addr_c1_cgc_io_en = _T_18 | io_clk_override; // @[el2_pic_ctrl.scala 163:34]
assign pic_addr_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 164:89]
assign pic_data_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 168:34]
assign pic_data_c1_cgc_io_en = io_picm_wren | io_clk_override; // @[el2_pic_ctrl.scala 167:34]
assign pic_data_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 168:89]
assign pic_pri_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 172:33]
assign pic_pri_c1_cgc_io_en = _T_21 | io_clk_override; // @[el2_pic_ctrl.scala 171:33]
assign pic_pri_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 172:87]
assign pic_int_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 176:33]
assign pic_int_c1_cgc_io_en = _T_24 | io_clk_override; // @[el2_pic_ctrl.scala 175:33]
assign pic_int_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 176:87]
assign gw_config_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 180:35]
assign gw_config_c1_cgc_io_en = _T_27 | io_clk_override; // @[el2_pic_ctrl.scala 179:35]
assign gw_config_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 180:91]
assign sync_inst_reset = reset;
assign sync_inst_io_din = io_extintsrc_req[31:1]; // @[el2_pic_ctrl.scala 186:29]
assign sync_inst_io_clk = io_free_clk; // @[el2_pic_ctrl.scala 188:29]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
picm_raddr_ff = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
picm_waddr_ff = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
picm_wren_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
picm_rden_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
picm_wr_data_ff = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
config_reg = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_36 = _RAND_6[3:0];
_RAND_7 = {1{`RANDOM}};
_T_45 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
picm_raddr_ff = 32'h0;
end
if (reset) begin
picm_waddr_ff = 32'h0;
end
if (reset) begin
picm_wren_ff = 1'h0;
end
if (reset) begin
picm_rden_ff = 1'h0;
end
if (reset) begin
picm_wr_data_ff = 32'h0;
end
if (reset) begin
config_reg = 1'h0;
end
if (reset) begin
_T_36 = 4'h0;
end
if (reset) begin
_T_45 = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge pic_raddr_c1_clk or posedge reset) begin
if (reset) begin
picm_raddr_ff <= 32'h0;
end else begin
picm_raddr_ff <= io_picm_rdaddr;
end
end
always @(posedge pic_data_c1_clk or posedge reset) begin
if (reset) begin
picm_waddr_ff <= 32'h0;
end else begin
picm_waddr_ff <= io_picm_wraddr;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
picm_wren_ff <= 1'h0;
end else begin
picm_wren_ff <= io_picm_wren;
end
end
always @(posedge io_active_clk or posedge reset) begin
if (reset) begin
picm_rden_ff <= 1'h0;
end else begin
picm_rden_ff <= io_picm_rden;
end
end
always @(posedge pic_data_c1_clk or posedge reset) begin
if (reset) begin
picm_wr_data_ff <= 32'h0;
end else begin
picm_wr_data_ff <= io_picm_wr_data;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
config_reg <= 1'h0;
end else if (config_reg_we) begin
config_reg <= config_reg_in;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
_T_36 <= 4'h0;
end else if (config_reg) begin
_T_36 <= 4'hf;
end else begin
_T_36 <= 4'h0;
end
end
always @(posedge io_free_clk or posedge reset) begin
if (reset) begin
_T_45 <= 1'h0;
end else begin
_T_45 <= pl_in_q == maxint;
end
end
endmodule

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