2020-10-06 22:30:06 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_iccm_mem :
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module el2_ifu_iccm_mem :
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input clock : Clock
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input reset : UInt<1>
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2020-10-08 14:44:49 +08:00
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output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_addr : UInt[4]}
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2020-10-06 22:30:06 +08:00
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io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
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io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
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node _T = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 24:38]
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node _T_1 = eq(_T, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 24:43]
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node _T_2 = bits(_T_1, 0, 0) @[el2_ifu_iccm_mem.scala 24:51]
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node addr_inc = mux(_T_2, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_iccm_mem.scala 24:21]
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node _T_3 = bits(io.iccm_rw_addr, 14, 0) @[el2_ifu_iccm_mem.scala 25:38]
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node _T_4 = add(_T_3, addr_inc) @[el2_ifu_iccm_mem.scala 25:54]
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node addr_bank_inc = tail(_T_4, 1) @[el2_ifu_iccm_mem.scala 25:54]
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wire iccm_bank_wr_data : UInt<39>[4] @[el2_ifu_iccm_mem.scala 27:35]
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node _T_5 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[0] <= _T_5 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_6 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[1] <= _T_6 @[el2_ifu_iccm_mem.scala 30:36]
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node _T_7 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36]
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2020-10-08 14:27:32 +08:00
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node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_11 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_13 = or(_T_10, _T_12) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_0 = and(io.iccm_wren, _T_13) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_16 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_18 = or(_T_15, _T_17) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_1 = and(io.iccm_wren, _T_18) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_21 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_22 = eq(_T_21, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_23 = or(_T_20, _T_22) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_2 = and(io.iccm_wren, _T_23) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_26 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64]
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2020-10-08 15:38:19 +08:00
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node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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2020-10-08 14:08:49 +08:00
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node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 38:55]
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node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 38:55]
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node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 38:55]
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node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 38:55]
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cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 41:21]
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node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 43:68]
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wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 43:51]
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node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 44:70]
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wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28]
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wire inter : UInt<39>[4] @[el2_ifu_iccm_mem.scala 47:19]
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2020-10-08 15:38:19 +08:00
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node _T_93 = bits(write_vec[0], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_93 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_94 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_94[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_95 = bits(write_vec[1], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_95 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_96 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_96[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_97 = bits(write_vec[2], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_97 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_98 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_98[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_99 = bits(write_vec[3], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_99 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_100 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_100[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_101 = bits(read_enable[0], 0, 0) @[Bitwise.scala 72:15]
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node _T_102 = mux(_T_101, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_103 = iccm_mem[UInt<1>("h00")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_104 = bits(addr_bank_0, 1, 0)
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node _T_105 = and(_T_102, _T_103[_T_104]) @[el2_ifu_iccm_mem.scala 51:67]
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node _T_106 = bits(read_enable[1], 0, 0) @[Bitwise.scala 72:15]
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node _T_107 = mux(_T_106, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_108 = iccm_mem[UInt<1>("h01")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_109 = bits(addr_bank_1, 1, 0)
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node _T_110 = and(_T_107, _T_108[_T_109]) @[el2_ifu_iccm_mem.scala 51:67]
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node _T_111 = bits(read_enable[2], 0, 0) @[Bitwise.scala 72:15]
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node _T_112 = mux(_T_111, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_113 = iccm_mem[UInt<2>("h02")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_114 = bits(addr_bank_2, 1, 0)
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node _T_115 = and(_T_112, _T_113[_T_114]) @[el2_ifu_iccm_mem.scala 51:67]
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node _T_116 = bits(read_enable[3], 0, 0) @[Bitwise.scala 72:15]
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node _T_117 = mux(_T_116, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_118 = iccm_mem[UInt<2>("h03")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_119 = bits(addr_bank_3, 1, 0)
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node _T_120 = and(_T_117, _T_118[_T_119]) @[el2_ifu_iccm_mem.scala 51:67]
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inter[0] <= _T_105 @[el2_ifu_iccm_mem.scala 51:9]
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inter[1] <= _T_110 @[el2_ifu_iccm_mem.scala 51:9]
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inter[2] <= _T_115 @[el2_ifu_iccm_mem.scala 51:9]
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inter[3] <= _T_120 @[el2_ifu_iccm_mem.scala 51:9]
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reg _T_121 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_121 <= inter[0] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[0] <= _T_121 @[el2_ifu_iccm_mem.scala 52:52]
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reg _T_122 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_122 <= inter[1] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[1] <= _T_122 @[el2_ifu_iccm_mem.scala 52:52]
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reg _T_123 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_123 <= inter[2] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[2] <= _T_123 @[el2_ifu_iccm_mem.scala 52:52]
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reg _T_124 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_124 <= inter[3] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[3] <= _T_124 @[el2_ifu_iccm_mem.scala 52:52]
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io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 54:21]
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io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 54:21]
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io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 54:21]
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io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 54:21]
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2020-10-06 22:30:06 +08:00
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wire redundant_valid : UInt<2>
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redundant_valid <= UInt<1>("h00")
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2020-10-08 15:38:19 +08:00
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 60:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:21]
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node _T_125 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_126 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_127 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_128 = eq(_T_126, _T_127) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_129 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_131 = and(_T_128, _T_130) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_132 = and(_T_125, _T_131) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_133 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_136 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_139 = or(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_140 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_141 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_142 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_143 = eq(_T_141, _T_142) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_144 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_145 = eq(_T_144, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_146 = and(_T_143, _T_145) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_147 = and(_T_140, _T_146) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_148 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_151 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_152 = eq(_T_151, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_154 = or(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_155 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_156 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_157 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_158 = eq(_T_156, _T_157) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_159 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_160 = eq(_T_159, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_161 = and(_T_158, _T_160) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_162 = and(_T_155, _T_161) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_163 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_164 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_165 = eq(_T_163, _T_164) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_166 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_167 = eq(_T_166, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_168 = and(_T_165, _T_167) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_169 = or(_T_162, _T_168) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_170 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_171 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_172 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_173 = eq(_T_171, _T_172) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_174 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_175 = eq(_T_174, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_176 = and(_T_173, _T_175) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_177 = and(_T_170, _T_176) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_178 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_179 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_180 = eq(_T_178, _T_179) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_181 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_182 = eq(_T_181, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_183 = and(_T_180, _T_182) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_184 = or(_T_177, _T_183) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_185 = cat(_T_184, _T_169) @[Cat.scala 29:58]
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node _T_186 = cat(_T_185, _T_154) @[Cat.scala 29:58]
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node sel_red1 = cat(_T_186, _T_139) @[Cat.scala 29:58]
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node _T_187 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
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node _T_188 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
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node _T_189 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
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node _T_190 = eq(_T_188, _T_189) @[el2_ifu_iccm_mem.scala 65:105]
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node _T_191 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
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node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169]
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node _T_193 = and(_T_190, _T_192) @[el2_ifu_iccm_mem.scala 65:145]
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node _T_194 = and(_T_187, _T_193) @[el2_ifu_iccm_mem.scala 65:71]
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node _T_195 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
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node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
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node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 66:37]
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node _T_198 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
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node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99]
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node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 66:77]
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node _T_201 = or(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 65:179]
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node _T_202 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
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node _T_203 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
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node _T_204 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
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node _T_205 = eq(_T_203, _T_204) @[el2_ifu_iccm_mem.scala 65:105]
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node _T_206 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
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node _T_207 = eq(_T_206, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169]
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node _T_208 = and(_T_205, _T_207) @[el2_ifu_iccm_mem.scala 65:145]
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node _T_209 = and(_T_202, _T_208) @[el2_ifu_iccm_mem.scala 65:71]
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node _T_210 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
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node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
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node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 66:37]
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node _T_213 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
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node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99]
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node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 66:77]
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node _T_216 = or(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 65:179]
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node _T_217 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
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node _T_218 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
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node _T_219 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
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node _T_220 = eq(_T_218, _T_219) @[el2_ifu_iccm_mem.scala 65:105]
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node _T_221 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
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node _T_222 = eq(_T_221, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169]
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node _T_223 = and(_T_220, _T_222) @[el2_ifu_iccm_mem.scala 65:145]
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node _T_224 = and(_T_217, _T_223) @[el2_ifu_iccm_mem.scala 65:71]
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node _T_225 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
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node _T_226 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
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node _T_227 = eq(_T_225, _T_226) @[el2_ifu_iccm_mem.scala 66:37]
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node _T_228 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
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node _T_229 = eq(_T_228, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99]
|
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|
|
node _T_230 = and(_T_227, _T_229) @[el2_ifu_iccm_mem.scala 66:77]
|
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|
node _T_231 = or(_T_224, _T_230) @[el2_ifu_iccm_mem.scala 65:179]
|
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|
node _T_232 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
|
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|
node _T_233 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
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|
node _T_234 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
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|
node _T_235 = eq(_T_233, _T_234) @[el2_ifu_iccm_mem.scala 65:105]
|
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|
node _T_236 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
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node _T_237 = eq(_T_236, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169]
|
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node _T_238 = and(_T_235, _T_237) @[el2_ifu_iccm_mem.scala 65:145]
|
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|
node _T_239 = and(_T_232, _T_238) @[el2_ifu_iccm_mem.scala 65:71]
|
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|
node _T_240 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
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|
node _T_241 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
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|
node _T_242 = eq(_T_240, _T_241) @[el2_ifu_iccm_mem.scala 66:37]
|
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|
node _T_243 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
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|
node _T_244 = eq(_T_243, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99]
|
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node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 66:77]
|
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node _T_246 = or(_T_239, _T_245) @[el2_ifu_iccm_mem.scala 65:179]
|
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node _T_247 = cat(_T_246, _T_231) @[Cat.scala 29:58]
|
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|
node _T_248 = cat(_T_247, _T_216) @[Cat.scala 29:58]
|
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|
|
node sel_red0 = cat(_T_248, _T_201) @[Cat.scala 29:58]
|
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|
|
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 68:27]
|
|
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|
|
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 68:27]
|
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|
|
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 69:27]
|
|
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|
|
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 69:27]
|
|
|
|
|
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 70:28]
|
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|
|
|
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 71:18]
|
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|
|
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 71:18]
|
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|
|
node _T_249 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:47]
|
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|
|
node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
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|
node _T_251 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 74:47]
|
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|
node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
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|
node _T_253 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47]
|
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|
node _T_254 = not(_T_253) @[el2_ifu_iccm_mem.scala 75:36]
|
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|
node _T_255 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:64]
|
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|
node _T_256 = not(_T_255) @[el2_ifu_iccm_mem.scala 75:53]
|
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|
node _T_257 = and(_T_254, _T_256) @[el2_ifu_iccm_mem.scala 75:51]
|
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node _T_258 = bits(_T_257, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
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node _T_259 = mux(_T_250, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_260 = mux(_T_252, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_261 = mux(_T_258, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72]
|
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|
node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 15:38:19 +08:00
|
|
|
iccm_bank_dout_fn_0 <= _T_263 @[Mux.scala 27:72]
|
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|
|
node _T_264 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:47]
|
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node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
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node _T_266 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 74:47]
|
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node _T_267 = bits(_T_266, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
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node _T_268 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47]
|
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node _T_269 = not(_T_268) @[el2_ifu_iccm_mem.scala 75:36]
|
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|
node _T_270 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:64]
|
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|
node _T_271 = not(_T_270) @[el2_ifu_iccm_mem.scala 75:53]
|
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|
node _T_272 = and(_T_269, _T_271) @[el2_ifu_iccm_mem.scala 75:51]
|
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|
node _T_273 = bits(_T_272, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
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|
|
node _T_274 = mux(_T_265, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_275 = mux(_T_267, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_276 = mux(_T_273, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_277 = or(_T_274, _T_275) @[Mux.scala 27:72]
|
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|
|
node _T_278 = or(_T_277, _T_276) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 15:38:19 +08:00
|
|
|
iccm_bank_dout_fn_1 <= _T_278 @[Mux.scala 27:72]
|
|
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|
|
node _T_279 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:47]
|
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|
node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
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|
|
node _T_281 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 74:47]
|
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|
|
|
node _T_282 = bits(_T_281, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
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|
|
node _T_283 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47]
|
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|
|
node _T_284 = not(_T_283) @[el2_ifu_iccm_mem.scala 75:36]
|
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|
node _T_285 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:64]
|
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|
node _T_286 = not(_T_285) @[el2_ifu_iccm_mem.scala 75:53]
|
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|
|
node _T_287 = and(_T_284, _T_286) @[el2_ifu_iccm_mem.scala 75:51]
|
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|
|
node _T_288 = bits(_T_287, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
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|
|
node _T_289 = mux(_T_280, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_290 = mux(_T_282, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_291 = mux(_T_288, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_292 = or(_T_289, _T_290) @[Mux.scala 27:72]
|
|
|
|
|
node _T_293 = or(_T_292, _T_291) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 15:38:19 +08:00
|
|
|
iccm_bank_dout_fn_2 <= _T_293 @[Mux.scala 27:72]
|
|
|
|
|
node _T_294 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:47]
|
|
|
|
|
node _T_295 = bits(_T_294, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
|
|
|
|
node _T_296 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 74:47]
|
|
|
|
|
node _T_297 = bits(_T_296, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
|
|
|
|
node _T_298 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47]
|
|
|
|
|
node _T_299 = not(_T_298) @[el2_ifu_iccm_mem.scala 75:36]
|
|
|
|
|
node _T_300 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:64]
|
|
|
|
|
node _T_301 = not(_T_300) @[el2_ifu_iccm_mem.scala 75:53]
|
|
|
|
|
node _T_302 = and(_T_299, _T_301) @[el2_ifu_iccm_mem.scala 75:51]
|
|
|
|
|
node _T_303 = bits(_T_302, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
|
|
|
|
node _T_304 = mux(_T_295, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_305 = mux(_T_297, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_306 = mux(_T_303, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_307 = or(_T_304, _T_305) @[Mux.scala 27:72]
|
|
|
|
|
node _T_308 = or(_T_307, _T_306) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 15:38:19 +08:00
|
|
|
iccm_bank_dout_fn_3 <= _T_308 @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire redundant_lru : UInt<1>
|
|
|
|
|
redundant_lru <= UInt<1>("h00")
|
2020-10-08 15:38:19 +08:00
|
|
|
node _T_309 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 77:20]
|
|
|
|
|
node r0_addr_en = and(_T_309, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 77:35]
|
|
|
|
|
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 78:35]
|
|
|
|
|
node _T_310 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 79:63]
|
|
|
|
|
node _T_311 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 79:78]
|
|
|
|
|
node _T_312 = or(_T_310, _T_311) @[el2_ifu_iccm_mem.scala 79:67]
|
|
|
|
|
node _T_313 = and(_T_312, io.iccm_rden) @[el2_ifu_iccm_mem.scala 79:83]
|
|
|
|
|
node _T_314 = and(_T_313, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 79:98]
|
|
|
|
|
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_314) @[el2_ifu_iccm_mem.scala 79:50]
|
|
|
|
|
node _T_315 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 80:55]
|
|
|
|
|
node _T_316 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 80:84]
|
|
|
|
|
node _T_317 = mux(_T_316, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 80:74]
|
|
|
|
|
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_315, _T_317) @[el2_ifu_iccm_mem.scala 80:29]
|
|
|
|
|
reg _T_318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when redundant_lru_en : @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
_T_318 <= redundant_lru_in @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
redundant_lru <= _T_318 @[el2_ifu_iccm_mem.scala 81:17]
|
|
|
|
|
node _T_319 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 82:52]
|
|
|
|
|
reg _T_320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
_T_320 <= _T_319 @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
redundant_address[0] <= _T_320 @[el2_ifu_iccm_mem.scala 82:24]
|
|
|
|
|
node _T_321 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 83:52]
|
|
|
|
|
node _T_322 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 83:85]
|
|
|
|
|
reg _T_323 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_322 : @[Reg.scala 28:19]
|
|
|
|
|
_T_323 <= _T_321 @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
redundant_address[1] <= _T_323 @[el2_ifu_iccm_mem.scala 83:24]
|
|
|
|
|
node _T_324 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:57]
|
|
|
|
|
reg _T_325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_324 : @[Reg.scala 28:19]
|
|
|
|
|
_T_325 <= UInt<1>("h01") @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
reg _T_326 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
_T_326 <= UInt<1>("h01") @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
|
|
|
node _T_327 = cat(_T_325, _T_326) @[Cat.scala 29:58]
|
|
|
|
|
redundant_valid <= _T_327 @[el2_ifu_iccm_mem.scala 84:19]
|
|
|
|
|
node _T_328 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45]
|
|
|
|
|
node _T_329 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 86:85]
|
|
|
|
|
node _T_330 = eq(_T_328, _T_329) @[el2_ifu_iccm_mem.scala 86:61]
|
|
|
|
|
node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22]
|
|
|
|
|
node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:48]
|
|
|
|
|
node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 87:26]
|
|
|
|
|
node _T_334 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70]
|
|
|
|
|
node _T_335 = eq(_T_334, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75]
|
|
|
|
|
node _T_336 = or(_T_333, _T_335) @[el2_ifu_iccm_mem.scala 87:52]
|
|
|
|
|
node _T_337 = and(_T_330, _T_336) @[el2_ifu_iccm_mem.scala 86:102]
|
|
|
|
|
node _T_338 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 87:101]
|
|
|
|
|
node _T_339 = and(_T_337, _T_338) @[el2_ifu_iccm_mem.scala 87:84]
|
|
|
|
|
node _T_340 = and(_T_339, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105]
|
|
|
|
|
node _T_341 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6]
|
|
|
|
|
node _T_342 = and(_T_341, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21]
|
|
|
|
|
node redundant_data0_en = or(_T_340, _T_342) @[el2_ifu_iccm_mem.scala 87:121]
|
|
|
|
|
node _T_343 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49]
|
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node _T_344 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:73]
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node _T_345 = and(_T_343, _T_344) @[el2_ifu_iccm_mem.scala 89:52]
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node _T_346 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:100]
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node _T_347 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122]
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node _T_348 = eq(_T_347, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127]
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node _T_349 = and(_T_346, _T_348) @[el2_ifu_iccm_mem.scala 89:104]
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node _T_350 = or(_T_345, _T_349) @[el2_ifu_iccm_mem.scala 89:78]
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node _T_351 = bits(_T_350, 0, 0) @[el2_ifu_iccm_mem.scala 89:137]
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node _T_352 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20]
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node _T_353 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44]
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node redundant_data0_in = mux(_T_351, _T_352, _T_353) @[el2_ifu_iccm_mem.scala 89:31]
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node _T_354 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78]
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reg _T_355 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_354 : @[Reg.scala 28:19]
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_T_355 <= redundant_data0_in @[Reg.scala 28:23]
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2020-10-06 22:30:06 +08:00
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skip @[Reg.scala 28:19]
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2020-10-08 15:38:19 +08:00
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redundant_data[0] <= _T_355 @[el2_ifu_iccm_mem.scala 91:21]
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node _T_356 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45]
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node _T_357 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 93:85]
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node _T_358 = eq(_T_356, _T_357) @[el2_ifu_iccm_mem.scala 93:61]
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node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22]
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node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:48]
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node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 94:26]
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node _T_362 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70]
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node _T_363 = eq(_T_362, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75]
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node _T_364 = or(_T_361, _T_363) @[el2_ifu_iccm_mem.scala 94:52]
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node _T_365 = and(_T_358, _T_364) @[el2_ifu_iccm_mem.scala 93:102]
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node _T_366 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 94:101]
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node _T_367 = and(_T_365, _T_366) @[el2_ifu_iccm_mem.scala 94:84]
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node _T_368 = and(_T_367, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105]
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node _T_369 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6]
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node _T_370 = and(_T_369, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21]
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node redundant_data1_en = or(_T_368, _T_370) @[el2_ifu_iccm_mem.scala 94:121]
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node _T_371 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49]
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node _T_372 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:73]
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node _T_373 = and(_T_371, _T_372) @[el2_ifu_iccm_mem.scala 96:52]
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node _T_374 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:100]
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node _T_375 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122]
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node _T_376 = eq(_T_375, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127]
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node _T_377 = and(_T_374, _T_376) @[el2_ifu_iccm_mem.scala 96:104]
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node _T_378 = or(_T_373, _T_377) @[el2_ifu_iccm_mem.scala 96:78]
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node _T_379 = bits(_T_378, 0, 0) @[el2_ifu_iccm_mem.scala 96:137]
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node _T_380 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20]
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node _T_381 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44]
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node redundant_data1_in = mux(_T_379, _T_380, _T_381) @[el2_ifu_iccm_mem.scala 96:31]
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node _T_382 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78]
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reg _T_383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_382 : @[Reg.scala 28:19]
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_T_383 <= redundant_data1_in @[Reg.scala 28:23]
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2020-10-06 22:30:06 +08:00
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skip @[Reg.scala 28:19]
|
2020-10-08 15:38:19 +08:00
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redundant_data[1] <= _T_383 @[el2_ifu_iccm_mem.scala 98:21]
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node _T_384 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 100:50]
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reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 100:34]
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iccm_rd_addr_lo_q <= _T_384 @[el2_ifu_iccm_mem.scala 100:34]
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node _T_385 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 101:48]
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reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 101:34]
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iccm_rd_addr_hi_q <= _T_385 @[el2_ifu_iccm_mem.scala 101:34]
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node _T_386 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 103:86]
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node _T_387 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
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node _T_388 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 103:86]
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node _T_389 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
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node _T_390 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 103:86]
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node _T_391 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
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node _T_392 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:86]
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node _T_393 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
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node _T_394 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_395 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_396 = mux(_T_390, _T_391, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_397 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_398 = or(_T_394, _T_395) @[Mux.scala 27:72]
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node _T_399 = or(_T_398, _T_396) @[Mux.scala 27:72]
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node _T_400 = or(_T_399, _T_397) @[Mux.scala 27:72]
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wire _T_401 : UInt<32> @[Mux.scala 27:72]
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_T_401 <= _T_400 @[Mux.scala 27:72]
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node _T_402 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
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node _T_403 = eq(_T_402, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 104:77]
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node _T_404 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
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node _T_405 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
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node _T_406 = eq(_T_405, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 104:77]
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node _T_407 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
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node _T_408 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
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node _T_409 = eq(_T_408, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 104:77]
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node _T_410 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
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node _T_411 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
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node _T_412 = eq(_T_411, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 104:77]
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node _T_413 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
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node _T_414 = mux(_T_403, _T_404, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_415 = mux(_T_406, _T_407, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_416 = mux(_T_409, _T_410, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_417 = mux(_T_412, _T_413, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_418 = or(_T_414, _T_415) @[Mux.scala 27:72]
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node _T_419 = or(_T_418, _T_416) @[Mux.scala 27:72]
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node _T_420 = or(_T_419, _T_417) @[Mux.scala 27:72]
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wire _T_421 : UInt<32> @[Mux.scala 27:72]
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_T_421 <= _T_420 @[Mux.scala 27:72]
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node iccm_rd_data_pre = cat(_T_401, _T_421) @[Cat.scala 29:58]
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node _T_422 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 105:43]
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node _T_423 = bits(_T_422, 0, 0) @[el2_ifu_iccm_mem.scala 105:53]
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node _T_424 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
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node _T_425 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 105:89]
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node _T_426 = cat(_T_424, _T_425) @[Cat.scala 29:58]
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node _T_427 = mux(_T_423, _T_426, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 105:25]
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io.iccm_rd_data <= _T_427 @[el2_ifu_iccm_mem.scala 105:19]
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node _T_428 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:85]
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node _T_429 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:85]
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node _T_430 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:85]
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node _T_431 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:85]
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node _T_432 = mux(_T_428, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_433 = mux(_T_429, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_434 = mux(_T_430, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_435 = mux(_T_431, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_436 = or(_T_432, _T_433) @[Mux.scala 27:72]
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node _T_437 = or(_T_436, _T_434) @[Mux.scala 27:72]
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node _T_438 = or(_T_437, _T_435) @[Mux.scala 27:72]
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wire _T_439 : UInt<39> @[Mux.scala 27:72]
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_T_439 <= _T_438 @[Mux.scala 27:72]
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node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
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node _T_441 = eq(_T_440, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 107:79]
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node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
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node _T_443 = eq(_T_442, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 107:79]
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node _T_444 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
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node _T_445 = eq(_T_444, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 107:79]
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node _T_446 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
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node _T_447 = eq(_T_446, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 107:79]
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node _T_448 = mux(_T_441, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_449 = mux(_T_443, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_450 = mux(_T_445, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_451 = mux(_T_447, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_452 = or(_T_448, _T_449) @[Mux.scala 27:72]
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node _T_453 = or(_T_452, _T_450) @[Mux.scala 27:72]
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node _T_454 = or(_T_453, _T_451) @[Mux.scala 27:72]
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wire _T_455 : UInt<39> @[Mux.scala 27:72]
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_T_455 <= _T_454 @[Mux.scala 27:72]
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node _T_456 = cat(_T_439, _T_455) @[Cat.scala 29:58]
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|
io.iccm_rd_data_ecc <= _T_456 @[el2_ifu_iccm_mem.scala 106:23]
|
2020-10-06 22:30:06 +08:00
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