2020-09-07 16:25:23 +08:00
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package ifu
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2020-09-07 16:27:29 +08:00
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import lib._
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import chisel3._
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import chisel3.util._
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2020-09-07 16:25:23 +08:00
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2020-09-07 16:27:29 +08:00
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class el2_ifu_bp_ctl extends Module with el2_lib {
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val io = IO (new Bundle {
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val in = Input(UInt(32.W))
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2020-09-08 13:00:45 +08:00
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val in2 = Input(UInt(32.W))
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2020-09-07 16:27:29 +08:00
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val out = Output(UInt())
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})
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2020-09-08 13:00:45 +08:00
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io.out := el2_btb_ghr_hash(io.in,io.in2)
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2020-09-07 16:27:29 +08:00
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}
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2020-09-08 22:00:03 +08:00
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//object ifu_ic extends App {
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// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
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//}
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