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quasar/EL2_IC_DATA.fir

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Daily update
2020-09-10 15:04:38 +08:00
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit EL2_IC_DATA :
module EL2_IC_DATA :
input clock : Clock
input reset : UInt<1>
IFC bits rectified
2020-10-01 14:41:24 +08:00
output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip test_in : UInt<71>, test : UInt, test_port : UInt<71>[2][2]}
Daily update
2020-09-10 15:04:38 +08:00
Branch predictor done
2020-09-30 14:57:37 +08:00
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23]
io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 196:16]
io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 197:16]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
io.test <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 198:11]
node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 200:70]
node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 200:68]
Branch predictor done
2020-09-30 14:57:37 +08:00
node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15]
node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 200:94]
node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 201:70]
node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 201:68]
Branch predictor done
2020-09-30 14:57:37 +08:00
wire _T_6 : UInt<1>[2] @[el2_lib.scala 185:48]
_T_6[0] <= _T_5 @[el2_lib.scala 185:48]
_T_6[1] <= _T_5 @[el2_lib.scala 185:48]
I$ Almost done
2020-09-12 23:12:43 +08:00
node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 201:94]
IFC bits rectified
2020-10-01 16:05:22 +08:00
wire ic_bank_wr_data : UInt<71>[2] @[el2_ifu_ic_mem.scala 203:29]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
wire ic_rd_en_with_debug : UInt<1>
ic_rd_en_with_debug <= UInt<1>("h00")
node _T_8 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 206:45]
node _T_9 = bits(_T_8, 0, 0) @[el2_ifu_ic_mem.scala 206:66]
node _T_10 = cat(io.ic_debug_addr, UInt<2>("h00")) @[Cat.scala 29:58]
node ic_rw_addr_q = mux(_T_9, _T_10, io.ic_rw_addr) @[el2_ifu_ic_mem.scala 206:25]
node _T_11 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 208:38]
node _T_12 = add(_T_11, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 208:79]
node ic_rw_addr_q_inc = tail(_T_12, 1) @[el2_ifu_ic_mem.scala 208:79]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 210:78]
node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 210:113]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 210:38]
node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 210:17]
node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 210:78]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 210:113]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
node _T_20 = bits(_T_19, 0, 0) @[Bitwise.scala 72:15]
node _T_21 = mux(_T_20, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 210:38]
node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 210:17]
node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:76]
node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 211:111]
node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:76]
node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:111]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
node ic_debug_sel_sb = cat(_T_26, _T_24) @[Cat.scala 29:58]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 212:77]
node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, ic_bank_wr_data[0]) @[el2_ifu_ic_mem.scala 212:60]
node _T_30 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 212:77]
node _T_31 = and(_T_30, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
node _T_32 = bits(_T_31, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
node ic_sb_wr_data_1 = mux(_T_32, io.ic_debug_wr_data, ic_bank_wr_data[1]) @[el2_ifu_ic_mem.scala 212:60]
node _T_33 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
node _T_34 = bits(_T_33, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
node _T_36 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
node _T_37 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
node _T_38 = bits(_T_37, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
node _T_39 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
node _T_40 = eq(_T_39, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ic_mem.scala 215:98]
node _T_43 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
node _T_44 = bits(_T_43, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
node _T_45 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
node _T_46 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
node _T_49 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
node _T_50 = eq(_T_49, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
node _T_51 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ic_mem.scala 217:99]
node _T_53 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_54 = mux(_T_38, _T_42, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_55 = mux(_T_44, _T_45, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_56 = mux(_T_48, _T_52, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_57 = or(_T_53, _T_54) @[Mux.scala 27:72]
node _T_58 = or(_T_57, _T_55) @[Mux.scala 27:72]
node _T_59 = or(_T_58, _T_56) @[Mux.scala 27:72]
wire _T_60 : UInt<1> @[Mux.scala 27:72]
_T_60 <= _T_59 @[Mux.scala 27:72]
node _T_61 = and(_T_60, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
node _T_62 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
node _T_63 = bits(_T_62, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
node _T_65 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
node _T_66 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
node _T_68 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
node _T_69 = eq(_T_68, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
node _T_70 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ic_mem.scala 215:98]
node _T_72 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
node _T_74 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
node _T_75 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
node _T_77 = bits(_T_76, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
node _T_78 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
node _T_79 = eq(_T_78, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
node _T_80 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
node _T_81 = and(_T_79, _T_80) @[el2_ifu_ic_mem.scala 217:99]
node _T_82 = mux(_T_64, _T_65, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_67, _T_71, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_73, _T_74, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_77, _T_81, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = or(_T_82, _T_83) @[Mux.scala 27:72]
node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72]
node _T_88 = or(_T_87, _T_85) @[Mux.scala 27:72]
wire _T_89 : UInt<1> @[Mux.scala 27:72]
_T_89 <= _T_88 @[Mux.scala 27:72]
node _T_90 = and(_T_89, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
node ic_b_rden = cat(_T_90, _T_61) @[Cat.scala 29:58]
node _T_91 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 218:89]
node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 72:15]
node ic_b_sb_rden_0 = mux(_T_92, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_93 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 218:89]
Async reset done in IFC
2020-09-30 18:17:21 +08:00
node _T_94 = bits(_T_93, 0, 0) @[Bitwise.scala 72:15]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node ic_b_sb_rden_1 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_95 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
node _T_96 = or(_T_95, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_97 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
node _T_98 = or(_T_96, _T_97) @[el2_ifu_ic_mem.scala 220:43]
node _T_99 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
node _T_100 = or(_T_99, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_101 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
node _T_102 = or(_T_100, _T_101) @[el2_ifu_ic_mem.scala 220:43]
node ic_bank_way_clken_0 = cat(_T_98, _T_102) @[Cat.scala 29:58]
node _T_103 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
node _T_104 = or(_T_103, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_105 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
node _T_106 = or(_T_104, _T_105) @[el2_ifu_ic_mem.scala 220:43]
node _T_107 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
node _T_108 = or(_T_107, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
node _T_109 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
node _T_110 = or(_T_108, _T_109) @[el2_ifu_ic_mem.scala 220:43]
node ic_bank_way_clken_1 = cat(_T_106, _T_110) @[Cat.scala 29:58]
node _T_111 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 222:74]
node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 222:61]
node _T_113 = and(io.ic_debug_rd_en, _T_112) @[el2_ifu_ic_mem.scala 222:58]
node _T_114 = or(io.ic_rd_en, _T_113) @[el2_ifu_ic_mem.scala 222:38]
ic_rd_en_with_debug <= _T_114 @[el2_ifu_ic_mem.scala 222:23]
node _T_115 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 224:37]
node _T_116 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 224:71]
node _T_117 = eq(_T_116, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 224:77]
node _T_118 = and(_T_115, _T_117) @[el2_ifu_ic_mem.scala 224:56]
node _T_119 = and(_T_118, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 224:86]
node _T_120 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 224:124]
node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 224:110]
node ic_rw_addr_wrap = and(_T_119, _T_121) @[el2_ifu_ic_mem.scala 224:108]
node _T_122 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 226:40]
node _T_123 = bits(_T_122, 0, 0) @[el2_ifu_ic_mem.scala 226:58]
node _T_124 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 226:77]
node _T_125 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 227:21]
node _T_126 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 227:82]
node _T_127 = cat(_T_125, _T_126) @[Cat.scala 29:58]
node _T_128 = mux(_T_123, _T_124, _T_127) @[el2_ifu_ic_mem.scala 226:38]
node _T_129 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 228:17]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 226:34]
IFC bits rectified
2020-10-01 16:05:22 +08:00
ic_rw_addr_bank_q[0] <= _T_128 @[el2_ifu_ic_mem.scala 226:34]
ic_rw_addr_bank_q[1] <= _T_129 @[el2_ifu_ic_mem.scala 226:34]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 233:29]
ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 233:29]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node _T_130 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 234:43]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 234:30]
IFC bits rectified
2020-10-01 16:05:22 +08:00
ic_rw_addr_ff <= _T_130 @[el2_ifu_ic_mem.scala 234:30]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 235:38]
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 235:38]
reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 236:34]
ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 236:34]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node _T_131 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43]
node _T_132 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node ic_cacheline_wrap_ff = eq(_T_131, _T_132) @[el2_ifu_ic_mem.scala 238:84]
wire wb_dout : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 242:21]
Async reset done in IFC
2020-10-01 13:18:39 +08:00
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 243:21]
IFC bits rectified
2020-10-01 16:05:22 +08:00
wb_dout[0][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
node _T_133 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
node _T_134 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
node _T_137 = and(_T_135, _T_136) @[el2_ifu_ic_mem.scala 248:30]
node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
when _T_138 : @[el2_ifu_ic_mem.scala 248:64]
infer mport _T_139 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_139[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 248:64]
else : @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node _T_140 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_142 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
node _T_143 = and(_T_141, _T_142) @[el2_ifu_ic_mem.scala 250:36]
node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_144 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_145 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:32]
wb_dout[0][0] <= _T_145[0][0] @[el2_ifu_ic_mem.scala 251:21]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
wb_dout[0][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
node _T_146 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
node _T_147 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
node _T_150 = and(_T_148, _T_149) @[el2_ifu_ic_mem.scala 248:30]
node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
when _T_151 : @[el2_ifu_ic_mem.scala 248:64]
infer mport _T_152 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_152[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 248:64]
else : @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node _T_153 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_155 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
node _T_156 = and(_T_154, _T_155) @[el2_ifu_ic_mem.scala 250:36]
node _T_157 = bits(_T_156, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_157 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_158 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:32]
wb_dout[0][1] <= _T_158[1][0] @[el2_ifu_ic_mem.scala 251:21]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
wb_dout[1][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
node _T_159 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
node _T_160 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
node _T_163 = and(_T_161, _T_162) @[el2_ifu_ic_mem.scala 248:30]
node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
when _T_164 : @[el2_ifu_ic_mem.scala 248:64]
infer mport _T_165 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_165[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 248:64]
else : @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node _T_166 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
node _T_167 = eq(_T_166, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_168 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
node _T_169 = and(_T_167, _T_168) @[el2_ifu_ic_mem.scala 250:36]
node _T_170 = bits(_T_169, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_170 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_171 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:32]
wb_dout[1][0] <= _T_171[0][1] @[el2_ifu_ic_mem.scala 251:21]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
wb_dout[1][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
node _T_172 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
node _T_173 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
node _T_176 = and(_T_174, _T_175) @[el2_ifu_ic_mem.scala 248:30]
node _T_177 = bits(_T_176, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
when _T_177 : @[el2_ifu_ic_mem.scala 248:64]
infer mport _T_178 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
_T_178[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 248:64]
else : @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
node _T_179 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_181 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
node _T_182 = and(_T_180, _T_181) @[el2_ifu_ic_mem.scala 250:36]
node _T_183 = bits(_T_182, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_183 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_184 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:32]
wb_dout[1][1] <= _T_184[1][1] @[el2_ifu_ic_mem.scala 251:21]
IFC bits rectified
2020-10-01 14:41:24 +08:00
skip @[el2_ifu_ic_mem.scala 250:69]
IFC bits rectified
2020-10-01 16:05:22 +08:00
io.test_port[0][0] <= wb_dout[0][0] @[el2_ifu_ic_mem.scala 254:16]
io.test_port[0][1] <= wb_dout[0][1] @[el2_ifu_ic_mem.scala 254:16]
io.test_port[1][0] <= wb_dout[1][0] @[el2_ifu_ic_mem.scala 254:16]
io.test_port[1][1] <= wb_dout[1][1] @[el2_ifu_ic_mem.scala 254:16]
node _T_185 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_ic_mem.scala 255:43]
node ic_rd_hit_q = mux(_T_185, ic_debug_rd_way_en_ff, io.ic_rd_hit) @[el2_ifu_ic_mem.scala 255:24]
ic_bank_wr_data[0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 256:19]
ic_bank_wr_data[1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 256:19]
node _T_186 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 259:95]
node _T_188 = bits(_T_187, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
node _T_189 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
node _T_190 = eq(_T_189, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 259:95]
node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
node _T_192 = mux(_T_188, wb_dout[0][0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_193 = mux(_T_191, wb_dout[0][1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_194 = or(_T_192, _T_193) @[Mux.scala 27:72]
wire _T_195 : UInt<71> @[Mux.scala 27:72]
_T_195 <= _T_194 @[Mux.scala 27:72]
node _T_196 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
node _T_197 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
node _T_198 = tail(_T_197, 1) @[el2_ifu_ic_mem.scala 260:102]
node _T_199 = eq(_T_196, _T_198) @[el2_ifu_ic_mem.scala 260:95]
node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
node _T_201 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
node _T_202 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
node _T_203 = tail(_T_202, 1) @[el2_ifu_ic_mem.scala 260:102]
node _T_204 = eq(_T_201, _T_203) @[el2_ifu_ic_mem.scala 260:95]
node _T_205 = bits(_T_204, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
node _T_206 = mux(_T_200, wb_dout[0][0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_207 = mux(_T_205, wb_dout[0][1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_208 = or(_T_206, _T_207) @[Mux.scala 27:72]
wire _T_209 : UInt<71> @[Mux.scala 27:72]
_T_209 <= _T_208 @[Mux.scala 27:72]
node wb_dout_way_pre_0 = cat(_T_195, _T_209) @[Cat.scala 29:58]
node _T_210 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 259:95]
node _T_212 = bits(_T_211, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
node _T_213 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 259:95]
node _T_215 = bits(_T_214, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
node _T_216 = mux(_T_212, wb_dout[1][0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_217 = mux(_T_215, wb_dout[1][1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72]
wire _T_219 : UInt<71> @[Mux.scala 27:72]
_T_219 <= _T_218 @[Mux.scala 27:72]
node _T_220 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
node _T_221 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
node _T_222 = tail(_T_221, 1) @[el2_ifu_ic_mem.scala 260:102]
node _T_223 = eq(_T_220, _T_222) @[el2_ifu_ic_mem.scala 260:95]
node _T_224 = bits(_T_223, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
node _T_225 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
node _T_226 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
node _T_227 = tail(_T_226, 1) @[el2_ifu_ic_mem.scala 260:102]
node _T_228 = eq(_T_225, _T_227) @[el2_ifu_ic_mem.scala 260:95]
node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
node _T_230 = mux(_T_224, wb_dout[1][0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_231 = mux(_T_229, wb_dout[1][1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_232 = or(_T_230, _T_231) @[Mux.scala 27:72]
wire _T_233 : UInt<71> @[Mux.scala 27:72]
_T_233 <= _T_232 @[Mux.scala 27:72]
node wb_dout_way_pre_1 = cat(_T_219, _T_233) @[Cat.scala 29:58]
node _T_234 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 262:78]
node _T_235 = eq(_T_234, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 262:83]
node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_ic_mem.scala 262:91]
node _T_237 = bits(wb_dout_way_pre_0, 63, 0) @[el2_ifu_ic_mem.scala 262:117]
node _T_238 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 263:45]
node _T_239 = eq(_T_238, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 263:50]
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_ic_mem.scala 263:58]
node _T_241 = bits(wb_dout_way_pre_0, 86, 71) @[el2_ifu_ic_mem.scala 263:88]
node _T_242 = bits(wb_dout_way_pre_0, 63, 16) @[el2_ifu_ic_mem.scala 263:114]
node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58]
node _T_244 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 264:45]
node _T_245 = eq(_T_244, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 264:50]
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_ic_mem.scala 264:58]
node _T_247 = bits(wb_dout_way_pre_0, 102, 71) @[el2_ifu_ic_mem.scala 264:88]
node _T_248 = bits(wb_dout_way_pre_0, 63, 32) @[el2_ifu_ic_mem.scala 264:115]
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
node _T_250 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 265:45]
node _T_251 = eq(_T_250, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 265:50]
node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_ic_mem.scala 265:58]
node _T_253 = bits(wb_dout_way_pre_0, 119, 71) @[el2_ifu_ic_mem.scala 265:88]
node _T_254 = bits(wb_dout_way_pre_0, 63, 48) @[el2_ifu_ic_mem.scala 265:115]
node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58]
node _T_256 = mux(_T_236, _T_237, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_257 = mux(_T_240, _T_243, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_258 = mux(_T_246, _T_249, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_259 = mux(_T_252, _T_255, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_260 = or(_T_256, _T_257) @[Mux.scala 27:72]
node _T_261 = or(_T_260, _T_258) @[Mux.scala 27:72]
node _T_262 = or(_T_261, _T_259) @[Mux.scala 27:72]
wire wb_dout_way_0 : UInt<65> @[Mux.scala 27:72]
wb_dout_way_0 <= _T_262 @[Mux.scala 27:72]
node _T_263 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 262:78]
node _T_264 = eq(_T_263, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 262:83]
node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_ic_mem.scala 262:91]
node _T_266 = bits(wb_dout_way_pre_1, 63, 0) @[el2_ifu_ic_mem.scala 262:117]
node _T_267 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 263:45]
node _T_268 = eq(_T_267, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 263:50]
node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_ic_mem.scala 263:58]
node _T_270 = bits(wb_dout_way_pre_1, 86, 71) @[el2_ifu_ic_mem.scala 263:88]
node _T_271 = bits(wb_dout_way_pre_1, 63, 16) @[el2_ifu_ic_mem.scala 263:114]
node _T_272 = cat(_T_270, _T_271) @[Cat.scala 29:58]
node _T_273 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 264:45]
node _T_274 = eq(_T_273, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 264:50]
node _T_275 = bits(_T_274, 0, 0) @[el2_ifu_ic_mem.scala 264:58]
node _T_276 = bits(wb_dout_way_pre_1, 102, 71) @[el2_ifu_ic_mem.scala 264:88]
node _T_277 = bits(wb_dout_way_pre_1, 63, 32) @[el2_ifu_ic_mem.scala 264:115]
node _T_278 = cat(_T_276, _T_277) @[Cat.scala 29:58]
node _T_279 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 265:45]
node _T_280 = eq(_T_279, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 265:50]
node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_ic_mem.scala 265:58]
node _T_282 = bits(wb_dout_way_pre_1, 119, 71) @[el2_ifu_ic_mem.scala 265:88]
node _T_283 = bits(wb_dout_way_pre_1, 63, 48) @[el2_ifu_ic_mem.scala 265:115]
node _T_284 = cat(_T_282, _T_283) @[Cat.scala 29:58]
node _T_285 = mux(_T_265, _T_266, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_269, _T_272, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_275, _T_278, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_281, _T_284, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = or(_T_285, _T_286) @[Mux.scala 27:72]
node _T_290 = or(_T_289, _T_287) @[Mux.scala 27:72]
node _T_291 = or(_T_290, _T_288) @[Mux.scala 27:72]
wire wb_dout_way_1 : UInt<65> @[Mux.scala 27:72]
wb_dout_way_1 <= _T_291 @[Mux.scala 27:72]
node _T_292 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 267:92]
node wb_dout_way_with_premux_0 = mux(_T_292, io.ic_premux_data, wb_dout_way_0) @[el2_ifu_ic_mem.scala 267:69]
node _T_293 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 267:92]
node wb_dout_way_with_premux_1 = mux(_T_293, io.ic_premux_data, wb_dout_way_1) @[el2_ifu_ic_mem.scala 267:69]
node _T_294 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 269:71]
node _T_295 = or(_T_294, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 269:75]
node _T_296 = bits(_T_295, 0, 0) @[el2_ifu_ic_mem.scala 269:100]
node _T_297 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 269:71]
node _T_298 = or(_T_297, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 269:75]
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_ic_mem.scala 269:100]
node _T_300 = mux(_T_296, wb_dout_way_with_premux_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_299, wb_dout_way_with_premux_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = or(_T_300, _T_301) @[Mux.scala 27:72]
wire ic_rd_data : UInt<65> @[Mux.scala 27:72]
ic_rd_data <= _T_302 @[Mux.scala 27:72]
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2020-09-10 15:04:38 +08:00