2020-09-07 16:27:29 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_bp_ctl :
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module el2_ifu_bp_ctl :
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input clock : Clock
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input reset : UInt<1>
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2020-09-08 13:00:45 +08:00
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output io : {flip in : UInt<32>, flip in2 : UInt<32>, out : UInt}
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2020-09-07 16:27:29 +08:00
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2020-09-08 22:00:03 +08:00
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node _T = bits(io.in, 9, 2) @[el2_lib.scala 35:30]
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node _T_1 = bits(io.in2, 7, 0) @[el2_lib.scala 35:53]
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node _T_2 = xor(_T, _T_1) @[el2_lib.scala 35:48]
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2020-09-08 13:00:45 +08:00
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io.out <= _T_2 @[el2_ifu_bp_ctl.scala 13:10]
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2020-09-07 16:27:29 +08:00
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